CN103326677B - The control method of audio-frequency power amplifier and audio-frequency power amplifier - Google Patents

Abstract

The invention provides the control method of a kind of audio-frequency power amplifier and audio-frequency power amplifier. The present invention can make audio-frequency power amplifier realize slicing by the DC current gain that regulates self to suppress and help peripheral components without relending, thereby can reduce unnecessary noise that peripheral components introduces, can also reduce peripheral circuit cost and reduce the complexity of design; And, whether the present invention there is slicing and determines when by turning down DC current gain and open slicing and suppress with this by the detection of digital audio and video signals of output is judged in this digital audio and video signals, suppress to be opened by mistake to open thereby can reduce owing to detecting the slicing that error causes; And, whether the present invention has also disappeared by the slicing that the simulated audio signal of input is judged to existence and has determined when by heightening DC current gain and discharge slicing and suppress with this, thereby can avoid cannot all being suppressed owing to discharging the improper slicing that causes of moment suppressing.

Description

The control method of audio-frequency power amplifier and audio-frequency power amplifier

Technical field

The present invention relates to Audio power amplifier technology, particularly taking simulated audio signal as input, numeralAudio signal is the audio-frequency power amplifier of output and the control method of this audio-frequency power amplifier.

Background technology

The effect of audio-frequency power amplifier is that the audio signal of input is amplified, also amplified by outputAfter audio signal drive passive acoustic element (as loudspeaker, earphone) sounding.

According to dissimilar (numeral or the simulation) of the audio signal of input and output, Audio power amplifierDevice can adopt different mode of operations. Wherein, D class mode of operation is a kind of common mode of operation,The audio-frequency power amplifier that adopts this mode of operation taking simulated audio signal as input, digital audio and video signals asOutput, audio-frequency power amplifier as herein described mainly refers to and adopts the audio power of D class mode of operation to putLarge device.

Fig. 1 is the example arrangement schematic diagram of a kind of audio-frequency power amplifier of the prior art. As Fig. 1The audio-frequency power amplifier 10 of shown employing D class mode of operation comprises: order is connected on audio powerFiltration module 11 between audio input end IN and the audio output OUT of amplifier 10, comparison mouldPiece 12 and power output module 13, that is, the filtration module 11 of order series connection, comparison module 12,And power output module 13 forms the signal path of this audio-frequency power amplifier 10.

Filtration module 11 is for utilizing a biasing voltage signal Vb (by audio-frequency power amplifier 10 insideProvide or introduce from audio-frequency power amplifier 10 is outside) and the DAB exported of audio output OUTSignal Dig carries out LPF and passes through the simulated audio signal Ana of audio input end IN inputThis LPF obtains a filtering signal Vi, and, for audio-frequency power amplifier 10 provides fixing straightFlow enhancement;

Comparison module 12 is for (being put above-mentioned filtering signal Vi and a carrier signal Vs by audio powerLarge device 10 inside provide or introduce and be generally periodically triangular wave from audio-frequency power amplifier 10 outsidesOr sawtooth signal) compare and relatively obtain a pulse signal Vpwm by this;

Power output module 13 drives audio output OUT for the pulse signal Vpwm according to above-mentionedOutputting digital audio signal Dig, and the power of the digital audio and video signals Dig of output is greater than analogue audio frequency letterNumber Ana.

As above visible, the audio-frequency power amplifier 10 of employing D class mode of operation can be by the simulation of inputAudio signal Ana is converted to more powerful digital audio and video signals Dig output, still, and due to this audio frequencyThe DC current gain that power amplifier 10 is provided by filtration module 11 is changeless and to analogue audio frequencyThe tolerance of the signal amplitude of signal Ana is limited, therefore, if the simulated audio signal Ana of inputSignal amplitude is excessive, just easily causes the digital audio and video signals Dig of output to occur slicing (Clipping)Distortion. Wherein, clipping distortion refers to: in the time of overflow, this signal exceedes one of signal strength thresholdPart can be eliminated and be formed slicing, thereby because the formation of slicing causes this distorted signals.

There is clipping distortion in the digital audio and video signals Dig exporting for fear of audio-frequency power amplifier 10,Prior art can be equipped with a preamplifier for audio-frequency power amplifier 10 conventionally.

Fig. 2 is the annexation of the preamplifier of audio-frequency power amplifier as shown in Figure 1 and its outfitSchematic diagram. As shown in Figure 2:

One preamplifier 20 is connected on the front end of the audio input end IN of audio-frequency power amplifier 10,First pass through preamplifier so that should be directly inputted into the simulated audio signal Ana of audio input end IN20 process, and then, input to sound through preamplifier 20 simulated audio signal Ana ' after treatment againFrequency input terminal IN;

And, also need to detect the M signal (example of certain point in the signal path of audio-frequency power amplifier 10The pulse signal Vpwm obtaining as comparison module 12) and predict audio output by this detectionIn the digital audio and video signals Dig of OUT output, whether there is slicing; When doping while there is slicing, prepositionAmplifier 20 will open slicing suppress, to treat the simulated audio signal that inputs to audio input end INAna suppresses slicing processing, thereby makes to input in audio input end IN simulated audio signal Ana ' notWith the slicing existing in simulated audio signal Ana, and then after one period of fixing time delay,Front storing amplifier 20 automatically discharges slicing again and suppresses, inputs to audio input end IN's to stop treatingThe inhibition slicing processing of simulated audio signal Ana.

Adopt as shown in Figure 2 suppress the mode of slicing with preamplifier 20, although can be oneDetermine to avoid the digital audio and video signals Dig that audio-frequency power amplifier 10 is exported to occur clipping distortion in degree, but, because audio-frequency power amplifier 10 itself does not still still have the function that suppresses slicing, therefore willCause following problem to occur:

1, the existence of preamplifier 20 can be introduced unnecessary noise and can increase peripheral circuitThe complexity that this and increase design;

2, the waveform of the digital audio and video signals of M signal and audio-frequency amplifier 10 final outputs there are differences,Therefore, preamplifier 20 is only by judging in the digital audio and video signals of output the detection of M signalWhether there is slicing and determine and open the moment that slicing suppresses with this, can have certain error, enterAnd cause slicing to suppress to be opened by mistake to open;

3, suppress after slicing be only determine time delay of fixing discharge moment of suppressing andWhether do not disappear and determine exactly the moment that discharges inhibition by detection slicing, therefore, just easily leadCausing part slicing cannot be suppressed, for example, exceedes the situation of this time delay for the slicing duration,After will causing discharging inhibition, still there is not yet disappearance but not repressed slicing.

In like manner, the control method suppressing for audio-frequency power amplifier 10 being realized to slicing in prior artAlso need to realize by the peripheral components of audio-frequency power amplifier 10, and this control method also onlyTo predict by detecting M signal in the digital audio and video signals Dig of audio output OUT output to beNoly there is slicing and doping while there is slicing inputing to the analogue audio frequency letter of audio input end INNumber Ana suppresses slicing processing, and, only suppress according to determining fixing time delay to dischargeThe moment of slicing. Therefore the adjusting, suppressing for realizing audio-frequency power amplifier 10 slicings in prior artMethod also can cause the problem of mentioning to occur above.

Summary of the invention

In view of this, the invention provides the adjusting side of a kind of audio-frequency power amplifier and audio-frequency power amplifierMethod.

According to a first aspect of the invention, provide a kind of audio-frequency power amplifier, this audio-frequency power amplifierComprise: order is connected on the filter between audio input end and the audio output of described audio-frequency power amplifierMode piece, comparison module and power output module, also comprise connect described audio input end, described inThe slicing of audio output and described filtration module suppresses module;

Described filtration module is for utilizing the numeral of a biasing voltage signal and the output of described audio outputAudio signal the simulated audio signal of described audio input end input is carried out to LPF and pass through described inLPF obtains a filtering signal, and, for described audio-frequency power amplifier provides adjustable direct currentGain;

Described comparison module for described filtering signal and a carrier signal are compared and pass through described inRelatively obtain a pulse signal;

Described power output module is for driving described audio output output number according to described pulse signalWord audio signal, and the power of described digital audio and video signals is greater than described simulated audio signal;

Described slicing suppresses module in the time being tested with slicing from described digital audio and video signals and existing,The described DC current gain that described filtration module is provided is turned down; And, from described simulated audio signalWhen the slicing that detects existence has disappeared, the described DC current gain that described filtration module is provided is heightened.

According to a second aspect of the invention, provide a kind of control method of audio-frequency power amplifier, this adjustingIt is adjustable that method arranges the DC current gain of described audio-frequency power amplifier, and this control method is included in instituteState the following steps of carrying out in audio-frequency power amplifier:

Step a, from the digital audio and video signals of described audio-frequency power amplifier output, detect and whether have slicingExist, and in the time being tested with slicing existing from described digital audio and video signals, described DC current gain is adjustedLow;

Step b, from input the simulated audio signal of described audio-frequency power amplifier, detect and whether have existenceSlicing disappear, and in the time that the slicing that detects existence from described simulated audio signal has disappeared, willDescribed DC current gain is heightened.

As above visible, the audio-frequency power amplifier in the present invention can come by the DC current gain that regulates selfRealize slicing and suppress, and the audio-frequency power amplifier in the present invention can also be by the numeral to outputThe detection of audio signal is judged and in this digital audio and video signals, whether is had slicing and what determined with thisTime by turn down DC current gain open slicing suppress, and, by input simulated audio signal comeWhether the slicing of judging existence has disappeared and has determined when by heightening DC current gain and discharge with thisSlicing suppresses, and thus, the audio-frequency power amplifier in the present invention can produce following technique effect:

1, because the audio-frequency power amplifier in the present invention itself has possessed the function that suppresses slicing, therefore,Than the mode that preamplifier is set in prior art, the audio-frequency power amplifier in the present invention withoutCan realize slicing by peripheral components and suppress, thereby not only can reduce unnecessary the making an uproar that peripheral components is introducedSound, can also reduce peripheral circuit cost and reduce design complexity;

2, owing to being based on this numeral while whether there is slicing in the digital audio and video signals that detects outputAudio signal itself, thereby than the mode detecting according to M signal in prior art, in the present inventionAudio-frequency power amplifier can reduce owing to detecting the slicing that causes of error and suppress to be opened by mistake to open;

3, be by whether detect slicing from the simulated audio signal of input owing to discharging the moment of suppressingDisappear to determine, thereby determined when release with the delay time of fixing in prior artThe mode suppressing, it is improper owing to discharging the moment of suppressing that the audio-frequency power amplifier in the present invention can be avoidedAnd cause slicing all to be suppressed.

Similarly, the control method of sound intermediate frequency power amplifier of the present invention can make audio-frequency power amplifier logicalThe DC current gain that overregulates self is realized slicing inhibition and helps peripheral components without relending, and in realityWhen existing slicing suppresses, can judge this numeral by the detection of the digital audio and video signals to output equallyIn audio signal, whether there is slicing and determine and open the moment that slicing suppresses with this, and, pass throughWhether the slicing of the simulated audio signal of input being judged to existence has disappeared and has determined release with thisIn the moment that slicing suppresses, therefore, the control method of sound intermediate frequency power amplifier of the present invention also can produceThe technique effect of stating.

Brief description of the drawings

Fig. 1 is the example arrangement schematic diagram of a kind of audio-frequency power amplifier of the prior art;

Fig. 2 is the annexation of the preamplifier of audio-frequency power amplifier as shown in Figure 1 and its outfitSchematic diagram;

Fig. 3 is the example arrangement schematic diagram of the audio-frequency power amplifier in the embodiment of the present invention;

Fig. 4 is for audio-frequency power amplifier is as shown in Figure 3 in the time that its signal path has adopted a kind of preferred structureSchematic diagram;

Fig. 5 is that the slicing in audio-frequency power amplifier suppresses a kind of preferred structure of module as shown in Figure 3Schematic diagram;

Fig. 6 is that the digital audio and video signals of audio-frequency power amplifier in embodiment of the present invention output is cut occurringSchematic diagram during ripple;

Fig. 7 is that the simulated audio signal of the audio-frequency power amplifier input in the embodiment of the present invention is tied at slicingSchematic diagram when bundle;

Fig. 8 is that the timing enable circuits that slicing suppresses in module as shown in Figure 5 coordinates with slicing testing circuitThe sequential schematic diagram producing;

Fig. 9 is that the timing enable circuits that slicing suppresses in module as shown in Figure 5 coordinates with release testing circuitThe sequential schematic diagram producing;

Figure 10 is that slicing suppresses the preferred structure schematic diagram of slicing testing circuit of module as shown in Figure 5;

Figure 11 is the schematic diagram of an instantiation of the preferred structure of slicing testing circuit as shown in figure 10;

Figure 12 is that slicing suppresses the alternative construction schematic diagram of slicing testing circuit of module as shown in Figure 5;

Figure 13 is that slicing suppresses the preferred structure schematic diagram of release testing circuit of module as shown in Figure 5;

Figure 14 is the schematic diagram that discharges as shown in figure 13 an instantiation of the preferred structure of testing circuit;

Figure 15 is that slicing suppresses the alternative construction schematic diagram of release testing circuit of module as shown in Figure 5;

Figure 16 is that slicing suppresses the preferred structure schematic diagram of timing enable circuits of module as shown in Figure 5;

Figure 17 is the schematic diagram of an instantiation of the preferred structure of timing enable circuits as shown in figure 16;

Figure 18 is that slicing suppresses the alternative construction schematic diagram of timing enable circuits of module as shown in Figure 5.

Detailed description of the invention

For making object of the present invention, technical scheme and advantage clearer, develop simultaneously referring to accompanying drawingEmbodiment, the present invention is described in more detail.

Fig. 3 is the example arrangement schematic diagram of the audio-frequency power amplifier in the embodiment of the present invention.

Refer to Fig. 3, the audio-frequency power amplifier 30 in the present embodiment comprises: order is connected on audio frequency meritFiltration module 31 between audio input end IN and the audio output OUT of rate amplifier 30, comparisonModule 32 and power output module 33, that is, the filtration module 31 of order series connection, comparison module 32,And power output module 33 forms the signal path of audio-frequency power amplifier 30;

Please, again referring to Fig. 3, the audio-frequency power amplifier 30 in the present embodiment also comprises: connect audio frequency inputThe slicing of end IN, audio output OUT and filtration module 31 suppresses module 34.

Filtration module 31 is for utilizing a biasing voltage signal Vb (by audio-frequency power amplifier 30 insideProvide or introduce from audio-frequency power amplifier 30 is outside) and the DAB exported of audio output OUTSignal Dig carries out LPF, also to the simulated audio signal Ana of audio input end input IN inputObtain a filtering signal Vi by LPF, and, for audio-frequency power amplifier 30 provides adjustableDC current gain Gain.

Comparison module 32 for by filtering signal Vi and a carrier signal Vs (by audio-frequency power amplifier30 inside provide or introduce and be generally periodically triangular wave or saw from audio-frequency power amplifier 30 outsidesTooth ripple signal) compare and relatively obtain a pulse signal Vpwm by this.

Power output module 33 is for driving audio output OUT output number according to pulse signal VpwmWord audio signal Dig, and the power of digital audio and video signals Dig is greater than simulated audio signal Ana.

Slicing suppresses module 34 in the time being tested with slicing from digital audio and video signals Dig and existing,The DC current gain Gain that filtration module 31 is provided turns down; And, from simulated audio signal AnaWhen the slicing that detects existence has disappeared, the DC current gain Gain that filtration module 31 is provided heightens.

Visible, the audio-frequency power amplifier 30 in the present embodiment can be by regulating the DC current gain of selfGain realizes slicing and suppresses, and, can also be by the detection of the digital audio and video signals Dig to outputJudge and in this digital audio and video signals Dig, whether have slicing and determine when by turning down with thisDC current gain Gain opens slicing and suppresses, and, by the simulated audio signal Ana of input is sentencedWhether the slicing of existence of breaking has disappeared and has determined when by heightening DC current gain Gain and release with thisPut slicing and suppress, thus, the audio-frequency power amplifier 30 in the present embodiment can produce following technology effectReally:

1, because this audio-frequency power amplifier 30 itself has possessed the function that suppresses slicing, therefore, compareThe mode of preamplifier is set in prior art, and this audio-frequency power amplifier 30 is without by peripheral devicePart can realize slicing suppress, thereby not only can reduce peripheral components introduce unnecessary noise, can alsoReduce peripheral circuit cost and reduce the complexity of design;

2, because whether this audio-frequency power amplifier 30 is deposited in the digital audio and video signals Dig that detects outputIn the time of slicing, be based on this digital audio and video signals Dig itself, thus than in prior art according inBetween the mode of signal detection, this audio-frequency power amplifier 30 can reduce owing to detecting cutting that error causesRipple suppresses to be opened by mistake to open; And, for the detection that whether has slicing, from digital audio and video signals DigCan be than obtain more easily testing result accurately from simulated audio signal Ana;

3, be by the analogue audio frequency from input because this audio-frequency power amplifier 30 discharges the moment of suppressingIn signal Ana, detect whether slicing disappeared to determine, thus than in prior art to fixDelay time determines when the mode that discharges inhibition, and this audio-frequency power amplifier 30 can be avoided owing to releasingMoment of putting inhibition is improper and cause slicing all to be suppressed; And, whether disappear for slicingDetection, from simulated audio signal Ana can than from digital audio and video signals Dig more easilyArrive testing result accurately.

In addition, in actual applications, slicing suppresses module 34 can be at every turn from digital audio and video signals DigIn when being tested with slicing and existing, the DC current gain Gain that filtration module 31 is provided turns down a gear;And, in the time that the slicing that at every turn detects existence from simulated audio signal Ana has disappeared, by filtering mouldThe DC current gain Gain that piece 31 provides progressively heightens to the step of high tap position and each step of progressively heighteningLength is a gear; Wherein, in the adjustable range that each gear is described DC current gain, mark off in advanceA corresponding interval Δ Gain.

Because the audio-frequency power amplifier 30 in the present embodiment is all to adopt to the adjusting of DC current gain GainThe mode of gradual change realizes, thus output digital audio and video signals Dig in slicing little by little disappearedAfter disappearing, also progressively recovers remove and slicing, thereby, except above-mentioned technique effect, thisThe progressive formation of sample is difficult for by hearing perception, and then can produce the defeated of this audio-frequency power amplifier 30 of raisingThe further effect of the sense of hearing of the digital audio and video signals Dig going out.

Fig. 4 is for audio-frequency power amplifier is as shown in Figure 3 in the time that its signal path has adopted a kind of preferred structureSchematic diagram. As shown in Figure 4, the filtration module 31 in the signal path of audio-frequency power amplifier 30,Comparison module 32 and power output module 33 all can have preferred structure separately.

In the preferred structure shown in Fig. 4, filtration module 31 comprises: operational amplifier A MP0, filteringCapacitor C f, feedback resistance Rf and adjustable resistance Ri;

The positive input of operational amplifier A MP0 receives biasing voltage signal Vb, reverse input end connectsReceive and go out filtering from simulated audio signal Ana, the output of audio input end IN to comparison module defeated 32Signal Vi;

Filter capacitor Cf is connected on reverse input end and the operational amplifier A MP0 of operational amplifier A MP0Output between;

Feedback resistance Rf is connected on reverse input end and the audio output OUT of operational amplifier A MP0Between;

Adjustable resistance Ri be connected on audio input end IN and operational amplifier A MP0 reverse input end itBetween and be controlled by slicing suppress module 34.

Wherein:

The resistance of the capacitance of filter capacitor Cf and feedback resistance Rf can determine cutting of filtration module 31Only frequency f_CSize,K is equivalent gain constant (this equivalence of filtration module 31The setting of gain constant K belongs to prior art, repeats no more herein);

The resistance of feedback resistance Rf and the ratio of the resistance of adjustable resistance Ri can determine that filtration module 31 carriesThe size of the DC current gain Gain of confession,Correspondingly, if suppressing module 34, selects gradually slicingThe adjusting of change mode, can be divided into the adjustable extent of DC current gain Gain several interval Δ Gain,Each gear in corresponding each interval while getting final product adjusted DC current gain Gain;

And, because the resistance of feedback resistance Rf is changeless, thereby suppress module 34 by slicingOnly can realize DC current gain Gain's according to the gear of dividing by the resistance that regulates adjustable resistance RiRegulate; Correspondingly, the adjustable extent of DC current gain Gain is come really by the adjustable extent of adjustable resistance RiFixed, and, if slicing suppresses the adjusting that module 34 is selected gradual manner, can be by adjustable resistance RiAdjustable extent be divided into several interval Δ Ri, can utilize the interval Δ Ri of adjustable resistance Ri to controlSeveral interval Δ Gain of the DC current gain Gain of corresponding each gear respectively.

Visible, utilize adjustable resistance Ri's for the preferred structure of the filtration module 31 shown in Fig. 4Resistance can realize the adjusting of DC current gain Gain and the change in resistance of adjustable resistance Ri can not have influence onThe cut-off frequency f of filtration module 31_C, thereby this preferred structure of filtration module 31 is being realized DC current gainAdjustable while of Gain can also be guaranteed the steady operation of signal path.

Certainly, in actual applications, as long as follow the operation principle of filtration module 31, filtration module 31Also can adopt other alternative construction to be replaced.

In the preferred structure shown in Fig. 4, comparison module 32 comprises a comparator C MP0, this comparatorCMP0 Yi road input accept filter signal Vi, another road input reception carrier signal Vs, a roadOutput produces pulse signal Vpwm.

Wherein, the preferred structure of the comparison module 32 shown in Fig. 4 with comparator C MP0 is justAccept filter signal Vi, negative input end reception carrier signal Vs of input is example, the pulse obtaining thusThe effective impulse of signal Vpwm is high level pulse.

In practical application, the operation principle of the comparison module 32 of understanding based on those skilled in the art,Comparison module 32 can also adopt other alternative construction to be replaced; The operation principle of comparison module 32 canWith with reference to prior art, thereby be no longer described in further detail for comparison module 32 herein.

In the preferred structure shown in Fig. 4, power output module 33 comprises PMOS pipe Mp0 and NMOSPipe Mn0 and driving logical device D0;

The grid of PMOS pipe Mp0 is controlled by driving logical device D0, source electrode by a voltage source V DD0Connection audio output OUT draws high, drains;

The grid of NMOS pipe Mn0 is controlled by driving logical device D0, source ground, drain electrode connection soundFrequently output OUT;

Drive logical device D0 for control PMOS pipe Mp0 and NMOS according to pulse signal VpwmThe open and-shut mode of pipe Mn0 is so that audio output OUT outputting digital audio signal Dig, and numeralThe power of audio signal Dig is greater than simulated audio signal Ana.

Wherein, the preferred structure of the power output module 33 shown in Fig. 4 is the digital sounds that obtainFrequently the effective impulse of signal Dig is that high level pulse is example.

In practical application, the work of the power output module 33 of understanding based on those skilled in the art is formerReason, power output module 33 can also adopt other alternative construction to be replaced; Power output module 33Operation principle can be with reference to prior art, thereby no longer enter one for power output module 33 hereinThe detailed description of step.

As above visible, the filter in the signal path of the audio-frequency power amplifier 30 based on going out as shown in Figure 4The preferred structure of mode piece 31, comparison module 32 and power output module 33, not only can realizeThe DC current gain Gain of audio-frequency power amplifier 30 is adjustable and realize slicing with this and suppress, and can also guaranteeThe normal work of signal path is unaffected.

Fig. 5 is that the slicing in audio-frequency power amplifier suppresses a kind of preferred structure of module as shown in Figure 3Schematic diagram. As shown in Figure 5, slicing suppresses the situation that module 34 selects gradual manner to regulate, the present embodimentIn the slicing that has of audio-frequency power amplifier 30 suppress module 34 and can comprise: slicing testing circuit341, discharge testing circuit 342, timing enable circuits 343 and bidirectional counter 344.

Fig. 6 is that the digital audio and video signals of audio-frequency power amplifier in embodiment of the present invention output is cut occurringSchematic diagram during ripple. Please in referring to Fig. 5 again in conjunction with Fig. 6:

For detection of the pulsewidth of the effective impulse in digital audio and video signals Dig whether slicing testing circuit 341Reach and represent this effective impulse pulsewidth duration threshold value Th_a that is slicing, and according to this testing result andAn inhibition enable signal Ta who receives produces one and suppresses cue Va; Wherein, this inhibition enables letterNumber Ta represent whether to allow by inhibition cue Va be set to effectively, this inhibition cue Va representsWhether need DC current gain Gain to turn down a gear;

From Fig. 6, can obviously find out the effective impulse of digital audio and video signals Dig during there is slicingPulsewidth W_clipping can obviously be greater than the pulsewidth of the effective impulse while there is not slicing and can be greater thanAbove-mentioned pulsewidth duration threshold value Th_a;

Therefore, reach pulsewidth duration threshold value Th_a if be tested with the pulsewidth of any effective impulse, can recognizeFor this effective impulse is slicing, therefore, by the detection of the pulsewidth to effective impulse, can detect numeralIn audio signal Dig, whether there is slicing, correspondingly:

If being tested with the pulsewidth of any effective impulse reaches pulsewidth duration threshold value Th_a and suppresses to enable letterNumber Ta is effective, suppresses cue Va and is set to effectively, to represent from digital audio and video signals DigBeing tested with slicing exists and DC current gain Gain need to be turned down to a gear;

Otherwise (pulsewidth that for example occurs effective impulse does not reach pulsewidth duration threshold value Th_a, suppresses to enable letterNumber invalid any one situation such as grade of Ta), suppress cue Va remain invalid, to represent not from numberIn word audio signal Dig, be tested with slicing exist and without DC current gain Gain being turned down to a gear.

In practical application, according to empirical value, pulsewidth duration threshold value Th_a can be set and be greater than carrier signalA carrier cycle of Vs. Certainly, those skilled in the art also can adopt other empirical value, orAccording to requiring and determine pulsewidth duration threshold by other means for the difference that suppresses slicing in practical applicationValue Th_a.

Fig. 7 is that the simulated audio signal of the audio-frequency power amplifier input in the embodiment of the present invention is tied at slicingSchematic diagram when bundle. Please in referring to Fig. 5 again in conjunction with Fig. 7:

Discharge testing circuit 342 for detection of the amplitude of simulated audio signal Ana lower than an amplitude with reference to electricityPress signal Vref_r (to be provided or from audio-frequency power amplifier 30 outsides by audio-frequency power amplifier 30 insideIntroduce) duration whether reach and represent the threshold value of the duration by a narrow margin Th_r that disappeared of slicing, and according to inspectionA release enable signal Tr who surveys result and inhibition cue Va and receive produces a release and carriesShow signal Vr; Wherein, whether this release enable signal Tr represents to allow release cue Vr is set toEffectively, whether this release cue Vr represents to need DC current gain Gain is heightened to a gear;

From Fig. 7, can obviously find out that simulated audio signal Ana is after the crest of slicing disappears, signal widthDegree can be lower than amplitude reference voltage signal Vref_r and lower than the shape of amplitude reference voltage signal Vref_rState at least will last till when next crest arrives;

Therefore the amplitude that, can pass through to judge simulated audio signal Ana is lower than amplitude reference voltage signalWhether the slicing that the duration of Vref_r is detected in simulated audio signal Ana disappears, correspondingly:

If detect amplitude the continuing lower than amplitude reference voltage signal Vref_r of simulated audio signal AnaIt is invalid (to suppress cue that time reaches by a narrow margin duration threshold value Th_r and suppresses cue VaVa invalid for trigger condition be to conflict with inhibition cue Va for fear of discharging cue Vr),Discharge enable signal Tr effective, discharge cue Vr be set to effectively, to represent from analogue audio frequencyThe slicing that detects existence in signal Ana has disappeared and DC current gain Gain need to have been heightened to a gear;

Otherwise (amplitude that for example occurs simulated audio signal Ana higher than amplitude reference voltage signal Vref_r,Suppress any one situations such as cue Va is effective, release enable signal Tr is invalid), discharge promptingThat signal Vr remains is invalid, to have represented not detect the slicing that exists from simulated audio signal AnaDisappear and without DC current gain Gain being heightened to a gear.

In practical application, according to empirical value, duration threshold value Th_r by a narrow margin can be set and be greater than analogue audio frequency letterA signal period of number Ana. Certainly, those skilled in the art also can adopt other empirical value,Or according in practical application for judging that the different criterions that slicing adopts while disappearance pass through itHe determines duration threshold value Th_r by a narrow margin at means.

Fig. 8 is that the timing enable circuits that slicing suppresses in module as shown in Figure 5 coordinates with slicing testing circuitThe sequential schematic diagram producing.

First note that in Fig. 8 effective impulse taking digital audio and video signals Dig as high level pulse, press downCue Va processed and inhibition enable signal Ta high level are effectively example, and have also expressed in Fig. 8When the pulsewidth W_clipping of the effective impulse of digital audio and video signals Dig during there is slicing is greater than pulsewidthLong threshold value Th_a;

Please in referring to Fig. 5 again in conjunction with Fig. 8:

Timing enable circuits 343, for generation of suppressing enable signal Ta, wherein, suppresses enable signal TaIn the delay duration Delay_a suppressing after cue Va is set to effectively at every turn, be set to invalid, itsThe remaining moment remains effectively.

Like this, be in order DC current gain Gain to be turned down according to effectively suppressing cue Va eachAfter a file location, produce one and forbid inhibition cue Va to be set to effective time delay, so thatBefore DC current gain Gain is turned down a file location by the effective inhibition of upper once foundation cue VaProduce certain time delay, thereby can make the process of turning down of DC current gain Gain be rendered as a gradual process,And then can improve the sense of hearing smoothness of opening while suppressing slicing.

Fig. 9 is that the timing enable circuits that slicing suppresses in module as shown in Figure 5 coordinates with release testing circuitThe sequential schematic diagram producing.

First note that in Fig. 9 and enable with inhibition cue Va, release cue Vr, releaseSignal Tr high level is effectively example;

Please in referring to Fig. 5 again in conjunction with Fig. 9:

Timing enable circuits 343 also, for generation of discharging enable signal Tr, wherein, discharges enable signalThat Tr is set in the delay duration Delay_r discharging after cue Vr is set to effectively is at every turn invalid,All the other moment remain effectively.

This be because:

Detecting amplitude the continuing lower than amplitude reference voltage signal Vref_r of simulated audio signal AnaTime as long as it is invalid to suppress cue Va, discharges prompting after reaching by a narrow margin duration threshold value Th_rSignal Vr will be similarly set to along with discharging the continuous and effective of enable signal Tr effectively constantly;

But become from invalid that effectively all only represent need to be by DC current gain owing to discharging cue Vr at every turnGain heightens a gear, and so, release cue Vr is set to constantly effectively can make direct current increaseBenefit Gain also can only be raised a gear and cannot progressively be heightened to high tap position;

Thereby, if can be at the delay duration discharging after cue Vr is set to effectively at every turnIt is invalid in Delay_r, all release enable signal Tr to be set to, and continues in the amplitude of simulated audio signal AnaContinuous lower than amplitude reference voltage signal Th_r and suppress cue Va invalid during in, canMake to discharge cue Vr along with discharge enable signal Tr postponing invalid in duration Delay_r shapeBecome effective and invalid between the state of saltus step alternately, and then make to discharge cue Vr and produce repeatedlySaltus step from invalid to effective, like this, utilizes to discharge cue Vr and produce repeatedly from invalid to effectivelySaltus step can make DC current gain Gain progressively be heightened to high tap position, thereby can make DC current gainThe process of heightening of Gain is rendered as a gradual process, and then it is level and smooth to improve the sense of hearing discharging when slicingDegree.

Please again referring to Fig. 5:

When bidirectional counter 344 is effective for be set at inhibition cue Va at every turn, carry out onceRepresent DC current gain Gain to turn down the counting in reverse of a gear, can guarantee like this detecting at every turnWhile having slicing to exist, DC current gain Gain can be turned down to a gear; Discharging cue Vr quilt at every turnBe set to effectively and when counting forward not yet reaches the maximum that represents high tap position, carry out that once represent willDC current gain Gain heightens the counting forward of a gear, can guarantee like this to detect existence at every turnWhen slicing has disappeared, DC current gain Gain progressively can be heightened to high tap position and progressively heighten eachThe step-length of step is a gear; And, by the two-way count results Vg[n:0 producing] may be output to filteringModule 31, DC current gain Gain in order to regulate filtration module 31 to provide, n is greater than 1 positive integer.

Preferably, for the preferred structure of wave filter 31 as shown in Figure 4,344 of bidirectional countersThe two-way count results Vg[n:0 producing] can thermometer-code form form, like this, without decoding beCan be directly by the adjusting of adjustable resistance Ri be changed to DC current gain Gain.

As above visible, the preferred structure of the slicing inhibition module 34 based on as shown in Figure 5, audio powerThe waveform characteristic of the digital audio and video signals Dig that amplifier 30 can utilize its output in the time there is slicing examinedMeasure and in this digital audio and video signals Dig, whether have slicing and determine when by turning down direct current with thisGain G ain opens slicing and suppresses, and, utilize the simulated audio signal Ana of its input to disappear at slicingWhether the slicing that the waveform characteristic after mistake detects existence disappear from simulated audio signal Ana, alsoDetermine when by heightening DC current gain Gain and discharge slicing inhibition with this.

Detect electricity for the slicing testing circuit 341 comprising in the preferred structure going out as shown in Figure 5, releaseRoad 342, timing enable circuits 343, also provide respectively the preferred structure of further refinement in the present embodimentAnd alternative construction, be explained respectively below.

Figure 10 is that slicing suppresses the preferred structure schematic diagram of slicing testing circuit of module as shown in Figure 5.As shown in figure 10, for whether the pulsewidth that can detect the effective impulse in digital audio and video signals Dig reachesPulsewidth duration threshold value Th_a also produces and suppresses prompting letter according to testing result and inhibition enable signal TaNumber Va, can comprise in a kind of preferred structure of slicing testing circuit 341: effectively current potential linear transformationCircuit Trans, comparator C MP1 and logical device D1.

Effectively current potential linear transformation electronic circuit Trans is for by effective each of digital audio and video signals DigPulses switch is and the effective potential vt of the corresponding linearity of pulsewidth of this effective impulse;

Wherein, between linear effectively potential vt and the pulsewidth of effective impulse, meet linear relationshipVt=Vt0+KOUT (t), Vt0 is that linear effectively initial value, the K of potential vt are a default constant ratioExample coefficient (those skilled in the art can set arbitrarily the value of K as required), OUT (t) are for representingFor the effective impulse taking time t as variable; In the time there is effective impulse OUT (t), linear effectively current potentialVt can become Vt0+KOUT (t) from Vt0, and in the time that effective impulse finishes, linear effectively potential vtTo be reset to Vt0.

Comparator C MP1 mono-road input order receives the effective potential vt of linearity, another of each effective impulseOne road input receives a linear reference voltage signal Vref_a and (is carried by audio-frequency power amplifier 30 insideFor or introduce from audio-frequency power amplifier 30 is outside), a road output produces a level signal S1;

The preferred structure that note that the slicing testing circuit 341 shown in Figure 10 is only to compareThe positive input terminal of device CMP1 receives linear effectively potential vt, negative input end receives linear reference voltage signalVref_a is example, and the level signal S1 obtaining is thus that high electricity is effective, but does not limit in actual applicationsIn this;

Wherein, because the size of the effective potential vt of linearity and the pulsewidth of this effective impulse of effective impulse areLinear dependence, therefore, if there is the effective potential vt of the linearity of any effective impulse to believe higher than linear reference voltageNumber Vref_a, level signal S1 is set to effectively, reaches pulsewidth with the pulsewidth that represents this effective impulseDuration threshold value Th_a, otherwise that level signal S1 remains is invalid, to represent the pulsewidth of this effective impulseDo not reach pulsewidth duration threshold value Th_a.

Logical device D1 is for producing and suppress prompting letter according to level signal S1 and inhibition enable signal TaNumber Va;

Wherein, if level signal S1 and inhibition enable signal Ta are all effective, suppress cue VaBe set to effectively, otherwise it is invalid that inhibition cue Va remains.

Figure 11 is the schematic diagram of an instantiation of the preferred structure of slicing testing circuit as shown in figure 10.

First note that in Figure 11 taking the effective impulse of digital audio and video signals Dig as high level pulse,Linear effectively potential vt is that high potential is example, and, in Figure 11, also enable with level signal S1, inhibitionIt is effectively example that signal Ta and inhibition cue Va are high level, and, real as shown in figure 11The initial value Vt0 of the effective potential vt of linearity in example is 0.

Refer to Figure 11, effectively the preferred structure of current potential linear transformation electronic circuit Trans can comprise:PMOS pipe Mp1, NMOS pipe Mn1 and charging capacitor Ct.

The grid of PMOS pipe Mp1 receive by the reverse digital audio and video signals Dig_n of a reverser N1,Source electrode is drawn high and is received a current signal Ic and (provided or from audio frequency by audio-frequency power amplifier 30 insidePower amplifier 30 is outside to be introduced), drain electrode is by charging capacitor Ct ground connection;

The grid of NMOS pipe Mn1 receive the above-mentioned digital audio and video signals Dig_n being reversed, source ground,Drain electrode is by charging capacitor Ct ground connection.

During the effective high level pulse of digital audio and video signals Dig:

Reverse digital audio and video signals Dig_n is low level;

Low level digital audio and video signals Dig_n makes the gate source voltage poor (negative value) of PMOS pipe Mp1Be enough to PMOS to manage Mp1 conducting;

Low level digital audio and video signals Dig_n make the gate source voltage of NMOS pipe Mn1 poor (on the occasion of)Be not enough to NMOS to manage Mn1 conducting and NMOS pipe Mn is closed;

Now, flow through the PMOS pipe Mp1 of conducting but the NMOS closing that cannot flow through of current signal IcPipe Mn1, thus current signal Ic is charged to charging capacitor Ct;

Correspondingly, the voltage Vt0+KOUT (t) producing after charging capacitor Ct charging is current high level arteries and veinsThe effective potential vt of linearity of punching, and the pulsewidth of current high level pulse is larger, this height that charging obtainsThe effective potential vt of linearity of level pulse is also just higher.

During the invalid low level pulse of digital audio and video signals Dig:

Reverse digital audio and video signals Dig_n is high level;

The digital audio and video signals Dig_n of high level makes the gate source voltage poor (negative value) of PMOS pipe Mp1Be not enough to PMOS to manage Mp1 conducting and PMOS pipe Mp1 is closed;

The digital audio and video signals Dig_n of high level make the gate source voltage of NMOS pipe Mn1 poor (on the occasion of)Be enough to NMOS to manage Mn1 conducting;

Now, the current signal Ic PMOS pipe Mp1 closing that cannot flow through, but due to NMOS pipeMn1 is conducting, discharges and makes charging capacitor Ct thereby charging capacitor Ct manages Mn1 by NMOSVoltage by the effective potential vt of linearity be down to 0, i.e. initial value Vt0.

In example as shown in figure 11, pulsewidth duration threshold value Th_a is just linear reference voltage signalThe product of the capacitance of the magnitude of voltage of Vref_a and charging capacitor Ct again with the current value of current signal Ic itRatio, that is, $\mathrm{Th}\_a=\frac{\mathrm{Vref}\_a\×\mathrm{Ct}}{\mathrm{Ic}}.$

Preferably, the voltage source V DD1 of current signal Ic by audio-frequency power amplifier 30 inside can be setProduce, and a PMOS pipe Mp2 control current signal Ic. Specifically:

The grid of PMOS pipe Mp2 receives one and controls voltage signal Vbp (by audio-frequency power amplifier 30Inside provides or introduces from audio-frequency power amplifier 30 is outside), source electrode by voltage source V DD1 draw high,Drain electrode connects the source electrode of PMOS pipe Mp1;

Make after PMOS pipe Mp2 conducting when controlling voltage signal Vbp, the source electrode of PMOS pipe Mp1 is logicalCross conducting PMOS pipe Mp2 and by voltage source V DD1 draw high, PMOS pipe Mp2 conducting producesCurrent signal Ic flows into the source electrode of PMOS pipe Mp1, and, by controlling leading of PMOS pipe Mp2Logical degree is adjustable current signal Ic size also;

After control voltage signal Vbp closes PMOS pipe Mp2, current signal Ic disappears.

Please again referring to Figure 11, the preferred structure of logical device D1 can be one with a door A1, should and door A1Two-way input receive respectively the effective level signal S1 of high level and high level effectively suppresses to enable letterNumber Ta, and should produce high level with door A1 mono-tunnel output and effectively suppress cue Va.

Certainly, if the effective impulse of digital audio and video signals Dig is low level pulse and/or level signalS1 Low level effective and/or inhibition enable signal Ta Low level effective and/or inhibition cue VaLow level effective, effectively current potential linear transformation electronic circuit Trans, logical device D1 can be with reference to above-mentionedPrinciple accommodation.

That is to say, effectively the specific implementation of current potential linear transformation electronic circuit Trans, logical device D1 alsoBe not limited to above-mentioned example as shown in figure 11.

Figure 12 is that slicing suppresses the alternative construction schematic diagram of slicing testing circuit of module as shown in Figure 5.As shown in figure 12, be that pulsewidth in order to detect the effective impulse in digital audio and video signals Dig is equallyNoly reach pulsewidth duration threshold value Th_a and according to testing result and suppress enable signal Ta and produce and suppressCue Va, can comprise in a kind of alternative construction of slicing testing circuit 341: timerTIMER0 and logical device D1 '.

When timer TIMER0 is used for utilizing during each effective impulse of digital audio and video signals DigClock signal CLK0 (is provided or from audio-frequency power amplifier 30 outsides by audio-frequency power amplifier 30 insideIntroduce) carry out timing, and produce a level signal S1 ' according to timing result;

Wherein, if timer TIMER0 timing arrives a preset value, level signal S1 ' has been set toEffect, to represent that the pulsewidth of this effective impulse reaches pulsewidth duration threshold value Th_a, otherwise, level signal S1 'Remain invalid, to represent that the pulsewidth of this effective impulse does not reach pulsewidth duration threshold value Th_a.

For example, pulsewidth duration threshold value Th_a is with reference to the foregoing greater than a carrier wave of carrier signal VsThe empirical value in cycle, supposes that the frequency of clock signal clk 0 is slightly less than carrier signal Vs and timing is setThe preset value that device TIMER0 timing arrives is 1, so, as long as timer TIMER0 utilizes clock letterNumber CLK0 timing arrives 1, represents that the duration of effective impulse has exceeded one of carrier signal VsIndividual carrier cycle, thus can assert that the pulsewidth of this effective impulse reaches pulsewidth duration threshold value Th_a.

Logical device D1 ' is for producing and suppress prompting letter according to level signal S1 ' and inhibition enable signal TaNumber Va;

Wherein, if level signal S1 ' and inhibition enable signal Ta are all effective, suppress cue VaBe set to effectively, otherwise it is invalid that inhibition cue Va remains.

Visible by alternative construction as shown in figure 12, slicing testing circuit 341 is in order to detect digital soundFrequently whether the pulsewidth of the effective impulse in signal Dig reaches pulsewidth duration threshold value Th_a, is not limited to as figureShown in 10 be converted to linear effectively potential vt and by effective linearity potential vt and linear reference electricityThe preferred structure of pressing signal Vref_a directly to compare, but can also be by entering taking effective impulse as constraintOther structures of row calendar scheduling mode; And slicing testing circuit 341 is in order to produce inhibition cueVa and the structure of carrying out logical operation is also not limited to preferred structure as shown in figure 10.

Figure 13 is that slicing suppresses the preferred structure schematic diagram of release testing circuit of module as shown in Figure 5.As shown in figure 13, for the amplitude that detects simulated audio signal Ana is lower than an amplitude reference voltage signalWhether the duration of Vref_r reaches the threshold value of the duration by a narrow margin Th_r, the also foundation inspection that represent slicing and disappearedThe release enable signal Tr generation release cue of surveying result and suppressing cue Va and receivingVr, can comprise in a kind of preferred structure of release testing circuit 342: comparator C MP2, timerTIMER1 and logical device D2.

Comparator C MP2 mono-road input receives amplitude reference voltage signal Vref_r, another road inputTermination is received simulated audio signal Ana, output produces a level signal S2;

The preferred structure that note that the release testing circuit 342 shown in Figure 13 is only to compareThe positive input terminal of device CMP2 receives amplitude reference voltage signal Vref_r, negative input end receives analogue audio frequencySignal Ana is example, and the level signal S2 obtaining is thus that high electricity is effective, but in actual applications notBe limited to this;

Wherein, if the amplitude of simulated audio signal Ana is lower than amplitude reference voltage signal Vref_r, electricFlat signal S2 is set to effectively, with the amplitude that represents simulated audio signal Ana lower than amplitude with reference to electricityPress signal Vref_r, otherwise that level signal S2 is set to is invalid, to represent simulated audio signal AnaAmplitude not lower than amplitude reference voltage signal Vref_r.

Timer TIMER1 utilizes a clock letter in be set to effectively at level signal S2 duringNumber CLK1 (provide or introduce from audio-frequency power amplifier 30 is outside by audio-frequency power amplifier 30 inside)Carry out timing, and produce a level signal S3 according to timing result and inhibition cue Va;

Wherein, if timing arrives and inhibition cue Va is invalid, level signal S3 is set toEffectively, to represent amplitude the continuing lower than amplitude reference voltage signal Vref_r of simulated audio signal AnaTime has reached duration threshold value Th_r by a narrow margin, otherwise that level signal S3 remains is invalid, to represent mouldThe amplitude of intending audio signal Ana does not reach low lower than the duration of an amplitude reference voltage signal Vref_rWidth duration threshold value Th_r.

Logical device D2 is for producing and suppress prompting letter according to level signal S3 and release enable signal TrNumber Vr;

Wherein, if level signal S3 and release enable signal Tr are all effective, discharge cue VrBe set to effectively, to represent that detecting the slicing existing from simulated audio signal Ana disappears, otherwise,Discharge cue Vr remain invalid, from simulated audio signal Ana, do not detect and exist representingSlicing disappear.

Figure 14 is the schematic diagram that discharges as shown in figure 13 an instantiation of the preferred structure of testing circuit.

First note that in Figure 14 with level signal S2, level signal S3, release enable signal TrAnd discharging cue Vr, to be high level be effectively example.

Refer to Figure 14, the preferred structure of timer TIMER1 can comprise: P D of order series connectionTrigger DFF_1_1～DFF_1_P, P is greater than 1 positive integer; Wherein:

The d type flip flop of the tail end in P d type flip flop DFF_1_1～DFF_1_P of order series connectionDFF_1_P suppressing cue Va and be activated when invalid (in Figure 14 with the d type flip flop of tail endThe inhibition cue Va_n of DFF_1_P after reverse by a reverser N2 is activated as example when effective);

In P d type flip flop DFF_1_1～DFF_1_P of order series connection, remove the d type flip flop of tail endAll the other d type flip flop DFF_1_1～DFF_1_P-1 outside DFF_1_P are all in the time that level signal S2 is effectiveBe activated;

The d type flip flop DFF_1_1 of the head end in P d type flip flop DFF_1_1～DFF_1_P of order series connectionBy preset input one significant level (in Figure 14 to utilize the d type flip flop of a voltage source V DD2 to head endThe effective high level of the preset input of DFF_1_1 is example), and after being activated according to by preset input effectivelyLevel and in the time that the rising edge of clock signal clk 1 arrives by the level of output by the invalid upset before activatingFor effectively;

In P d type flip flop DFF_1_1～DFF_1_P of order series connection, remove the d type flip flop of head endAll the other d type flip flop DFF_1_2～DFF_1_P outside DFF_1_1 are respectively with previous adjacent DThe level that trigger DFF_1_1～DFF_1_P-1 produces is input, and being activated after foundation by defeatedThe significant level entering and in the time that the rising edge of clock signal clk 1 arrives by the level of output by before activatingInvalid upset be effective;

At Figure 14, the level that the d type flip flop DFF_1_P that level signal S3 is tail end produces.

Like this, through i the clock cycle of clock signal clk 1, the d type flip flop DFF_1_1 of head end～I+1 d type flip flop DFF_1_i+1 can be triggered upset successively, and i is for being more than or equal to 1 and be less thanEqual the positive integer of P-1, thus, in the time that last d type flip flop DFF_1_P can be triggered upset,Experience P-1 the clock cycle of clock signal clk 1, so, as long as the d type flip flop of tail endThe inhibition cue Va that DFF_1_P now can be disabled activates, and is experiencing clock signalAfter the P of the CLK1 clock cycle, the d type flip flop DFF_1_P of tail end will complete and overturns and makeLevel signal S3 is set to effective high level, otherwise the d type flip flop DFF_1_P of tail end wouldn't holdRow overturns and makes level signal S3 remain invalid low level.

Thereby, total number P of d type flip flop DFF_1_1～DFF_1_P and the list of clock signal clk 1The product in bit clock cycle is equivalent to duration threshold value Th_r by a narrow margin.

Refer to Figure 14, the preferred structure of logical device D2 can be one with door an A2, with two of door A2Road input is incoming level signal S3 and release enable signal Tr respectively, produces and releases with door A2 mono-tunnel outputPut cue Vr.

Certainly, if level signal S2, level signal S3, release enable signal Tr and release prompting letterAny one or more in number Vr are Low level effective, timer TIMER1, logical device D2Can be with reference to above-mentioned principle accommodation.

That is to say, the specific implementation of timer TIMER1, logical device D2 be not limited to above-mentioned asExample shown in Figure 14.

Figure 15 is that slicing suppresses the alternative construction schematic diagram of release testing circuit of module as shown in Figure 5.As shown in figure 15, be equally amplitude in order to detect simulated audio signal Ana lower than an amplitude with reference to electricityThe threshold value of the duration by a narrow margin Th_r that presses duration of signal Vref_r whether to reach to represent slicing and disappeared, alsoProduce to discharge with the release enable signal Tr receiving according to testing result and inhibition cue Va and carryShow signal Vr, in a kind of alternative construction of release testing circuit 342, can comprise: comparator C MP2,Timer TIMER1 ' and logical device D2 '.

Identical with as shown in figure 13 of the annexation of comparator C MP2 and operation principle.

Logical device D2 ' is for producing a level according to suppressing cue Va with release enable signal TrSignal S3 ';

Wherein, if suppress, cue Va is invalid, Tr is effective for release enable signal, level signal S3 'Be set to effectively, allow to be set to effectively with the release cue Vr that represents now to produce, otherwise,Level signal S3 ' remains invalid, forbids being set to the release cue Vr that represents now to produceEffect.

Timer TIMER1 ' utilizes clock signal in be set to effectively at level signal S2 duringCLK1 (provided or introduced from audio-frequency power amplifier 30 is outside by audio-frequency power amplifier 30 inside) entersRow timing, and produce and suppress cue Va according to timing result and level signal S3 ';

Wherein, if timing arrives and level signal S3 ' is effective, suppress cue Va and be set toEffectively, to represent that detecting the slicing existing from simulated audio signal Ana disappears, otherwise, suppressThat cue Va remains is invalid, to represent not detect cutting of existing from simulated audio signal AnaRipple disappears.

Visible by alternative construction as shown in figure 15, discharge testing circuit 342 for produce have manyThe release cue Vr of individual constraints, the first utilization being not limited to as shown in figure 13 suppresses prompting letterNumber Va comes control level signal S3, recycling level signal S3 and the logic fortune that discharges enable signal TrCalculate result and determine whether effectively preferred structure of release cue Vr, can produce but can adoptOther structures of constraint logic arbitrarily.

Figure 16 is that slicing suppresses the preferred structure schematic diagram of timing enable circuits of module as shown in Figure 5.As shown in figure 16, to suppress enable signal Ta and discharge enable signal Tr, timing enable circuits in order to produceIn a kind of preferred structure of 343, can comprise: logical device D3 and timer TIMER2.

Logical device D3 is for producing a level according to suppressing cue Va with release cue VrSignal S4;

Wherein, if suppress cue Va and discharge cue Vr all invalid, level signal S4Remain effectively, to represent now to need to make to suppress enable signal Ta and to discharge enable signal Tr separatelyInvalid in corresponding time delay, otherwise that level signal S4 is set to is invalid, now continue representingContinuation of insurance is held and is suppressed enable signal Ta and discharge the effective of enable signal Tr;

Timer TIMER2 for level signal S4 be set at every turn invalid after by timing result reset,And, waiting until that level signal S4 utilizes a clock signal after being set to effectively after each resetCLK2 (provided or introduced from audio-frequency power amplifier 30 is outside by audio-frequency power amplifier 30 inside) is heavyNewly carry out timing, and produce and suppress enable signal Ta and discharge enable signal Tr according to timing result;

Wherein, suppress enable signal Ta after resetting to before timing arrival delay duration Delay_aDuring this time, being set to invalid, all the other moment remains valid, discharge cue Tr after resetting to timingDuring arriving before delay duration Delay_r, being set to invalid, all the other moment remains valid.

For the preferred structure of above-mentioned timing enable circuits 343, once timer TIMER2 quiltReset, it is invalid that inhibition enable signal Ta and release enable signal Tr will certainly be set to immediately, presses soEnable letter according to previously described inhibition enable signal Ta to suppressing the impact of cue Va and dischargingNumber Tr is on discharging the impact of cue Vr, for retraining the inhibition cue Va of level signal S4Vr also can be set to immediately invalid and cause level signal S4 after each reset with release cueBe set to effectively, thereby the preferred structure of above-mentioned timing enable circuits 343 can be realized previously describedDelay duration Delay_a and delay duration Delay_r.

In addition, the preferred structure of above-mentioned timing enable circuits 343 is actually generation is suppressed to enable letterNumber Ta and produce the multiplexing functions that discharges enable signal Tr in a timer TIMER2, like thisCan save hardware resource.

And, suppress enable signal Ta by producing and produce the multiplexing functions that discharges enable signal TrIn a timer TIMER2, also can not lead to a conflict, this be because:

In the time that the delay duration Delay_a that utilizes inhibition enable signal Ta to produce works, only need to pay close attention toIt can be invalid now effectively suppressing cue Va and release cue Vr now, thereby thisTime the state of release enable signal Tr do not have any impact;

Similarly, replace saltus step what discharge that enable signal Tr produces for making to discharge cue VrWhen delay duration Delay_r works, only need concern now effectively to discharge cue Vr and thisTime inhibition cue Va can be invalid, thereby the state of inhibition enable signal Ta now does not haveAny impact.

Figure 17 is the schematic diagram of an instantiation of the preferred structure of timing enable circuits as shown in figure 16.

First note that in Figure 17 to suppress cue Va, to discharge cue Vr, level signalIt is effectively example that S4, inhibition enable signal Ta and release enable signal Tr are high level.

Refer to Figure 17, the preferred structure of logical device D3 can be a nor gate O0, nor gate O0Two-way input receive respectively and suppress cue Va and discharge cue Vr, one of nor gate O0Road output produces level signal S4.

Please, again referring to Figure 17, the preferred structure of timer TIMER2 can comprise Q D of order series connectionTrigger DFF_2_1～DFF_2_Q, Q is greater than 1 positive integer; Wherein:

Q d type flip flop DFF_2_1～DFF_2_Q of order series connection is all at level signal S4 quilt at every turnBe set to after invalid and be reset;

The d type flip flop of the head end in Q d type flip flop DFF_2_1～DFF_2_Q of order series connectionDFF_2_1 by preset input one significant level (in Figure 17 to utilize a voltage source V DD3 to head endThe effective high level of the preset input of d type flip flop DFF_2_1 is example), and level signal S4 by the time inAfter being set to effectively after each reset, foundation is by the significant level of preset input and in clock signalInvalid and upset that the rising edge of CLK2 forms the level of output while arrival by resetting is for effective;

In Q d type flip flop DFF_2_1～DFF_2_Q of order series connection, remove the d type flip flop of head endAll the other d type flip flop DFF_2_2～DFF_2_Q outside DFF_2_1 are respectively with previous adjacent DThe level that trigger DFF_2_1～DFF_2_Q-1 produces is input, and at level signal S4 by the time in oftenAfter being set to effectively after inferior reset, according to the significant level of input in the rising of clock signal clk 2The level of output is formed by resetting invalid when arriving and upset are for effective.

In Figure 17, suppressing enable signal Va can be any one d type flip flop DFF_2_j outputLevel, discharging enable signal Vr can be the level that any one d type flip flop DFF_2_k exports,J be more than or equal to 1 and the positive integer, the k that are less than or equal to Q be more than or equal to 1 and be just less than or equal to QInteger (in Figure 17, be only taking j get be greater than 1 and the value, the k that are less than Q get Q as example, in practical applicationBe not limited to this).

Like this, through j clock cycle of clock signal clk 2, j d type flip flop DFF_2_jWill complete and overturn and make to suppress that enable signal Va forms by resetting is invalidly set to effective high electricityFlat, thereby, the delay duration of size for j the clock cycle of clock signal clk 2 can be produced thusDelay_a；

Similarly, through k clock cycle of clock signal clk 2, k d type flip flop DFF_2_kWill complete and overturn and make to discharge that enable signal Vr forms by resetting is invalidly set to effective high electricityFlat, thereby, the delay duration of size for k the clock cycle of clock signal clk 2 can be produced thusDelay_r。

Certainly, if suppress cue Va, discharge cue Vr, level signal S4, suppress to enableSignal Ta and to discharge any one or more in enable signal Tr be Low level effective, timingDevice TIMER2, logical device D3 can be with reference to above-mentioned principle accommodation.

That is to say, the specific implementation of timer TIMER2, logical device D3 be not limited to above-mentioned asExample shown in Figure 17.

Figure 18 is that slicing suppresses the alternative construction schematic diagram of timing enable circuits of module as shown in Figure 5.As shown in figure 18, be to suppress enable signal Ta and discharge enable signal Tr in order to produce equally, timing makesCan in a kind of alternative construction of circuit 343, can comprise: timer TIMER3 and timerTIMER4。

Timer TIMER3 is used for after inhibition cue Va is set to effectively at every turn timing resultReset, and, after each reset, be set to after invalid and utilize one by the time suppressing cue VaClock signal clk 3 (is provided or from audio-frequency power amplifier 30 by audio-frequency power amplifier 30 insidePortion introduces) re-start timing, and produce and suppress enable signal Ta according to timing result;

Wherein, suppress enable signal Ta after resetting to before timing arrival delay duration Delay_aDuring this time, being set to invalid, all the other moment remains valid.

Timer TIMER4 is used for after release cue Vr is set to effectively at every turn timing resultReset, and, after each reset, be set to after invalid and utilize one by the time discharging cue VrClock signal clk 4 (is provided or from audio-frequency power amplifier 30 by audio-frequency power amplifier 30 insidePortion introduces) re-start timing, and produce and discharge enable signal Tr according to timing result;

Wherein, discharge cue Tr after resetting to before timing arrival delay duration Delay_rDuring this time, being set to invalid, all the other moment remains valid.

Visible by alternative construction as shown in figure 18, timing enable circuits 343 suppresses to make in order to produceCan signal Ta and discharge enable signal Tr, be not limited to as shown in figure 16 based on to suppressing cueVa and discharge the logical operation of cue Vr and the preferred structure of a multiplexing timer TIMER2,But can adopt other structures that can produce effect same.

It is more than the detailed description to the audio-frequency power amplifier 30 in the present embodiment. With reference to this audio frequency meritThe general principle that rate amplifier 30 suppresses for realizing slicing, the present embodiment also provides a kind of audio powerThe control method of amplifier.

It is adjustable that this paramodulation arranges the DC current gain Gain of audio-frequency power amplifier, and this control method alsoBe included in carry out in audio-frequency power amplifier for starting the step a that slicing suppresses and pressing down for discharging slicingThe step b of system, wherein:

For the step a that starts slicing inhibition be: the digital audio and video signals of exporting from audio-frequency power amplifier 30In Dig, detect and whether have slicing to exist, and in the time being tested with slicing existing from digital audio and video signals Dig,Adjustable DC current gain Gain of audio-frequency power amplifier 30 is turned down;

For the step b that discharges slicing inhibition be: from the simulated audio signal of input audio-frequency power amplifier 30In Ana, detect and whether have the slicing of existence to disappear, and detecting existence from simulated audio signal AnaSlicing while having disappeared, adjustable DC current gain Gain of audio-frequency power amplifier 30 is heightened.

Visible, the control method of the present embodiment sound intermediate frequency power amplifier can be by regulating audio-frequency power amplifierDC current gain Gain realize slicing and suppress, and, can also be by audio-frequency power amplifier outputThe detection of digital audio and video signals Dig judge in this digital audio and video signals Dig, whether exist slicing and withThis determine when by turn down DC current gain Gain opens slicing suppress, and, by input audio frequencyWhether the slicing that the simulated audio signal Ana of power amplifier judges existence has disappeared and has come really with thisDetermine when to discharge slicing inhibition by heightening DC current gain Gain, thus, the present embodiment sound intermediate frequency power is putThe control method of large device can produce same technique effect with previously described audio-frequency power amplifier 30, thisPlace repeats no more.

In addition:

The step a that is used for starting slicing inhibition is for can be tested with and cut from digital audio and video signals Dig at every turnWhen ripple exists, adjustable DC current gain Gain of audio-frequency power amplifier 30 is turned down to a gear;

The step b that is used for discharging slicing inhibition is for can detect and deposit from simulated audio signal Ana at every turnSlicing while having disappeared, by adjustable DC current gain Gain of audio-frequency power amplifier 30 progressively heighten toThe step-length of high tap position and each step of progressively heightening is a gear;

Wherein, the corresponding interval marking off in advance in the adjustable range that each gear is described DC current gainΔGain。

Like this, can produce same further effect with previously described audio-frequency power amplifier 30.

In practical application, for application this control method audio-frequency power amplifier signal path adopt adopt asThe situation of the preferred structure shown in Fig. 4, presses down at the step a for starting slicing inhibition with for discharging slicingIn the step b of system, DC current gain Gain be just the resistance of feedback resistance Rf and the resistance of adjustable resistance Ri itRatio,Correspondingly, adjustable by adjustable resistance Ri of the adjustable extent of DC current gain GainScope determines, and, if this control method is selected the adjusting of gradual manner, can be by adjustable resistance RiAdjustable extent be divided into several interval Δ Ri, can utilize the interval Δ Ri of adjustable resistance Ri to control pointNot several interval Δ Gain of the DC current gain Gain of corresponding each gear.

In this case, utilize the resistance of adjustable resistance Ri can realize DC current gain Gain adjusting andThe change in resistance of adjustable resistance Ri can not have influence on the cut-off frequency f for filtering_C, thereby realizing direct current increasingBenefit adjustable while of Gain can also be guaranteed the steady operation of signal path.

In addition for the control method of selecting gradual manner to regulate, in the present embodiment, be also to press down for starting slicing,System step a and for discharge slicing suppress step b corresponding optimal way is provided respectively.

For the step a suppressing for starting slicing, its optimal way can comprise following processing procedure:

Whether the pulsewidth of the effective impulse in step a1, detection digital audio and video signals Dig reaches and represents that this is effectivePulse is the pulsewidth duration threshold value Th_a of slicing, and enables letter according to testing result and the inhibition that receivesNumber Ta produces one and suppresses cue Va;

Wherein, whether this inhibition enable signal Ta represents to allow inhibition cue Va is set to effectively, is somebody's turn to doWhether suppress cue Va represents to need DC current gain Gain is turned down to a gear;

And the pulsewidth of any effective impulse reaches pulsewidth duration threshold value Th_a and inhibition makes if be tested withCan signal Ta effective, suppress cue Va and be set to effectively, to represent from digital audio and video signals DigIn be tested with slicing exist and DC current gain Gain need to be turned down to a gear; Otherwise, suppress prompting letterIt is invalid that number Va remains;

And, suppress enable signal Ta at the delay duration suppressing after cue Va is set to effectively at every turnIn Delay_a, being set to invalid, all the other moment remains effectively;

Step a2, be set to when effective suppressing cue Va, to for determining DC current gain size at every turnA two-way count results Vg[n:0] carry out and once represent DC current gain to turn down the counting in reverse of a gear.

Like this, when carrying out after the counting in reverse that once represents the DC current gain to turn down a gear, suitableIn having started slicing inhibition. And, suppressing cue Va quilt at every turn owing to suppressing enable signal TaIn delay duration Delay_a after being set to effectively, being set to invalid, all the other moment remains effectively, because ofAnd DC current gain is turned down after a file location according to effectively suppressing cue Va each, canProduce one and forbid inhibition cue Va to be set to effective time delay, thus can be in upper once foundationEffectively inhibition cue Va produces certain time delay before DC current gain is turned down to a file location.

For the step b suppressing for discharging slicing, its optimal way can comprise following processing procedure:

The amplitude of step b1, detection simulated audio signal Ana is lower than an amplitude reference voltage signal Vref_r'sWhether the duration reaches represents the threshold value of the duration by a narrow margin Th_r that disappeared of slicing, and according to testing result andA release enable signal Tr who suppresses cue Va and receive produces one and discharges cue Vr;

Wherein, this release enable signal Tr represent whether to allow by release cue Vr be set to effectively, this releasesWhether put cue Vr represents to need DC current gain Gain is heightened to a gear;

And, if the amplitude that detects simulated audio signal Ana is lower than amplitude reference voltage signal Vref_r'sDuration reach by a narrow margin duration threshold value Th_r and suppress cue Va invalid, discharge enable signal and haveEffect Tr, discharges cue Vr and is set to effectively, detects and deposit representing from simulated audio signal AnaSlicing disappeared and DC current gain Gain need to have been heightened to a gear; Otherwise, discharge cue VrIt is invalid to remain;

And, discharge enable signal Tr at the delay duration discharging after cue Vr is set to effectively at every turnIn Delay_r, being set to invalid, all the other moment remains effectively;

Step b2, discharging that cue Vr is set to effectively at every turn and counting forward not yet reaches expressionWhen the maximum of high tap position, to the two-way count results Vg[n:0 for determining DC current gain size] carry out oneThe counting forward of a gear is heightened DC current gain in inferior expression.

Like this, until reaching, counting forward represents high tap position when carrying out counting forward that DC current gain is heightenedMaximum after, be equivalent to discharge slicing inhibition. And, carry in release owing to discharging enable signal TrShow that in the delay duration Delay_r after signal Vr is set to effectively at every turn, being set to invalid, all the other moment protectsHold as effectively, thus the amplitude of simulated audio signal Ana continue lower than amplitude reference voltage signal Th_r,And suppress cue Va invalid during in, can make to discharge cue Vr along with release enables letterNumber Tr be formed on postponing invalid in duration Delay_r effective and invalid between the state of saltus step alternately,And then make to discharge repeatedly saltus step from invalid to effective of cue Vr generation, like this, utilize and discharge prompting letterNumber Vr produces repeatedly from invalid to effective saltus step and can make DC current gain progressively be heightened to high tap position.

In actual applications:

According to empirical value, pulsewidth duration threshold value Th_a is greater than the carrier signal in audio-frequency power amplifier 30A carrier cycle of Vs;

According to empirical value, duration threshold value Th_r is greater than a signal period of simulated audio signal Ana by a narrow margin;

And, adopt preferred structure as shown in Figure 4 for the signal path of audio-frequency power amplifier 30Situation, two-way count results Vg[n:0] can thermometer-code form form, like this, without decodingDirectly by the adjusting of adjustable resistance Ri is changed to DC current gain.

Further, cut for the step a1 of the step a for starting slicing inhibition and for dischargingStep b1 in the step b that ripple suppresses, the present embodiment provides respectively the Xiang Yingyou of further refinement to select modeAnd alternate ways.

The optimal way that is used for the step a1 of the step a that starts slicing inhibition comprises:

Step a11, each effective impulse in digital audio and video signals Dig is converted to and the arteries and veins of this effective impulseThe effective potential vt of wide corresponding linearity;

Step a12, by effective the linearity of each effective impulse potential vt and a linear reference voltage signal Vref_aCompare and produce a level signal S1 according to comparative result;

Wherein, if having the effective potential vt of the linearity of any effective impulse higher than linear reference voltage signal Vref_a,Level signal S1 be set to effectively, to represent that the pulsewidth of this effective impulse reaches pulsewidth duration threshold value Th_a,Otherwise level signal S1 remains invalid;

Step a12, according to level signal S1 with suppress enable signal Ta and produce and suppress cue Va;

Wherein, if level signal S1 and inhibition enable signal Ta are all effective, suppress cue Va and be set toFor effectively, otherwise, suppress cue Va remain invalid.

The alternate ways that is used for the step a1 of the step a that starts slicing inhibition comprises:

During step a11 ', each effective impulse in digital audio and video signals Dig, utilize clock signal clk 0Carry out timing, and produce a level signal S1 ' according to timing result;

Wherein, if step a11 ' timing arrives a preset value, level signal S1 ' be set to effectively, to representThe pulsewidth of this effective impulse reaches pulsewidth duration threshold value Th_a, otherwise level signal S1 ' remains invalid;

Step a12 ', according to level signal S1 ' with suppress enable signal Ta and produce and suppress cue Va;

Wherein, if level signal S1 ' and inhibition enable signal Ta are all effective, suppress cue VaBe set to effectively, otherwise it is invalid that inhibition cue Va remains.

Visible, be not limited to one for the implementation of a1 that starts the step a that slicing suppresses.

The optimal way that is used for the step b1 of the step b that discharges slicing inhibition comprises:

Step b11, will state amplitude reference voltage signal Vref_r and simulated audio signal Ana compares, alsoProduce a level signal S2 according to comparative result;

Wherein, if the amplitude of simulated audio signal Ana is lower than amplitude reference voltage signal Vref_r, levelSignal S2 is set to effectively, with the amplitude that represents simulated audio signal Ana lower than amplitude reference voltage signalVref_r, otherwise it is invalid that second electrical level signal S2 is set to;

Step b12, utilize clock signal clk 1 in during level signal S2 is set to effectivelyTime, and produce a level signal S3 according to timing result and inhibition cue Va;

Wherein, if step b12 timing arrives and inhibition cue Va is invalid, level signal S3Be set to effectively, otherwise level signal S3 remains invalid;

B13, according to level signal S3 with discharge enable signal Tr and produce and suppress cue Vr;

Wherein, if level signal S3 and release enable signal Tr are all effective, discharge cue Vr and be set toFor effectively, to represent amplitude the continuing lower than amplitude reference voltage signal Vref_r of simulated audio signal AnaTime has reached duration threshold value Th_r by a narrow margin, otherwise it is invalid that release cue Vr remains.

Visible, be not limited to one for the implementation of step b1 that discharges the step b that slicing suppressesKind.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all at thisWithin the spirit and principle of invention, any amendment of making, be equal to replacement, improvement etc., all should be included inWithin the scope of protection of the invention.

Claims (13)

1. an audio-frequency power amplifier, is characterized in that, this audio-frequency power amplifier comprises: order series connectionFiltration module between audio input end and the audio output of described audio-frequency power amplifier, comparison module,And power output module, also comprise connect described audio input end, described audio output and described inThe slicing of filtration module suppresses module;

Described filtration module is for utilizing the DAB of a biasing voltage signal and the output of described audio outputSignal to the simulated audio signal of described audio input end input carry out LPF, and by described low pass filteredRipple obtains a filtering signal, and, for described audio-frequency power amplifier provides adjustable DC current gain;

Described comparison module is for comparing described filtering signal and a carrier signal, also by described comparisonObtain a pulse signal;

Described power output module is for driving described audio output to export digital sound according to described pulse signalFrequently signal, and the power of described digital audio and video signals is greater than described simulated audio signal;

Described slicing suppresses module in the time being tested with slicing from described digital audio and video signals and existing, by instituteThe described DC current gain that stating filtration module provides is turned down; And, detecting from described simulated audio signalWhen the slicing existing has disappeared, the described DC current gain that described filtration module is provided is heightened;

Wherein, described slicing inhibition module comprises: slicing testing circuit, release testing circuit, timing enable electricityRoad and bidirectional counter;

Whether described slicing testing circuit reaches for detection of the pulsewidth of the effective impulse in described digital audio and video signalsTo representing this effective impulse pulsewidth duration threshold value that is slicing, and according to testing result and one pressing down of receivingEnable signal processed produces one and suppresses cue; Wherein, reach institute if detect the pulsewidth of any effective impulseState pulsewidth duration threshold value and described inhibition enable signal is effective, described inhibition cue is set to effectively,Otherwise it is invalid that described inhibition cue remains;

Described timing enable circuits is for generation of described inhibition enable signal; Wherein, described inhibition enable signal existsAfter described inhibition cue is set to effectively at every turn first postpones to be set to invalid, all the other moment in durationRemain effectively;

Described release testing circuit for detection of the amplitude of described simulated audio signal lower than an amplitude reference voltageWhether the duration of signal reaches represents the threshold value of duration by a narrow margin that disappeared of slicing, and according to testing result withAnd described inhibition cue and receive one discharge enable signal produce one discharge cue; Wherein,If detecting the amplitude of described simulated audio signal reached lower than the duration of described amplitude reference voltage signalThe described threshold value of duration by a narrow margin, invalid, the described release enable signal of described inhibition cue are effective, described inDischarge cue and be set to effectively, otherwise it is invalid that described release cue remains;

Described timing enable circuits is also for generation of described release enable signal; Wherein, described release enable signalAfter described release cue is set to effectively at every turn second postpone to be set in duration invalid, all the other timeCarve and remain effectively;

When described bidirectional counter is effective for be set in described inhibition cue at every turn, carries out once and representDescribed DC current gain is turned down to the counting in reverse of a gear; Be set in described release cue at every turnWhen effect and counting forward not yet reach the maximum that represents high tap position, carry out and once represent described direct currentThe counting forward of a gear is heightened in gain; And, by the two-way counting knot for determining described DC current gainFruit exports described filtration module to.

2. audio-frequency power amplifier according to claim 1, is characterized in that, described slicing detects electricityRoad comprises: effectively current potential linear transformation electronic circuit, the first comparator and the first logical device;

Described effective current potential linear transformation electronic circuit is used for each effective impulse of described digital audio and video signalsBe converted to the effective current potential of the corresponding linearity of pulsewidth with this effective impulse;

Described the first comparator Yi road input order receives the effective current potential of described linearity, another of each effective impulseOne road input receives a linear reference voltage signal, a road output produces one first level signal; Wherein,If have the effective current potential of described linearity of any effective impulse higher than described linear reference voltage signal, describedOne level signal is set to effectively, otherwise it is invalid that described the first level signal remains;

Described the first logical device is for producing institute according to described the first level signal and described inhibition enable signalState inhibition cue; Wherein, if described the first level signal and described inhibition enable signal are all effective,Described inhibition cue is set to effectively, otherwise it is invalid that described inhibition cue remains.

3. audio-frequency power amplifier according to claim 2, is characterized in that, described DAB letterNumber described effective impulse be high level pulse, and described effective current potential linear transformation electronic circuit comprises: PMOSPipe, NMOS pipe and charging capacitor;

The grid of described PMOS pipe receives the described digital audio and video signals, the source electrode that are reversed and is drawn high and receiveOne current signal, drain electrode are by described charging capacitor ground connection;

It is logical that the grid of described NMOS pipe receives the described digital audio and video signals, source ground, the drain electrode that are reversedCross described charging capacitor ground connection;

And, magnitude of voltage and described charging capacitor that described pulsewidth duration threshold value is described linear reference voltage signalThe product of capacitance and the ratio of the current value of described current signal.

4. audio-frequency power amplifier according to claim 2, is characterized in that, described the first level letterNumber, that described inhibition enable signal and described inhibition cue are high level is effective, and described firstLogical device be first with door, described first with the two-way input of door receive respectively described the first level signal andDescribed inhibition enable signal, described first produces described inhibition cue with Men mono-tunnel output.

5. audio-frequency power amplifier according to claim 1, is characterized in that, described release detects electricityRoad comprises: the second comparator, the first timer and the second logical device;

Described the second comparator Yi road input receives described amplitude reference voltage signal, another road input terminationReceive described simulated audio signal, output produces a second electrical level signal; Wherein, if described analogue audio frequency letterNumber amplitude lower than described amplitude reference voltage signal, described second electrical level signal is set to effectively, otherwise,It is invalid that described second electrical level signal is set to;

Described the first timer utilizes at first o'clock in be set to effectively at described second electrical level signal duringClock signal carries out timing, and produces a three level signal according to timing result and described inhibition cue;Wherein, if timing arrives and described inhibition cue is invalid, described three level signal has been set toEffect, otherwise it is invalid that described three level signal remains;

Described the second logical device is for producing institute according to described three level signal and described release enable signalState inhibition cue; Wherein, if described three level signal and described release enable signal are all effective,Described release cue is set to effectively, otherwise it is invalid that described release cue remains.

6. audio-frequency power amplifier according to claim 5, is characterized in that, described second electrical level letterNumber and described three level signal to be high level effective, described the first timer comprises order series connection at leastTwo the first d type flip flops, wherein:

The first d type flip flop of the tail end at least two the first d type flip flops of order series connection is carried in described inhibitionWhile showing invalidating signal, be activated;

Its at least two the first d type flip flops of order series connection except the first d type flip flop of described tail endFirst d type flip flop of Yuing is all activated in the time that described second electrical level signal is effective;

The first d type flip flop of the head end at least two the first d type flip flops of order series connection is by preset input oneSignificant level, and after being activated according to by the significant level of preset input and in described the first clock signalRising edge while arriving by the level of output by the invalid upset before activating for effectively;

Its at least two the first d type flip flops of order series connection except the first d type flip flop of described head endThe level that first d type flip flop of Yuing all produces taking previous adjacent the first d type flip flop is as input, and swashedAfter living according to the significant level of input in the time that the rising edge of described the first clock signal arrives by the electricity of outputFlat is effective by the invalid upset before activating;

And, the level of d type flip flop that described three level signal is described tail end output, described by a narrow margin timeLong threshold value is the product in the quantity of described the first d type flip flop and the cycle of described the first clock signal.

7. audio-frequency power amplifier according to claim 5, is characterized in that, described the 3rd level letterNumber, described release enable signal and discharge cue to be high level effective, and described second patrolsVolume device be second with door, described second receives respectively described three level signal and institute with the two-way input of doorState release enable signal, described second produces described release cue with Men mono-tunnel output.

8. audio-frequency power amplifier according to claim 1, is characterized in that, described timing enables electricityRoad comprises: the 3rd logical device and the second timer;

Described the 3rd logical device is for producing one according to described inhibition cue and described release cueThe 4th level signal; Wherein, if described inhibition cue and described release cue are all invalid, instituteState the 4th level signal and remain effectively, otherwise it is invalid that described the 4th level signal is set to;

Described the second timer for be set in described the 4th level signal at every turn invalid after by multiple timing resultPosition, and, waiting until that described the 4th level signal utilizes at second o'clock after being set to effectively after each resetClock signal carries out timing, and produces described inhibition enable signal and discharge enable signal according to timing result; ItsIn, described inhibition enable signal reset after arrive described the first delay duration to timing before during inBeing set to invalid, all the other moment remains valid, described release cue after resetting to timing arrival instituteDuring stating before the second delay duration, being set to invalid, all the other moment remains valid.

9. audio-frequency power amplifier according to claim 8, is characterized in that, described inhibition prompting letterNumber and described release cue to be high level effective, and described the 3rd logical device is nor gate, described inThe two-way input of nor gate receives respectively described inhibition cue and described release cue, described or non-Men mono-tunnel output produces described the 4th level signal.

10. audio-frequency power amplifier according to claim 8, is characterized in that, described the 4th level letterNumber, that described inhibition enable signal and described release enable signal are high level is effective, and described secondTime device comprise at least two the second d type flip flops of order series connection, wherein:

It is invalid that at least two the second d type flip flops of order series connection are all set in described the 4th level signal at every turnAfter be reset, and after being reset, the level of output is reset at every turn invalid;

The second d type flip flop of the head end at least two the second d type flip flops of order series connection is by preset input oneSignificant level, and after being reset at every turn and waiting until that described the 4th level signal is set to effectively, foundationBy the significant level of preset input and in the time that the rising edge of described second clock signal arrives by the level of output byReset the invalid of formation and overturn as effective;

Its at least two the second d type flip flops of order series connection except the second d type flip flop of described head endThe level that second d type flip flop of Yuing all produces taking previous adjacent the second d type flip flop is as input, and at every turnAfter being reset and waiting until that described the 4th level signal is set to effectively, according to the significant level of inputIt is invalid and overturn as having that the rising edge of described second clock signal forms the level of output while arrival by resettingEffect;

And described inhibition enable signal is the level of any one the second d type flip flop output, described releaseEnable signal is the level of any one the second d type flip flop output, and described the first delay duration is from described headThe second d type flip flop of end to export described inhibition enable signal any one the second d type flip flop described theThe product in the cycle of the quantity of 2-D trigger and described second clock signal, described second postpone duration be fromThe second d type flip flop of described head end is to any one the second d type flip flop of exporting described release enable signalThe product in the cycle of the quantity of described the second d type flip flop and described second clock signal.

The control method of 11. 1 kinds of audio-frequency power amplifiers, is characterized in that, this control method arranges described soundFrequently the DC current gain of power amplifier is adjustable, and this control method is included in described audio-frequency power amplifierThe following steps of interior execution:

Step a, from the digital audio and video signals of described audio-frequency power amplifier output, detect and whether have slicing to deposit, and in the time being tested with slicing existing from described digital audio and video signals, described DC current gain is turned down;

Step b, from input the simulated audio signal of described audio-frequency power amplifier, detect and whether have cutting of existenceRipple disappears, and in the time that the slicing that detects existence from described simulated audio signal has disappeared, by described straightFlow enhancement is heightened;

Wherein, described step a comprises:

Whether step a1, the pulsewidth that detects the effective impulse in described digital audio and video signals reach represents that this is effectivePulse is the pulsewidth duration threshold value of slicing, and according to testing result and receive one suppress enable signal produceRaw one suppresses cue; Wherein, reach described pulsewidth duration if be tested with the pulsewidth of any effective impulseThreshold value and described inhibition enable signal are effective, and described inhibition cue is set to effectively, otherwise, instituteState suppress cue remain invalid; And described inhibition enable signal is every in described inhibition cueThat inferior first after being set to effectively postpones to be set in duration is invalid, all the other moment remain effectively;

Step a2, be set to when effective in described inhibition cue, to for determining that described direct current increases at every turnOne two-way count results of benefit is carried out the counting in reverse that once represents described DC current gain to turn down a gear;

Described step b comprises:

Step b1, the amplitude during lower than an amplitude reference voltage signal lasting that detects described simulated audio signalBetween whether reach and represent the threshold value of duration by a narrow margin that disappeared of slicing, and carry according to testing result and described inhibitionShow that signal and the release enable signal receiving produce one and discharge cue; Wherein, if described in detectingDuration by a narrow margin described in the amplitude of simulated audio signal reached lower than the duration of described amplitude reference voltage signalThreshold value, invalid, the described release enable signal of described inhibition cue are effective, described release cueBe set to effectively, otherwise it is invalid that described release cue remains; And, described release enable signalAfter described release cue is set to effectively at every turn second postpone to be set in duration invalid, all the other timeCarve and remain effectively;

Step b2, be set to effectively and counting forward not yet reaches expression in described release cue at every turnWhen the maximum of high tap position, described two-way count results is carried out and once represented described DC current gain to heightenThe counting forward of a gear.

12. control methods according to claim 11, is characterized in that, described step a1 comprises:

Step a11, each effective impulse in described digital audio and video signals is converted to and the arteries and veins of this effective impulseThe effective current potential of wide corresponding linearity;

Step a12, the effective current potential of described linearity of each effective impulse and a linear reference voltage signal are comparedAnd according to comparative result produce one first level signal; Wherein, if there is the described line of any effective impulseThe effective current potential of property is higher than described linear reference voltage signal, and described the first level signal is set to effectively, no, described the first level signal remain invalid;

Step a12, described the first level signal of foundation and described inhibition enable signal produce described inhibition prompting letterNumber; Wherein, if described the first level signal and described inhibition enable signal are all effective, described inhibition promptingSignal is set to effectively, otherwise it is invalid that described inhibition cue remains.

13. control methods according to claim 11, is characterized in that, described step b1 comprises:

Step b11, described amplitude reference voltage signal and described simulated audio signal are compared and foundationComparative result produces a second electrical level signal; Wherein, if the amplitude of described simulated audio signal lower than described widthDegree reference voltage signal, described second electrical level signal is set to effectively, otherwise, described second electrical level signalIt is invalid to be set to;

Step b12, utilize the first clock signal to carry out in during described second electrical level signal is set to effectivelyTiming, and produce a three level signal according to timing result and described inhibition cue; Wherein, if meterTime arrive and described inhibition cue invalid, described three level signal is set to effectively, otherwise,It is invalid that described three level signal remains;

Step b13, the described three level signal of foundation and described release enable signal produce described inhibition prompting letterNumber; Wherein, if described three level signal and described release enable signal are all effective, described release promptingSignal is set to effectively, otherwise it is invalid that described release cue remains.