CN103325727B - Form the semiconductor approach and device for being fanned out to packaging body laminated device - Google Patents

Form the semiconductor approach and device for being fanned out to packaging body laminated device Download PDF

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Publication number
CN103325727B
CN103325727B CN201310024110.7A CN201310024110A CN103325727B CN 103325727 B CN103325727 B CN 103325727B CN 201310024110 A CN201310024110 A CN 201310024110A CN 103325727 B CN103325727 B CN 103325727B
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China
Prior art keywords
semiconductor element
sealant
conductive layer
core material
insulating barrier
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CN201310024110.7A
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CN103325727A (en
Inventor
林耀剑
P.C.马里穆图
陈康
Y.顾
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority claimed from US13/429,119 external-priority patent/US8810024B2/en
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to CN201810182803.1A priority Critical patent/CN108257877B/en
Publication of CN103325727A publication Critical patent/CN103325727A/en
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to the semiconductor approach and device that formation is fanned out to packaging body laminated device.Semiconductor devices includes the carrier with tube core attachment levels.Surface is installed to tube core attachment levels with carrier relative mode after semiconductor element.Modular interconnection unit be arranged on carrier on and around the outer peripheral areas around semiconductor element or in so that rear surface offsets of the modular interconnection unit from semiconductor element.Sealant is deposited in carrier, semiconductor element and modular interconnection unit.The Part I of sealant is removed in order to expose semiconductor element, and Part II is removed in order to expose modular interconnection unit.Carrier is removed.Interconnection structure is formed on semiconductor element and modular interconnection unit.Modular interconnection unit includes the vertical interconnecting structure or projection through semiconductor devices.Modular interconnection unit forms the part of interlocking pattern around semiconductor element.

Description

Form the semiconductor approach and device for being fanned out to packaging body laminated device
National preference requirement
The application is the part continuation application for the U.S. Patent Application No. 13/429119 submitted on March 23rd, 2012, should U.S. Patent application is hereby incorporated by.
Technical field
The present invention relates generally to semiconductor devices, and relate more specifically to a kind of formed there is printed substrate (PWB) mould The semiconductor devices and method that are fanned out to packaging body lamination (Fo-PoP) of block perpendicular interconnection unit.
Background technology
Semiconductor devices is usually found in modern electronic product.Semiconductor devices is in terms of the number and density of electric part Change.Discrete semiconductor device generally comprises a type of electric part, such as light emitting diode（LED）, small-signal crystal Pipe, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor（MOSFET）.It is integrated partly to lead Body device typically comprises hundreds of and arrives millions of electric part.The example of integrated-semiconductor device includes microcontroller, micro- Processor, charge coupling device（CCD）, solar cell and DMD（DMD）.
Semiconductor devices performs various functions, such as signal transacting, supercomputing, transmitting and reception electromagnetic signal, control Electronic device processed, convert sunlight into electric power and produce the visual projection shown for TV.In amusement, communication, power Conversion, network, computer and consumer products field in find semiconductor devices.Also in Military Application, aviation, automobile, work Semiconductor devices is found in industry controller and office equipment.
Semiconductor devices utilizes the electrical properties of semi-conducting material.The atomic structure of semi-conducting material allows by applying electric field Or base current（base current）Or its electric conductivity is manipulated by doping process.Adulterate to semi-conducting material introduce impurity with Manipulate and control the electric conductivity of semiconductor devices.
Semiconductor devices includes active and passive electrical structure.Including the bipolar and active structure of field-effect transistor control electricity The flowing of stream.Either promote or limit the flowing of electric current by changing doped level and application electric field or base current, transistor. Passive structures including resistor, capacitor and inductor are created as between voltage and current necessary to performing various Electricity Functionals Relation.Passive and active structure is electrically connected to form circuit, and this causes semiconductor devices to be able to carry out supercomputing and other Useful function.
Semiconductor devices is typically manufactured using two complicated manufacturing process, i.e. front end manufactures and manufactured with rear end, often One may relate to hundreds step.Front end manufacture, which is related on the surface of semiconductor wafer, forms multiple tube cores.Each partly lead Body tube core is typically identical and comprising by electrically connecting active and passive component the circuit that is formed.Rear end manufacture be related to from The chip segmentation of completion（singulate）Each semiconductor element and package die are to provide structural support and be environmentally isolated.Such as Term " semiconductor element " used herein refers to the odd number and plural form of the word, and therefore can refer to single semiconductor Device and multiple semiconductor devices.
One purpose of semiconductor manufacturing is the less semiconductor devices of production.Less device typically consumes less Power, there is higher performance and can be produced more efficiently.In addition, less semiconductor devices has less occupy-place area （footprint）, what this was desirable to for less end product.Less semi-conductor die size can pass through front end Improvement in technique obtains, the improvement in the front-end process cause semiconductor element have it is smaller, higher density active and Passive component.Backend process can cause the semiconductor with compared with reduced dimension area by the improvement in electricity interconnection and encapsulating material Device encapsulates.
A kind of method for realizing the purpose of more highly integrated and smaller semiconductor devices is to lay particular emphasis on the three-dimensional (3D) including PoP Encapsulation technology.However, PoP is frequently necessary to laser drill to form interconnection structure, which increase equipment cost and require to drill Through whole package thickness.Laser drill increases cycle time and reduces manufacture handling capacity.Exclusively pass through laser drill work The perpendicular interconnection that skill is formed can cause the reduction of the control to perpendicular interconnection.Unprotected contact can also cause using follow-up The yield loss increase for the interconnection that surface mounting technique (SMT) is formed.In addition, for forming leading for perpendicular interconnection in PoP Electric material, such as copper (Cu), semiconductor element may be accidentally transferred to during formation is encapsulated, thus half in pollution encapsulation Conductor tube core.
The content of the invention
For it is a kind of need not laser drill through encapsulation Fo-PoP in perpendicular interconnection demand be present.Therefore, at one In embodiment, the present invention is a kind of method for making semiconductor devices, and it includes step：Tube core attachment levels are provided for carrier, First semiconductor element is installed to tube core attachment levels, it is in the outer peripheral areas around the first semiconductor element that modularization is mutual Even unit is arranged on carrier, and the first sealant is deposited in carrier, the first semiconductor element and modular interconnection unit, is moved Except a part for sealant to expose the first semiconductor element and modular interconnection unit, carrier is removed, and led the first half Interconnection structure is formed in body tube core and modular interconnection unit.
In another embodiment, the present invention is a kind of method for making semiconductor devices, and it includes step：Carrier is provided, Semiconductor element is installed to carrier, modular interconnection unit is arranged on carrier in the outer peripheral areas around semiconductor element On, sealant is deposited in carrier, semiconductor element and modular interconnection unit, and remove a part for sealant to reveal Go out modular interconnection unit and semiconductor element.
In another embodiment, the present invention is a kind of method for making semiconductor devices, and it includes step：Semiconductor is provided Tube core, modular interconnection unit is arranged in the outer peripheral areas around semiconductor element, and in semiconductor element and module Change and deposit sealant on interconnecting unit.
In another embodiment, the present invention is a kind of semiconductor devices, and it includes semiconductor element.Modular interconnection unit It is arranged in the outer peripheral areas around semiconductor element.Sealant is deposited on around semiconductor element and modular interconnection unit.
Brief description of the drawings
Fig. 1 illustrates the different types of printed circuit board (PCB) (PCB) for encapsulating and being installed to its surface；
Fig. 2 a-2c illustrate the other details for the representative semiconductor packages for being installed to PCB；
Fig. 3 a-3c illustrate the semiconductor wafer with the multiple semiconductor elements separated by saw lanes；
Fig. 4 a-4h illustrate to be formed for Fo-PoP, have the technique of the PWB modular units of vertical interconnecting structure；
Fig. 5 a-5i illustrate to form the technique of the Fo-PoP with semiconductor element, and the semiconductor element passes through with vertical The PWB modular units of interconnection structure and interconnect；
Fig. 6 a-6r illustrate another technique to form the Fo-PoP with semiconductor element, the semiconductor element by with The PWB modular units of vertical interconnecting structure and interconnect；
Fig. 7 a-7i illustrate the various conductive vertical interconnection structures for PWB modular units；
Fig. 8 a-8c illustrate to form the technique of PWB modular units, and the PWB modular units, which have, includes the vertical of projection Interconnection structure；
Fig. 9 illustrates a kind of Fo-PoP with semiconductor element, and the semiconductor element is by with including the vertical of projection The PWB modular units of interconnection structure and interconnect；
Figure 10 illustrates another Fo-PoP with semiconductor element, and the semiconductor element passes through with vertical interconnecting structure PWB modular units and interconnect；
Second semiconductor element is installed to PWB modular units by Figure 11 a-11b explanations；
Figure 12 a-12b illustrate the technique for forming modular unit from the sealant panel with fine filler；
Figure 13 a-13i illustrate to form the modularization that the sealant panel with never embedded conductive pole or projection is formed The Fo-PoP of unit another technique；
Figure 14 illustrates the another of the modular unit that the sealant panel with never embedded conductive pole or projection is formed One Fo-PoP；
Figure 15 a-15b illustrate the technique for forming modular unit from PCB panel；And
Figure 16 illustrates the another of the modular unit that the PCB panel with never embedded conductive pole or projection is formed Fo-PoP。
Embodiment
In the following description, reference chart describes the present invention with one or more embodiments, in these figures similar mark Number represent same or similar element.Although just it is used for the optimal mode description present invention for realizing the object of the invention, ability Field technique personnel should be appreciated that its be intended to covering can be included in such as following disclosure and figure support appended claims and its Replacement, modification and the equivalent in the spirit and scope of the present invention that equivalent limits.
Semiconductor devices is typically manufactured using two complex fabrication process：Front end manufactures and rear end manufacture.Front end manufactures It is related on the surface of semiconductor wafer and forms multiple tube cores.Each tube core on chip includes active and passive electrical part, it Be electrically connected to form functional circuit.The active electrical part of such as transistor and diode has the ability that control electric current flows. Voltage necessary to the passive electrical part of such as capacitor, inductor, resistor and transformer is created as execution circuit function and Relation between electric current.
By including adulterating, depositing, photoetching, etching and planarization series of process step on the surface of semiconductor wafer The passive and active parts of upper formation.Doping adds impurities to semi-conducting material by the technology of such as ion implanting or thermal diffusion In.Doping process have modified the electric conductivity of semi-conducting material in active device, and semi-conducting material is changed into insulator, conductor, Or the electric conductivity of semi-conducting material is dynamically changed in response to electric field or base current.Transistor includes different type and doping The region of degree, it is arranged such that transistor can promote or limit electric current when applying electric field or base current as required Flowing.
Active and passive component is formed by the material layer with different electrical properties.Layer can be by part by deposited material The various deposition techniques that material type determines are formed.For example, thin film deposition may relate to chemical vapor deposition（CVD）, physics vapour Mutually deposit（PVD）, electrolytic coating and chemical plating technique.Each layer is typically patterned to form active parts, passive component Or the part of the electrical connection between part.
Layer can be patterned using photoetching, the light-sensitive material that photoetching is related to such as photoresist is being treated by pattern Deposition on the layer of change.Using light, pattern is transferred to photoresist from photomask.In one embodiment, light influences The part of photoresist pattern is removed using solvent, exposes the part of bottom to be patterned.In another embodiment, The not part for the photoresist pattern that light influences, i.e. negative photoresist, are removed using solvent, exposed to be patterned The part of bottom.The remainder of photoresist is removed, and leaves patterned layer.Alternatively, some type of material passes through The region or room for directly to be formed to original deposition/etch processes using technology as such as chemical plating and electrolytic coating Deposition materials and be patterned.
Patterning is the fundamental operation for the part for removing the top layer on semiconductor wafer surface.Photoetching, light can be used to cover Mould, mask, oxide or metal removal, photography and mould printing and microlithography remove the part of semiconductor wafer.Photoetching It is included in reticle mask or photomask and forms pattern and transfer the pattern onto in the superficial layer of semiconductor wafer.Photoetching is two The active and horizontal scale of passive component formed in step process on the surface of semiconductor wafer.First, reticle mask or mask On pattern be transferred in photoresist layer.Photoresist is that the photosensitive of structure and attribute change is undergone when being exposed to light Feel material.Change the structure of photoresist and the process of attribute either as negative effects photoresist or as positivity Act on photoresist.Second, photoresist layer is transferred in wafer surface.When etching removes semiconductor wafer During the part that top layer is not covered by photoresist, the transfer occurs.The chemical property of photoresist causes photoresist Keep essentially completed and be resistant to the removal by chemical etching liquor, and the top layer of semiconductor wafer is not by photoresist The part of covering is removed.Formed, expose and remove the process of photoresist and remove the mistake of a part of semiconductor wafer Journey can be changed according to used specific resist and desired result.
In negative effects photoresist, photoresist is exposed to light and during being referred to as polymerizeing from solvable Solution state change is insoluble state.In polymerization, unpolymerized material exposure forms tool in light or energy source and polymer There is the cross-linked material of etch resistance.In most of negative resists, polymer is polyisoprene.Utilize chemical solvent or aobvious Shadow agent removes solubilized part (that is, the part for being not exposed to light) and left in resist layer corresponding to opaque on reticle mask The hole of pattern.The mask that its pattern is present in zone of opacity is referred to as clear-field mask.
In positivity acts on photoresist, photoresist is exposed to light and the slave phase during referred to as light dissolves It is the much higher state of solubility to insoluble state change.In light dissolving, the resist of relatively insoluble solution is exposed to Appropriate light energy and it is switched to the much higher state of solubility.The light dissolving part of resist can be in developing process Removed by solvent.Basic positive photoresist polymer is phenol formaldehyde polymers, also referred to as phenol formaldehyde lacquer resin.Profit Solubilized part (that is, exposed to the part of light) is removed with chemical solvent or developer to leave in resist layer corresponding to centre The hole of transparent pattern on mask.The mask that its pattern is present in transparent region is referred to as dark-field mask.
After the top section not covered by photoresist of semiconductor wafer is removed, remaining photoresist quilt Remove, leave patterned layer.Alternatively, passed through using the technology of such as chemical plating and electrolytic coating, some type of material Material is deposited directly in the region or room formed by previous deposition/etching process and is patterned.
The film of deposition materials can amplify bottom pattern and form uneven flat surfaces on existing pattern.Need Uniform flat surfaces produce the active and passive component of smaller and finer and close stacking.Planarization can be used for the table from chip Face removes material and produces uniform flat surfaces.Planarization is directed to use with polishing pad and the surface of chip is polished.Grinding Material and etch chemistries thing are added to the surface of chip during polishing.The mechanical behavior of the abrasive material of combination and chemicals Corrosion behavior removes any irregular appearance, causes uniform flat surfaces.
Rear end manufacture, which refers to, to be cut the chip of completion or is divided into each semiconductor element and then encapsulates semiconductor element For structural support and it is environmentally isolated.For dividing semiconductor tube core, chip is non-along the referred to as chip of saw lanes or line Functional area is by scribing and fractures.Split chip using laser cutting tool or saw blade.Upon splitting, each transistor Core is installed to package substrate, the package substrate include pin or contact pad for other systems component connection.Half The contact pad formed on conductor tube core is then attached to the contact pad in encapsulation.Electrical connection can use solder projection, post Shape projection, conducting resinl or wire bonding are made.Sealant or other moulding materials are deposited in encapsulation to provide physical support And electric isolution.The encapsulation of completion is subsequently inserted into electric system and causes the feature of semiconductor devices for other systems portion Part can use.
Fig. 1 illustrates there is chip carrier substrate or PCB 52 electronic device 50, the chip carrier substrate or printed circuit Plate（PCB）52 have the multiple semiconductor packages of installation in its surface.Depending on application, electronic device 50 can have one kind The semiconductor packages of type or polytype semiconductor packages.For explanatory purposes, figure 1 illustrates different types of Semiconductor packages.
Electronic device 50 can be that the autonomous system for performing one or more Electricity Functionals is filled with using semiconductor package.Replace Ground, electronic device 50 can be the subassemblies of larger system.Helped for example, electronic device 50 can be cell phone, individual digital Reason（PDA）, DV（DVC）An or part for other electronic communication devices.Alternatively, electronic device 50 can be figure Card, NIC or other signal processing cards that can be inserted into computer.Semiconductor packages can include microprocessor Device, memory, application specific integrated circuit（ASIC）, logic circuit, analog circuit, RF circuits, discrete device or other transistors Core or electric part.It is vital that miniaturization and weight reduction are acceptable to the market for these products.Between semiconductor devices Distance must reduce to realize higher density.
In Fig. 1, PCB 52 is provided for mount to the structural support of the semiconductor packages on PCB and is electrically interconnected general Property substrate.Use evaporation, electrolytic coating, chemical plating, silk-screen printing or other suitable metal deposition process, electrically conductive signal Trace 54 is formed on PCB 52 surface or in its layer.Signal traces 54 provide semiconductor packages, installation part and its Telecommunication between each in his external system components.Trace 54 also into semiconductor packages each provide power and Grounding connection.
In certain embodiments, semiconductor devices has two encapsulation ranks.First order encapsulation is for mechanically and electrically attached Even technology of the semiconductor element to intermediate carrier.Second level encapsulation, which is related to, mechanically and electrically attaches intermediate carrier to PCB.In other realities Apply in example, semiconductor devices can only have first order encapsulation, and wherein tube core is directly installed to PCB mechanically and electrically.
For illustration purposes, if showing to include the dry type of bonding wire encapsulation 56 and flip-chip 58 on PCB 52 The first order encapsulates.If in addition it is shown that the second level encapsulation for the dry type installed on PCB 52, including ball grid array（BGA）60、 Bump chip carrier（BCC）62nd, dual-inline package（DIP）64th, Land Grid Array（LGA）66th, multi-chip module（MCM） 68th, quad flat non-leaded chip package（QFN）70 and quad-flat-pack 72.Depending on system requirements, first and second are used The semiconductor packages of any combinations configuration and any combinations of other electronic units of level encapsulated type may be coupled to PCB 52.In certain embodiments, electronic device 50 includes single attached semiconductor packages, and other embodiment needs multiple interconnection Encapsulation.By combining one or more semiconductor packages on single substrate, pre-constructed unit can be attached to electronics by manufacturer In device and system.Because semiconductor packages includes complicated feature, less expensive part and streamline system can be used Technique is made to manufacture electronic device.Resulting device, which is less inclined to, to break down and less expensive for manufacturing, leads Cause the less cost for consumer.
Fig. 2 a-2c show that exemplary semiconductor encapsulates.Fig. 2 a illustrate that the DIP's 64 being arranged on PCB 52 is further thin Section.Semiconductor element 74 includes active region, the active region include be embodied as electricity design according to tube core and in tube core shape Into and be electrically interconnected active device, passive device, conductive layer and dielectric layer analog or digital circuit.For example, circuit can With including one or more transistors, diode, inductor, capacitor, resistor and the active area in semiconductor element 74 Other circuit elements formed in domain.Contact pad 76 is such as aluminium（Al）, Cu, tin（Sn）, nickel（Ni）, gold（Au）Or silver（Ag） One or more layers conductive material, and be electrically connected to the circuit element formed in semiconductor element 74.In the DIP 64 assembling phase Between, semiconductor element 74 is installed to using gold-silicon congruent melting layer or the adhesive material of such as hot epoxy material or epoxy resin Intermediate carrier 78.Packaging body includes the insulative potting material of such as polymer or ceramics.Wire 80 and bonding wire 82 provide half Electrical interconnection between conductor tube core 74 and PCB 52.Sealant 84 is deposited in encapsulation, with by preventing moisture and particle from entering Encapsulate and pollute semiconductor element 74 or bonding wire 82 and carry out environmental protection.
Fig. 2 b illustrate the further detail below for the BCC 62 being arranged on PCB 52.Semiconductor element 88 using underfilling or Person's epobond epoxyn material 92 and on the carrier 90.Bonding wire 94 provides first between contact pad 96 and 98 Level encapsulation interconnection.Moulding compound or sealant 100 are deposited on semiconductor element 88 and bonding wire 94, so as to provide thing for device Reason support and electric isolution.Contact pad 102 uses the suitable metal deposition process of such as electrolytic coating or chemical plating etc And formed on PCB 52 surface to prevent oxidation.Contact pad 102 is electrically connected to one or more conductions in PCB 52 Signal traces 54.Projection 104 is formed between BCC 62 contact pad 98 and PCB 52 contact pad 102.
In figure 2 c, encapsulated using the flip-chip variety first order and semiconductor element 58 is installed to middle load face-down Body 106.The active region 108 of semiconductor element 58 includes active device, the nothing for being embodied as being formed according to the electricity design of tube core The analog or digital circuit of source device, conductive layer and dielectric layer.For example, circuit can include one or more transistors, Other circuit elements in diode, inductor, capacitor, resistor and active region 108.Semiconductor element 58 is by convex Block 110 is electrically and mechanically connected to carrier 106.
Encapsulated using using the BGA types second level of projection 112, BGA 60 is electric and is mechanically connected to PCB 52.Semiconductor Tube core 58 is electrically connected to the conductive signal trace 54 in PCB 52 by projection 110, signal wire 114 and projection 112.Moulding compound or Sealant 116 is deposited on semiconductor element 58 and carrier 106 to provide physical support and electric isolution for device.Flip-chip Semiconductor devices provide from the active device on semiconductor element 58 to PCB 52 on conductive traces short-range missile power path so as to Reduce signal propagation distance, reduce electric capacity and improve overall circuit performance.In another embodiment, semiconductor element 58 can make With the encapsulation of the flip-chip variety first order come it is direct mechanically and electrically be connected to PCB 52 and without using intermediate carrier 106.
Fig. 3 a show the semiconductor wafer 120 with the basal substrate material 122 for structural support, the basal substrate material Expect all silicon in this way, germanium, GaAs, indium phosphide or carborundum.As described above, formed on chip 120 as described above by non- The multiple semiconductor elements or part 124 that wafer area or saw lanes 126 separate between active tube core.Saw lanes 126 provide cutting Region by semiconductor wafer 120 to be divided into each semiconductor element 124.
Fig. 3 b show the profile of a part for semiconductor wafer 120.Each semiconductor element 124 has rear surface 128 With active surface 130, the active surface is formed comprising the electric Design and Features being embodied as according to tube core and in tube core and electricity is mutual The analog or digital circuit of the active device, passive device, conductive layer and the dielectric layer that connect.For example, circuit can include one Individual or more transistor, diode and other circuit elements for being formed in active surface 130 are to realize such as numeral letter Number processor（DSP）, ASIC, the analog circuit of memory or other signal processing circuits etc or digital circuit.Transistor Core 124 can also include such as integrated passive devices of inductor, capacitor and resistor（IPD）For RF signal transactings.
Using PVD, CVD, electrolytic coating, chemical plating technique or other suitable metal deposition process in active surface Conductive layer 132 is formed on 130.Conductive layer 132 can be one in Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials Layer or more layer.The operation of conductive layer 132 is the contact pad for the circuit being electrically connected on active surface 130.Conductive layer 132 can be with Be formed as the contact pad being arranged side by side apart from the distance of edge first of semiconductor element 124, as shown in Figure 3 b.Alternatively, lead Electric layer 132 can be formed as the contact pad in multiple rows so that the first row contact pad apart from the edge first of tube core away from Arranged from arrangement, and with edge second distance of the alternate second row contact pad of the first row apart from tube core.
Using PVD, CVD, silk-screen printing, spin coating or spraying, insulation or passivation layer 134 is conformal applies in active surface 130 On.Insulating barrier 134 includes silica (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), one or more layers of aluminum oxide (Al2O3) or the other materials with similar insulation and structure attribute.Insulating barrier 134 Cover active surface 130 and provide protection for active surface 130.By using the laser of laser 136 directly melt (LDA) or Other appropriate process, a part for insulating barrier 134 is removed, so as to expose conductive layer 132 and be prepared for follow-up electrical interconnection.
In figure 3 c, semiconductor wafer 120 is divided into respectively by saw lanes 126 using saw blade or laser cutting tool 138 Individual semiconductor element 124.
Associated with Fig. 1 and 2 a-2c, Fig. 4 a-4h and 5a-5i illustrate to form the Fo- with PWB modularization perpendicular interconnection units PoP technique.Fig. 4 a show to be laminated the section view of a part for core 140.Optional conductive layer 142 is formed at core 140 Surface 144 on, and optional conductive layer 146 is formed at the surface 148 of core.Conductive layer 142 and 146 uses such as Cu paper tinsels Stacking, printing, PVD, CVD, sputtering, the metal deposition process of electrolytic coating and chemical plating are formed.Conductive layer 142 and 146 Can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W) or other suitable conductive materials.In an implementation In example, conductive layer 142 and 146 is Cu paper tinsels, has the thickness of 20-200 microns (μm).Conductive layer 142 and 146 can pass through wet method Etch process is thinned.
In fig. 4b, using laser drill, machine drilling, deep reaction ion(ic) etching (DRIE) or other appropriate process, Form multiple through holes 150 through stacking core 140 and conductive layer 142 and 146.Through hole 150 extends through stacking core 140.Through hole 150 is cleaned by desmear technique.
In Fig. 4 c, using the metal deposition process of such as printing, PVD, CVD, sputtering, electrolytic coating and chemical plating, Conductive layer 152 is formed in the side wall of stacking core 140, conductive layer 142 and 146 and through hole 150.Conductive layer 152 can be One or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W or other suitable conductive materials.In one embodiment, conductive layer 152 Including the first Cu layers formed by chemical plating, followed by the 2nd Cu layers formed by electrolytic coating.
In figure 4d, the remainder of through hole 150 is filled using the insulation with filler material 154 or conductive material. Insulating materials with insulating packing can be with filler and SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar One or more polymer dielectric materials of the other materials of insulation and structure attribute.Conducting filler material can be Al, One or more layers of Cu, Sn, Ni, Au, Ag or other suitable conductive materials.In one embodiment, filler material 154 can be Polymer connector.Alternatively, filler material 154 is Cu cremes.Through hole 150 can also be left as room, that is, is not had and filled out Expect material.Filler material 154 is selected as softer than conductive layer 152 or submissiveer.Through hole 150 with filler material 154 is logical Cross allow conductive layer 152 deform under stress or alteration of form and reduce rupture or be layered incidence.Through hole 150 can also be complete Filled entirely with conductive layer 152.
In figure 4e, using the metal deposition process of such as printing, PVD, CVD, sputtering, electrolytic coating and chemical plating, Conductive layer 156 is formed on conductive layer 152 and filler material 154.Conductive layer 156 can be Al, Cu, Sn, Ni, Au, Ag, Ti, W Or other suitable conductive materials one or more layers.In one embodiment, conductive layer 156 includes what is formed by chemical plating First Cu layers, followed by the 2nd Cu layers formed by electrolytic coating.
In Fig. 4 f, the part of conductive layer 142,146,148,152 and 156 is by wet etching process by patterning Photoresist layer is removed, so as to expose stacking core 140 and leave the conductive pole or conductive vertical through stacking core 140 Straight interconnection structure 158.Using vacuum laminated, spin coating, spraying, silk-screen printing or other typographies, insulation or the shape of passivation layer 160 Into in stacking core 140 and conductive vertical interconnection structure 158.Insulating barrier 160 include one layer of polymer dielectric material or Multilayer, it is with or without SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with other of similar insulation and structure attribute The insulating packing of material.A part for insulating barrier 160 is removed by etch process or LDA, so as to expose conductive layer 156 and Promote the formation of subsequent conductive layer.
Using the metal deposition process of such as electrolytic coating and chemical plating, optional conductive layer 162 can be formed at dew On the conductive layer 156 gone out.Conductive layer 162 can be Al, Cu, Sn, Ni, Au, Ag, Ti, W or one layer of other suitable conductive materials Or multilayer.In one embodiment, conductive layer 162 is Cu protective layers.
Stacking core 140 with vertical interconnecting structure 158 constructs one or more PWB modularizations perpendicular interconnection units, It is arranged between semiconductor element or encapsulation so as to promote the electrical interconnection for Fo-PoP.Fig. 4 g show to be organized in PWB moulds The top view of stacking core 140 in block unit 164-166.PWB modular units 164-166 is included in the phase of PWB units To the vertical interconnecting structure 158 of the multirow extended between surface.PWB units 164-166 is arranged to be integrated in Fo-PoP, It is dimensionally different from each other according to resulting devices configuration and therefore following article is discussed more fully.Although PWB units 164- 166 are illustrated as including square or rectangle occupy-place area in figure 4g, and alternatively, PWB units may include cross (+), be at an angle of Or " L shape ", circle, the occupy-place area of ellipse, hexagon, octagonal, star shape or any geometry.Fig. 4 h are shown The stacking core 140 of each PWB modular units 164 and 166 is divided into using saw blade or laser cutting tool 168.
Fig. 5 a show the section view of the part of carrier or temporary base 170, and the carrier or temporary base 170, which include, sacrifices Base material, such as silicon, polymer, beryllium oxide, glass or other suitable inexpensive rigid materials for structural support.Boundary Surface layer or two-sided tape 172, which are formed on carrier 170, is used as temporary adhesion junction film, etching stopping layer or hot releasing layer.
PWB modular units 164-166 from Fig. 4 h is installed to boundary layer 172 and carrier 170 using Pick-and-Place operations. After placing PWB units 164-166, the semiconductor element 124 from Fig. 3 c is using Pick-and-Place operations with active surface 130 towards load The mode of body orientation is installed to boundary layer 172 and carrier 170.Fig. 5 b show semiconductor element 124 and PWB units 164-166 peaces It is attached to carrier 170 and makes chip 174 as reconstruct.The distance D1 that semiconductor element 124 extends on PWB units 164-166 is more than 1 μm, such as 1-150 μm.Skew between PWB units 164-166 and semiconductor element 124 subtracts during follow-up back-grinding step Small pollution.
In fig. 5 c, printed using creme, compression forming, transfer formation, fluid sealant shaping, vacuum laminated, spin coating Or other suitable coaters, sealant or moulding compound 176 are deposited on semiconductor element 124, PWB units 164-166 and carrier 170 On.Sealant 176 can be polymer composite material, such as epoxy resin with filler, the epoxy propylene with filler Sour fat or the polymer with appropriate filler.Sealant 176 is nonconducting and protection semiconductor devices is exempted from the environment By external key elements and pollutant effects.
In figure 5d, carrier 170 and boundary layer 172 pass through chemical etching, mechanical stripping, chemically mechanical polishing (CMP), machine Tool grinding, hot baking, UV light, laser scanning or wet method are peeled off and are removed, so as to expose insulating barrier 134, PWB units 164-166 With sealant 176.
In Fig. 5 e, accumulation interconnection structure 180 is formed at semiconductor element 124, PWB units 164-166 and sealant 176 On.Using PVD, CVD, stacking, printing, spin coating or spraying, it is mono- that insulation or passivation layer 182 are formed at semiconductor element 124, PWB On first 164-166 and sealant 176.Insulating barrier 182 includes dielectric one layer or more of low temperature (being less than 250oC) solidification polymer Layer, it is with or without such insulating packing, such as SiO2, Si3N4, SiON, Ta2O5, Al2O3, rubber grain or tool There is the other materials of similar insulation and structure attribute.The part of insulating barrier 182 can be removed by etch process so as to expose PWB Unit 164-166 vertical interconnecting structure 158 and the conductive layer 132 of semiconductor element 124.
Using the patterning and metal deposition process of such as sputtering, electrolytic coating and chemical plating, conductive layer or RDL 184 It is formed on insulating barrier 182.Conductive layer 184 can be one layer of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials or Multilayer.In one embodiment, conductive layer 184 includes Ti/Cu, TiW/Cu or Ti/NiV/Cu.One part of conductive layer 184 It is electrically connected to the contact pad 132 of semiconductor element 124.Another part of conductive layer 184 is electrically connected to PWB units 164-166 Vertical interconnecting structure 158.According to the Design and Features of semiconductor element 124, the other parts of conductive layer 184 can be electric public Or it is electrically isolated.
Using PVD, CVD, stacking, printing, spin coating or spraying, insulation or passivation layer 186 are formed at insulating barrier 182 and conduction On layer 184.Insulating barrier 186 include low temperature (being less than 250oC) solidification polymer it is dielectric one or more layers, it has or not had There is such insulating packing, such as SiO2, Si3N4, SiON, Ta2O5, Al2O3, rubber grain or with similar insulation and structure The other materials of attribute.The part of insulating barrier 186 can be removed by etch process so as to expose conductive layer 184.
Using the patterning and metal deposition process of such as sputtering, electrolytic coating and chemical plating, conductive layer or RDL 188 It is formed on conductive layer 184 and insulating barrier 186.Conductive layer 188 can be Al, Cu, Sn, Ni, Au, Ag or other Suitable conductive materials Material one or more layers.In one embodiment, conductive layer 188 includes Ti/Cu, TiW/Cu or Ti/NiV/Cu.Conductive layer 188 A part be electrically connected to conductive layer 184.According to the Design and Features of semiconductor element 124, the other parts of conductive layer 188 Can electric public or electric isolution.
Using PVD, CVD, printing, spin coating or spraying, insulation or passivation layer 190 are formed at insulating barrier 186 and conductive layer 188 On.Insulating barrier 190 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or the other materials with similar insulation and structure attribute One or more layers.The part of insulating barrier 190 can be removed by etch process to expose conductive layer 188.
The insulation and the number of conductive layer that accumulation interconnection structure 180 includes depend on the complexity of wiring design simultaneously And with its change.Therefore, accumulation interconnection structure 180 may include any number of insulation and conductive layer to promote relevant transistor The electrical interconnection of core 124.
Using evaporation, electrolytic coating, chemical plating, globule or silk-screen printing technique, conductive bump material is being accumulated On interconnection structure 180 and it is electrically connected to the exposed portion of conductive layer 188.Bump material can have optional flux solvent Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof.For example, bump material can be congruent melting Sn/Pb, high kupper solder Or lead-free solder.Conductive layer 188 is engaged to using suitable attached or joint technology, bump material.In one embodiment, Bump material is flowed back to form spherical balls or projection 192 by heating the material on its fusing point.In some applications In, projection 192 is by secondary back to improve the electrical contact with conductive layer 188.(UBM) can be in projection in under-bump metallization portion 192 times formation.Projection 192 can also be by compression engagement to conductive layer 188.Projection 192 is represented and can formed on conductive layer 188 A type of interconnection structure.The interconnection structure can also use stud bumps, dimpling block or other electrical interconnections.
In Fig. 5 f, a part for sealant 176 and semiconductor element 124 passes through grinding operation quilt using mill 194 Remove, so as to planarize surface and reduce the thickness of sealant.The thickness that sealant 176 retains on PWB units 164-166 D2 is that D2 is 100 μ in one embodiment 1-150 μm between the rear surface 128 of semiconductor element and PWB units 164-166 m.Chemical etching, CMP or plasma dry etching can be used for removing back-grinding damage and semiconductor element 124 and close Residual stress in envelope agent 176 is so as to strengthening package strength.
In Fig. 5 g, dorsal part balance layer 196 is applied to sealant 176, PWB units 164-166 and semiconductor element 124 On.The thermal coefficient of expansion (CTE) of the balanced conductive layer 184 and 188 of dorsal part balance layer 196, such as 30-150ppm/K, and reduce Warpage in encapsulation.In one embodiment, dorsal part balance layer 196 has 10-100 μm of thickness.Dorsal part balance layer 196 can be Any suitable balance layer with appropriate thermal and structure attribute, such as resin coated copper（RCC）Adhesive tape.
In Fig. 5 h, a part for dorsal part balance layer 196 and sealant 176 is removed so as to expose vertical interconnecting structure 158.Using saw blade or laser cutting tool 202, reconstruct, which is made chip 174 and is divided through PWB modular units 164, turns into separation Fo-PoP 204.
Fig. 5 i show the Fo-PoP 210 that projection 198 is formed on the vertical interconnecting structure 158 exposed.Projection 198 is arranged At least 1 μm under the rear surface 128 of semiconductor element 124.Alternatively, projection 198 extends and had on dorsal part balance layer 196 Some height can be the 25-67% of the thickness of semiconductor element 124.
The PWB modular units 164-166 being arranged in Fo-PoP 204 can be with different from each other, together on size and dimension When still provide break-through perpendicular interconnection for Fo-PoP.PWB modular units 164-166 is included with square and rectangular shape, ten Font (+), angled or " L shape ", circular or elliptical shape, hex shape, octagonal shape, star shape are appointed The what interlocking occupy-place area of his geometry.In wafer scale, and before it is split, PWB modular units 164-166 is to interlock Pattern is arranged in around semiconductor element 124 so that the not ipsilateral of semiconductor element is registered to and corresponds to repeat patterns In PWB units multiple not ipsilaterals.Before accumulation interconnection structure 180 is formed on PWB units, PWB units 164-166 Additional metal layer be may also comprise to promote the wiring flexibility of integrated design and increase.
Due to multiple reasons, PWB modular units 164-166 provides utilizes mark for the perpendicular interconnection in Fo-PoP The cost-effective alternative of quasi- laser drilling process.First, PWB units 164-166 can utilize such as substrate fabrication techniques Low-cost manufacturing technique make.Second, standard laser drilling includes high equipment cost and requires to drill through whole encapsulation Thickness, which increase cycle time and reduce manufacture handling capacity.In addition, relative to exclusively being formed by laser drilling process Perpendicular interconnection, be used for perpendicular interconnection using PWB units 164-166 and provide the advantages of improvement to perpendicular interconnection controls.
In another embodiment, Fig. 6 a show the section view of a part for carrier or temporary base 220, the carrier or face When substrate include sacrificial substrate material, such as silicon, polymer, beryllium oxide, glass or for structural support other are suitable low Cost rigidity material.Boundary layer or two-sided tape 224 are formed on carrier 220 as temporary adhesion junction film, etching stopping layer Or hot releasing layer.
In figure 6b, the semiconductor element 124 from Fig. 3 c is oriented using Pick-and-Place operations with active surface 130 towards carrier Mode be installed to boundary layer 224 and carrier 220.Semiconductor element 124 is forced into boundary layer 224 so that the cloth of insulating barrier 134 Put in boundary layer.When semiconductor element 124 is installed to boundary layer 224, the surface 225 of insulating barrier 134 separates with carrier 220 Distance D1.
In fig. 6 c, the PWB modular units 164-166 from Fig. 4 h is installed to the He of boundary layer 224 using Pick-and-Place operations Carrier 220.PWB units 164-166 is forced into boundary layer 224 so that contact surface 226 is arranged in boundary layer.When PWB is mono- When first 164-166 is installed to boundary layer 224, surface 226 has separated distance D2 with carrier 220.D2 can be more than D1 so that PWB Unit 164-166 surface 226 relative to insulating barrier 134 the vertical shift of surface 225.
Fig. 6 d show that semiconductor element 124 and PWB modular units 164-166 are installed to carrier 220 and make crystalline substance as reconstruct Piece 227.Hung down relative to the rear surface 128 of semiconductor element 124 on the PWB units 164-166 surface 228 relative with surface 226 Directly it offset by distance D3, such as 1-150 μm.By by the rear surface on the surface 228 of PWB units 166 and semiconductor element 124 128 separation, by preventing such as Cu of the material from vertical interconnecting structure 158 from polluting the material such as Si of semiconductor element 124, Promote follow-up back-grinding step.
Fig. 6 e show that chip 227 is made in the reconstruct with the PWB modular units 164-166 being arranged on boundary layer 224 Partial top view.PWB units 164-166 includes multirow vertical interconnecting structure 158, its provide PWB units opposite flank it Between break-through perpendicular interconnection.PWB units 164-166 is arranged in around semiconductor element 124 with interlocking pattern.PWB units 164- 166 are arranged in around semiconductor element 124 so that the not ipsilateral of semiconductor element is registered to and corresponded to and made across reconstruct Multiple not ipsilaterals of PWB units in the repeat patterns of chip 227.Multiple saw lanes 230 are aligned simultaneously relative to semiconductor element And extend across PWB units 164-166 so that when chip 227 is made in reconstruct to be divided along saw lanes, each semiconductor element 124 have around outer peripheral areas around semiconductor element or middle arrangement, PWB units 164-166 from segmentation more Individual vertical interconnecting structure 158.Although PWB units 164-166, which is illustrated as having, interlocks square and rectangle occupy-place area, half is arranged in PWB units around conductor tube core 124 may include to have cross (+), angled or " L shape ", circular or oval shape Shape, hex shape, octagonal shape, star shape or any other geometry occupy-place area PWB units.
Fig. 6 f show that chip is made in the reconstruct with cross (+) the PWB modular units 242 being arranged on boundary layer 224 The top view of 240 part.The shape in the technique similar to the PWB units 164-166 as shown in Fig. 4 a-4h of PWB units 242 Into.PWB units 242 include the multirow vertical interconnecting structure 244 similar to vertical interconnecting structure 158, and provide PWB units Break-through perpendicular interconnection between opposite flank.PWB units 242 are arranged in around semiconductor element 124 with interlocking pattern.PWB is mono- Member 242 is arranged in around semiconductor element 124 so that the not ipsilateral of semiconductor element is registered to and corresponded to across reconstruct Make multiple not ipsilaterals of the PWB units in the repeat patterns of chip 240.Multiple saw lanes 246 are right relative to semiconductor element 124 It is accurate and extend across PWB units 242 so that when chip 240 is made in reconstruct to be divided along saw lanes, each semiconductor element 124 have around outer peripheral areas around semiconductor element or middle arrangement, the multiple of PWB units 242 from segmentation hang down Straight interconnection structure 244.After being split by saw lanes 246, vertical interconnecting structure 244 is arranged in inclined from the periphery of semiconductor element In one or more rows of shifting.
Fig. 6 g are shown with angled or " L shape " PWB modular units 252 the weight being arranged on boundary layer 224 Construct the top view of the part of chip 250.PWB units 252 are in the work similar to the PWB units 164-166 as shown in Fig. 4 a-4h Formed in skill.PWB units 252 include the multirow vertical interconnecting structure 254 similar to vertical interconnecting structure 158, and provide PWB Break-through perpendicular interconnection between the opposite flank of unit.PWB units 252 are arranged in around semiconductor element 124 with interlocking pattern. PWB units 252 are arranged in around semiconductor element 124 so that the not ipsilateral of semiconductor element be registered to and corresponding to across Multiple not ipsilaterals of PWB units in the repeat patterns of overweight construction chip 250.Multiple saw lanes 256 are relative to transistor Core 124 is aligned and extends across PWB units 252 so that when chip 250 is made in reconstruct to be divided along saw lanes, each partly leads Body tube core 124 has around outer peripheral areas around semiconductor element or middle arrangement, PWB units 252 from segmentation Multiple vertical interconnecting structures 254.After being split by saw lanes 256, vertical interconnecting structure 254 is arranged in from semiconductor element In one or more rows of periphery skew.
Fig. 6 h are shown with the circle being arranged on boundary layer 224 or the He of PWB modular units 262 of elliptical shape The top view of the part of chip 260 is made in 263 reconstruct.PWB units 262 and 263 are mono- similar to the PWB as shown in Fig. 4 a-4h Formed in first 164-166 technique.PWB units 262 and 263 include the multirow perpendicular interconnection similar to vertical interconnecting structure 158 Structure 264, and the break-through perpendicular interconnection between the opposite flank of PWB units is provided.PWB units 262 and 263 are with interlocking pattern It is arranged in around semiconductor element 124.PWB units 262-263 is arranged in around semiconductor element 124 so that semiconductor element Not ipsilateral be registered to and corresponding to multiple different portions that PWB units in the repeat patterns of chip 260 are made across reconstruct Point.Multiple saw lanes 265 are aligned relative to semiconductor element 124 and extend across PWB units 262 and 263 so that when reconstruct is made Chip 260 along saw lanes be divided when, each semiconductor element 124 have around outer peripheral areas around semiconductor element or Middle arrangement, PWB units 262 and 263 from segmentation multiple vertical interconnecting structures 264.Passing through the segmentation of saw lanes 265 Afterwards, vertical interconnecting structure 264 is arranged in from one or more rows of the periphery skew of semiconductor element.
Fig. 6 i show that the portion of chip 266 is made in the reconstruct with the continuous P WB or PCB panel 267 that are arranged on boundary layer 224 The top view divided.PWB panels 267 are aligned and are layered on the boundary layer 224 with the boundary layer 224 on temporary carrier 220. PWB panels 267 are formed in the technique similar to the PWB units 164-166 as shown in Fig. 4 a-4h, and with panel scale shape Into for example formed as 300-325 millimeters (mm) round panel or 470mm × 370mm rectangular panels.Last panel size is straight It is smaller about 5mm to 15mm than being finally fanned out to display panel substrate size in terms of footpath or length or width.It is 50- that PWB panels 267, which have scope, 250 μm of thickness.In one embodiment, PWB panels 267 have 80 μm of thickness.Similar to the more of vertical interconnecting structure 158 Row vertical interconnecting structure 268 is formed through PWB panels 267, so as to separate each PWB units 270.Vertical interconnecting structure 268 exists Formed around the outer peripheral areas of PWB units 270.
The core of each PWB units 270 by punching, etching, LDA or other be suitable for forming the work of opening 271 Skill removes.Opening 271 forms at center relative to the vertical interconnecting structure 268 of each PWB units 270 and passes through PWB mono- Member 270 is formed so as to expose boundary layer 224.Opening 271 has generally square occupy-place area and is formed as sufficiently large with receiving Semiconductor element 124 from Fig. 3 c.Using Pick-and-Place operations with the active surface 130 of semiconductor element 124 towards boundary layer 224 The mode of orientation, semiconductor element 124 are seated in the boundary layer 224 in opening 271.The edge 272 of opening 271 and half At least 50 μm of gap or distance between conductor tube core 124.It is mono- that PWB panels 267 along saw lanes 269 are divided into each PWB Member 270, and each semiconductor element 124 have around the outer peripheral areas of semiconductor element or middle arrangement it is multiple it is vertical mutually Link structure 268.After being split by saw lanes 269, vertical interconnecting structure 268 can be arranged in the outer peripheral areas of semiconductor 124 In turn into the one or more rows offset from the periphery of semiconductor element.
Continue from Fig. 6 d, Fig. 6 j show to be installed to boundary layer in semiconductor element 124 and PWB modular units 164-166 After 224, reconstruct make chip 227 using saw blade or laser cutting tool 274 by saw lanes 230 by part Ground Split, so as to shape Into passage or opening 276.Passage 276 extends through PWB unit 164-166, and can extend through in addition boundary layer 224 with And part but do not pass through carrier 220 thoroughly.Passage 276 formed vertical interconnecting structure 158 with Fo-PoP conductive through hole it is subsequent The separation being incorporated between its semiconductor element 124.
In Fig. 6 k, printed using creme, compression forming, transfer formation, fluid sealant shaping, vacuum laminated, spin coating Or other suitable coaters, sealant or moulding compound 282 are deposited on semiconductor element 124, PWB units 164-166 and carrier 220 On.Sealant 282 can be polymer composite material, such as epoxy resin with filler, the epoxy propylene with filler Sour fat or the polymer with appropriate filler.Sealant 282 be nonconducting and protect in the environment semiconductor devices from External key elements and pollutant effects.
In Fig. 6 l, the surface 290 of sealant 282 is ground operation using mill 292, so as to planarize surface simultaneously And reduce the thickness of sealant.Grinding operation removes the part of sealant material downwards until the rear surface of semiconductor element 124 128.Chemical etching can be used for removing and planarize sealant 282.Because the surface 228 of PWB units 166 is relative to partly leading The vertical shift of rear surface 128 of body tube core 124 distance D3, it is possible to achieve the removal of sealant 282, without will come from it is vertical mutually The material such as Cu for linking structure 158 removes and is transferred to by accident semiconductor element 124, such as Si.Prevent conductive material from Vertical interconnecting structure 158 is transferred to the risk that semiconductor element 124 reduces the material of pollution semiconductor element.
In Fig. 6 m, using PVD, CVD, silk-screen printing, spin coating or spraying, insulation or passivation layer 296 is conformal applies close Seal on agent 282 and semiconductor element 124.Insulating barrier 296 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar exhausted The other materials of edge and structure attribute one or more layers.Insulating barrier 296 equably covers sealant 282 and semiconductor element 124 and it is formed on PWB units 164-166.Insulating barrier 296 is formed simultaneously after the Part I of sealant 282 is removed And the rear surface 128 exposed of contact semiconductor element 128.Insulating barrier 296 be sealant 282 Part II be removed with Formed before exposing PWB units 164-166.In one embodiment, the attribute of insulating barrier 296 is selected as help and controlled subsequently The Fo-PoP of formation warpage.
In Fig. 6 n, the part of insulating barrier 296 and sealant 282 is removed to form opening 298 and expose vertical mutual Link structure 158.Opening 298 is formed by etching, laser or other appropriate process.In one embodiment, opening 298 is by making Formed with the LDA of laser 300.Material from vertical interconnecting structure 158 is prevented from contact during sealant 282 is removed and partly led Body tube core 124 because opening 298 around the outer peripheral areas around semiconductor element 124 or in be formed at perpendicular interconnection In structure 158 so that vertical interconnecting structure 158 offsets relative to semiconductor element 124 and do not extend to rear surface 128.Separately Outside, time for being removed in sealant 282 from rear surface 128 and semiconductor element 124 expose and vulnerable to pollution when Between, opening 298 is not formed.Because after insulating barrier 296 is arranged on semiconductor element 124, opening 298 is formed, the insulation Layer serves as the barrier layer of the material from the vertical interconnecting structure 158 for being transferred to semiconductor element 124.
In Fig. 6 o, pass through chemical etching, mechanical stripping, CMP, mechanical lapping, hot baking, UV light, laser scanning or wet Method is peeled off, and carrier 220 and boundary layer 224 are made chip 227 from reconstruct and removed, so as to promote the active table in semiconductor element 124 Interconnection structure is formed on face 130 and PWB units 164-166 vertical interconnecting structure 158.
Fig. 6 o also illustrate that interconnection or RDL Part I are formed by the deposition and patterning of insulation or passivation layer 304. Insulating barrier 304 is conformal to be applied to sealant 282, PWB units 164-166 and semiconductor element 124, and has and defer to its profile First surface.Insulating barrier 304 has second flat surfaces relative with first surface.Insulating barrier 304 include SiO2, Si3N4, SiON, Ta2O5, Al2O3 or one or more layers with the other materials similar to insulation and structure attribute.Insulating barrier 304 utilizes PVD, CVD, printing, spin coating, spraying or other appropriate process deposit.The part of insulating barrier 304 is by using laser 305 LDA, etching or other appropriate process remove, so as to form opening 306 on vertical interconnecting structure 158.Opening 306 is exposed vertical The conductive layer 164 of straight interconnection structure 158, for the configuration according to semiconductor element 124 and the follow-up electrical connection of design.
In Fig. 6 p, conductive layer 308 is patterned and is deposited on insulating barrier 304 and semiconductor element 124, and is arranged in It is open in 306 so as to fill the conductive layer 164 and contact conductive layer 132 of opening and contact vertical interconnecting structure 158.It is conductive Layer 308 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials.The deposition of conductive layer 308 makes With PVD, CVD, electrolytic coating, chemical plating or other appropriate process.Conductive layer 308 as RDL operate, so as to will electrical connection from The each point that semiconductor element 124 is extended to outside semiconductor element 124.
Fig. 6 p also illustrate insulation or passivation layer 310 is conformal is applied to insulating barrier 304 and conductive layer 308, and defer to insulation The profile of layer 304 and conductive layer 308.Insulating barrier 310 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar insulation With the other materials of structure attribute one or more layers.Insulating barrier 310 utilizes PVD, CVD, printing, spin coating, spraying or other conjunctions Suitable technique deposits.The part of insulating barrier 310 is removed by using the LDA of laser 311, etching or other appropriate process, from And opening 312 is formed, the part that the opening exposes conductive layer 308 is electrically interconnected for follow-up.
In Fig. 6 q, conductive layer 316 is patterned and is deposited on insulating barrier 310 and conductive layer 308, and is arranged in opening In 312 so as to fill opening and contact conductive layer 308.Conductive layer 316 can be Al, Cu, Sn, Ni, Au, Ag or other are suitable Conductive material one or more layers.The deposition of conductive layer 316 uses PVD, CVD, electrolytic coating, chemical plating or other suitable works Skill.Conductive layer 316 operates as RDL, so as to which electrical connection is extended to outside semiconductor element 124 from semiconductor element 124 Each point.
Fig. 6 q also illustrate insulation or passivation layer 318 is conformal is applied to insulating barrier 310 and conductive layer 316, and defer to insulation The profile of layer 310 and conductive layer 316.Insulating barrier 318 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar insulation With the other materials of structure attribute one or more layers.Insulating barrier 318 utilizes PVD, CVD, printing, spin coating, spraying or other conjunctions Suitable technique deposits.The part of insulating barrier 318 is removed by LDA, etching or other appropriate process, so as to form opening 320, The part that the opening exposes conductive layer 316 is electrically interconnected for follow-up.
In Fig. 6 r, using evaporation, electrolytic coating, chemical plating, globule or silk-screen printing technique, conductive bump material is sunk Product is on conductive layer 316 and in the opening 320 of insulating barrier 318.Bump material can be have optional flux solvent Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof.For example, bump material can be congruent melting Sn/Pb, high kupper solder or unleaded Solder.Bump material is joined to conductive layer 316 using suitable attachment or joint technology.In one embodiment, bump material is led to Cross and heat the material on its fusing point and flowed back to form spherical balls or projection 322.In some applications, projection 322 By secondary back to improve the electrical contact with conductive layer 316.In one embodiment, projection 322 is formed at wetting layer, resistance On the UBM of barrier and adhesive layer.Projection can also compression engagement to conductive layer 316.Projection 322 represents can be in conductive layer 316 The a type of interconnection structure of upper formation.Interconnection structure can also use bonding wire, conductive creme, stud bumps, dimpling Block or other electrical interconnections.
Altogether, insulating barrier 304,310 and 318 and conductive layer 308,316, and conductive projection 322 form accumulation mutually Link structure 324.The number for being included in the insulation in accumulation interconnection structure 324 and conductive layer depends on the complexity that wiring designs Property and with its change.Therefore, accumulation interconnection structure 324 may include any number of insulation with conductive layer to promote You Guan partly to lead The electrical interconnection of body tube core 124.Similarly, before accumulation interconnection structure 324 is formed on PWB units, PWB units 164-166 It may include additional metal layer to promote the wiring flexibility of integrated design and increase.Mutually link in addition, being otherwise included within dorsal part Element in structure or RDL can be integrated into accumulating the part of interconnection structure 324, so as to relative to mutual including front side and dorsal part Connect or RDL encapsulation simplifies manufacture and reduces cost of manufacture.
Fig. 6 r also illustrate that the reconstruct with accumulation interconnection structure 324 makes chip 227 and utilizes saw blade or laser cutting tool 326 It is divided, so as to form each Fo-PoP 328.In one embodiment, Fo-PoP 328 has in the scope less than 1mm Highly.Due to multiple reasons, the PWB modular units 164-166 in Fo-PoP 328 is provided for vertical in Fo-PoP The cost-effective alternative using standard laser bore process of interconnection.First, PWB units 164-166 can be utilized such as The low-cost manufacturing technique of substrate fabrication techniques makes, rather than including high equipment cost and requires to drill through whole encapsulation Thickness（Which increase cycle time and reduce manufacture handling capacity）Standard laser drilling.In addition, relative to exclusively passing through The perpendicular interconnection that laser drilling process is formed, provided using PWB units 164-166 for Fo-PoP perpendicular interconnections to vertical mutual The advantages of improvement even controls.
PWB modular units 164-166 includes a line or multirow vertical interconnecting structure 158, and it provides the relative of PWB units Break-through perpendicular interconnection between side and it is configured to be integrated in the Fo-PoP being subsequently formed.Vertical interconnecting structure 158 includes Through hole 150, it is left fills as room or alternatively with the filler material 154 of such as conductive material or insulating materials. Filler material 154 is particularly selected to be softer than conductive layer 152 or submissiveer.By allowing vertical interconnecting structure 158 pressing Deformation or alteration of form under power, filler material 154 reduce the incidence of rupture or layering.In one embodiment, perpendicular interconnection Structure 158 includes conductive layer 162, and the conductive layer is the oxidation that copper protective layer is used to prevent conductive through hole, thus reduces SMT applications In yield loss.
PWB modular units 164-166 is arranged in Fo-PoP 328 so that the surface 228 of PWB units 166 and PWB are mono- The respective surfaces of member 164 relative to semiconductor element 124 rear surface 128 vertical shift distance D3.D3 separation prevents from coming It is transferred to by accident from the material such as Cu of vertical interconnecting structure 158 and pollutes the material of semiconductor element 124, such as Si.Using LDA or another removal technique separated with grinding operation shown in Fig. 6 l by exposing conductive layer 162, further promote Material contamination of the semiconductor element 124 by vertical interconnecting structure 158 is entered to prevent.In addition, before opening 298 is formed, insulation 296 presence on the rear surface 128 of semiconductor element 124 of layer, which is played, stops that the material from vertical interconnecting structure 158 reaches The effect of semiconductor element.
The PWB modular units 164-166 being arranged in Fo-PoP 328 can be with different from each other, together on size and dimension When still provide break-through perpendicular interconnection for Fo-PoP.PWB units 164-166 include having square and rectangular shape, cross (+), Angled or " L shape ", circular or elliptical shape, hex shape, octagonal shape, star shape or any other is several The interlocking occupy-place area of what shape.In wafer scale, and before it is split, PWB units 164-166 is arranged in interlocking pattern partly to be led Around body tube core 124 so that the not ipsilateral of semiconductor element is registered to and corresponding to the more of the PWB units in repeat patterns Individual not ipsilateral.Before accumulation interconnection structure 324 is formed on PWB units, PWB units 164-166 may also comprise additional gold Wiring flexibility of the category layer to promote integrated design and increase.
Due to multiple reasons, PWB modular units 164-166 provides utilizes mark for the perpendicular interconnection in Fo-PoP The cost-effective alternative of quasi- laser drilling process.First, PWB units 164-166 can utilize such as substrate fabrication techniques Low-cost manufacturing technique make.Second, standard laser drilling includes high equipment cost and requires to drill through whole encapsulation Thickness, which increase cycle time and reduce manufacture handling capacity.In addition, relative to exclusively being formed by laser drilling process Perpendicular interconnection, be used for perpendicular interconnection using PWB units 164-166 and provide the advantages of improvement to perpendicular interconnection controls.
Fig. 7 a show the embodiment of conductive pole or conductive vertical interconnection structure 340, and it has stacking core 342, conductive layer 344 and 346 and filler material 348.Filler material 348 can be conductive material or insulating materials.Conductive layer 344 and stacking core The heart 342 overlaps 0-200 μm.Cu protective layers 350 are formed on conductive layer 346.Insulating barrier 352 is formed at the one of stacking core 342 On individual surface.The part of insulating barrier 352 is removed in order to expose Cu protective layers 350.
Fig. 7 b show the embodiment of conductive pole or conductive vertical interconnection structure 360, and it has stacking core 362, conductive layer 364 and 366 and filler material 368.Filler material 368 can be conductive material or insulating materials.Conductive layer 364 and stacking core The heart 362 overlaps 0-200 μm.Cu protective layers 370 are formed on conductive layer 366.
Fig. 7 c show the embodiment of conductive pole or conductive vertical interconnection structure 380, and it has stacking core 382, conductive layer 384 and 386 and filler material 388.Filler material 388 can be conductive material or insulating materials.Conductive layer 384 and stacking core The heart 382 overlaps 0-200 μm.Cu protective layers 390 are formed on conductive layer 346.Insulating barrier 392 is formed at the one of stacking core 382 On individual surface.Insulating barrier 394 is formed on the apparent surface of stacking core 382.The part of insulating barrier 394 is removed in order to expose Cu Protective layer 386.
Fig. 7 d show the embodiment of conductive pole or conductive vertical interconnection structure 400, and it has stacking core 402, conductive layer 404 and 406 and filler material 408.Filler material 408 can be conductive material or insulating materials.Conductive layer 404 and stacking core The heart 402 overlaps 0-200 μm.
Fig. 7 e show the embodiment of conductive pole or conductive vertical interconnection structure 410, and it has stacking core 412, conductive layer 414 and filler material 416.Filler material 416 can be conductive material or insulating materials.Conductive layer 414 is handed over stacking core 412 It is folded 0-200 μm.Insulating barrier 418 is formed on a surface of stacking core 412.The part of insulating barrier 418 is removed in order to expose Conductive layer 414.Conductive layer 420 is formed on the conductive layer 414 exposed.Cu protective layers 422 are formed on conductive layer 420.Insulation Layer 424 is formed on the apparent surface of stacking core 412.Conductive layer 426 is formed on the conductive layer 414 exposed.
Fig. 7 f show the embodiment of conductive pole or conductive vertical interconnection structure 430, and it has stacking core 432, conductive layer 434 and filler material 436.Filler material 436 can be conductive material or insulating materials.Conductive layer 434 is handed over stacking core 432 It is folded 0-200 μm.Insulating barrier 438 is formed on a surface of stacking core 432.The part of insulating barrier 438 is removed in order to expose Conductive layer 434.Conductive layer 440 is formed on the conductive layer 434 exposed.Cu protective layers 442 are formed on conductive layer 420.Insulation Layer 444 is formed on the apparent surface of stacking core 432.Conductive layer 446 is formed on the conductive layer 434 exposed.Cu protective layers 446 are formed on conductive layer 446.
Fig. 7 g show the embodiment of conductive pole or conductive vertical interconnection structure 450, and it has stacking core 452, conductive layer 454 and 456 and filler material 458.Filler material 458 can be conductive material or insulating materials.Conductive layer 454 and stacking core The heart 452 overlaps 0-200 μm.Cu protective layers 460 are formed on conductive layer 456.Insulating barrier 462 is formed at the one of stacking core 452 On individual surface.The part of insulating barrier 462 is removed in order to expose Cu protective layers 460.Insulating barrier 464 is formed at stacking core 452 On apparent surface.The part of insulating barrier 464 is removed in order to expose Cu protective layers 460.
Fig. 7 h show the embodiment of conductive pole or conductive vertical interconnection structure 470, and it has stacking core 472, conductive layer 474 and 476 and filler material 478.Filler material 478 can be conductive material or insulating materials.Conductive layer 474 and stacking core The heart 472 overlaps 0-200 μm.Cu protective layers 480 are formed on conductive layer 476.Insulating barrier 482 is formed at the one of stacking core 472 On individual surface.Insulating barrier 484 is formed on the apparent surface of stacking core 472.The part of insulating barrier 484 is removed in order to expose Cu Protective layer 480.
Fig. 7 i show the embodiment of conductive pole or conductive vertical interconnection structure 490, and it has stacking core 492, conductive layer 494 and 496 and filler material 498.Filler material 498 can be conductive material or insulating materials.Conductive layer 494 and stacking core The heart 492 overlaps 0-200 μm.Cu protective layers 500 are formed on conductive layer 496.Insulating barrier 502 is formed at the phase of stacking core 492 To on surface.The part of insulating barrier 502 is removed in order to expose Cu protective layers 480.Cu protective layers 504 are formed at the conductive layer exposed On 496.
In Fig. 8 a, multiple projections 510 be formed at Cu paper tinsels 512 either other paper tinsels or with thin patterning Cu or other moisten On the carrier of the moist wood bed of material.Paper tinsel or supporting layer can utilize the heat release adhesive tape for being resistant to reflux temperature and equably be joined to Temporary carrier.In figure 8b, sealant 514 is formed on projection 510 and Cu paper tinsels 512.In Fig. 8 c, Cu paper tinsels 512 are removed simultaneously And the projection 510 in sealant 514 is divided into PWB perpendicular interconnection units using saw blade or laser cutting tool 516 518。
Fig. 9 shows the Fo-PoP 520 for including semiconductor element 522, and the semiconductor element is similar to partly leading from Fig. 3 c Body tube core 124.Semiconductor element 522 has rear surface 524 and the active surface 526 relative with rear surface 524, the active table Face 526 includes be embodied as according to the electric Design and Features of tube core and formed in the tube core and active device of electrical interconnection, passive The analog or digital circuit of device, conductive layer and dielectric layer.Conductive layer 528 is formed on active surface 526 by as electricity The contact pad of the circuit being connected on active surface 526 operates.Insulation or passivation layer 530 is conformal applies in active surface On 526.
Fig. 9 is also illustrated from the lateral shift of semiconductor element 522 and around the outer peripheral areas around semiconductor element 522 Or middle arrangement, the PWB modular units 518 from Fig. 8 a-8c.The rear surface 524 of semiconductor element 522 is from PWB modularizations Unit 518 offset by least 1 μm, similar to Fig. 5 b.Sealant 532 is deposited on around PWB units 518.Accumulate interconnection structure 534, similar to Fig. 5 e accumulation interconnection structure 180, it is formed on sealant 532, PWB units 518 and semiconductor element 522. Insulation or passivation layer 536 are formed on sealant 532, PWB units 518 and semiconductor element 522.Sealant 514 and insulating barrier 536 part is removed in order to expose projection 510.Projection 510 offset by least 1 μm from the rear surface 524 of semiconductor element 522.
Figure 10 is shown similar to Fig. 5 h Fo-PoP 540 embodiment, and wherein sealant 542 is arranged in PWB units 164- Around 166.
In fig. 11 a, semiconductor element 550 has rear surface 552 and active surface 554, and the active surface, which includes, to be realized Active device formed for the electric Design and Features according to tube core in tube core and electrical interconnection, passive device, conductive layer with And the analog or digital circuit of dielectric layer.Conductive layer 556, which is formed and is used as on active surface 554, is electrically connected to active table The contact pad of circuit on face 554 operates.
The mode that later surface 552 orients towards substrate 560 installs semiconductor element 550.Substrate 560 can be PCB.It is more Individual bonding wire 562 is formed between conductive layer 556 and the trace formed on substrate 560 or contact pad 564.Sealant 566 are deposited on semiconductor element 550, substrate 560 and bonding wire 562.Projection 568 is formed at the Contact welding on substrate 560 On disk 570.
Figure 11 b show the Fo-PoP 540 from Figure 10, wherein PWB modular units 164-166 lateral shifts and cloth Put around the outer peripheral areas around semiconductor element 124 or in.Substrate 560 with semiconductor element 550 is installed to Fo- PoP 540, wherein projection 568 are mechanically and electrically connected to PWB modular units 164-166.Fo-PoP 540 semiconductor element 124 are electrically connected to perpendicular interconnection through bonding wire 562, substrate 560, projection 556 and PWB modular units 164-166 Accumulation interconnection structure 180.
Figure 12 a-12b illustrate the process that modular unit is formed from the sealant panel with fine filler.Figure 12 a are shown The section view of a part for sealant panel 578.Sealant panel 578 includes polymer composite material, such as asphalt mixtures modified by epoxy resin Fat, epoxy acrylic acid fat or polymer, suitable fine filler material are deposited on the polymer complex (i.e. less than 45 μm) In material.Fine filler material enables the CTE of sealant panel 578 to be regulated so that the CTE of sealant panel 578 is big In the potting agent material of subsequent deposition.Sealant panel 578 has multiple saw lanes 579, for sealant panel 578 to be divided It is segmented into modules unit.
In Figure 12 b, sealant panel 578 is divided into respectively by saw lanes 579 using saw blade or laser cutting tool 582 Individual modular unit 580.Modular unit 580 has the shape similar with PWB modular units 164-166 shown in Fig. 6 e-6i Or occupy-place area, but without embedded conductive pole or conductive projection.The CTE of modular unit 580 is more than the close of subsequent deposition The CTE of agent material is sealed, so as to reduce the incidence of warpage under heat stress.Essence in the sealant material of modular unit 580 Flour filler also enables the opening for realizing improved laser drill for being subsequently formed, and the opening is formed through modularization list Member 580.
Figure 13 a-13i illustrate another process to form Fo-PoP, and wherein modular unit is from without embedded conductive pole Or the sealant panel of projection is formed.Continue from Fig. 6 b, using Pick-and-Place operations, the modular unit 580 from Figure 12 b is mounted Boundary layer 224 on to carrier 220.In another embodiment, before semiconductor element 124 is installed, the sealing from Figure 12 a Agent panel 578, which is installed to boundary layer 224, turns into 300-325mm round panels or 470mm × 370mm rectangular panels, and opens Mouth feedthrough seal agent panel 578 is to accommodate semiconductor element 124, and sealant panel 578 is divided into modules list Member 580, similar to Fig. 6 i.
When modular unit 580 is installed to boundary layer 224, surface 583 and the boundary layer 224 of modular unit 580 The copline of exposing surface 584 so that surface 583 is not embedded in boundary layer 224.Thus, the phase of surface 583 of modular unit 580 For the vertical shift of surface 225 of insulating barrier 134.
Figure 13 b show that semiconductor element 124 and modular unit 580 are arranged on carrier 220 and make chip as reconstruct 590.The surface 592 of modular unit 580 relative to semiconductor element 124 the vertical shift of rear surface 128.Chip is made in reconstruct 590 using saw blades or laser cutting tool 596 between semiconductor element 124 by modular unit 580 by part Ground Split, So as to form passage or opening 598.Passage 598 extends through modular unit 580, and can additionally extend through interface Layer 224 and partly but be not to pass completely through carrier 220.Passage 598 forms modular unit 580 and semiconductor element 124 Between separation.
In Figure 13 c, printed using creme, compression forming, transfer formation, fluid sealant shaping, vacuum laminated, spin coating Or other suitable coaters, sealant or moulding compound 600 are deposited on semiconductor element 124, modular unit 580 and carrier 220 On.Sealant 600 can be polymer composite material, such as epoxy resin with filler, the epoxy propylene with filler Sour fat or the polymer with appropriate filler.Sealant 600 be nonconducting and protect in the environment semiconductor devices from External key elements and pollutant effects.The CTE of sealant 600 is less than modular unit 580.In Figure 13 d, lost by chemistry Quarter, mechanical stripping, CMP, mechanical lapping, hot baking, UV light, laser scanning or wet method peeling, carrier 220 and boundary layer 224 from Chip removal is made in reconstruct, so as to promote that interconnection is formed on the active surface 130 and modular unit 580 of semiconductor element 124 Structure.
In Figure 13 e, insulation or passivation layer 602 are formed at sealant 600, modular unit 580 and semiconductor element 124 On.Insulating barrier 602 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or the other materials with similar insulation and structure attribute One or more layers.Using PVD, CVD, printing, spin coating, spraying or other appropriate process come depositing insulating layer 602.Insulating barrier 602 part is removed by LDA, etching or other appropriate process, so as to expose conductive layer 132 and modular unit 580 surface 182.
Conductive layer 603 is patterned and is deposited on insulating barrier 602, on semiconductor element 124, and through insulating barrier In 602 openings formed.Conductive layer 603 is electrically connected to the conductive layer 132 of semiconductor element 124.Conductive layer 603 can be Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials one or more layers.In one embodiment, conductive layer 603 includes Ti/Cu, TiW/Cu or Ti/NiV/Cu.The deposition of conductive layer 603 used PVD, CVD, electrolytic coating, chemical plating or other Appropriate process.Conductive layer 603 is operated as RDL, and electrical connection is extended to outside semiconductor element 124 from semiconductor element 124 Each point, so as to which the electric signal of semiconductor element 124 laterally be redistributed across encapsulation.According to semiconductor element 124 Design and Features, each several part of conductive layer 603 can be electric public or are electrically isolated.
Insulation or passivation layer 604 are formed on conductive layer 603 and insulating barrier 602.Insulating barrier 604 include SiO2, Si3N4, SiON, Ta2O5, Al2O3 or one or more layers with the other materials similar to insulation and structure attribute.Using PVD, CVD, Printing, spin coating, spraying or other appropriate process carry out depositing insulating layer 604.A part for insulating barrier 604 by LDA, etching or its He is removed appropriate process, is used to subsequently be electrically interconnected so as to expose conductive layer 603.
Conductive layer 605 is patterned and is deposited on insulating barrier 604, in the opening formed through insulating barrier 604, and electricity It is connected to conductive layer 603 and 132.Conductive layer 605 can be Al, Cu, Sn, Ni, Au, Ag or one of other suitable conductive materials Or multiple layers.In one embodiment, conductive layer 605 includes Ti/Cu, TiW/Cu or Ti/NiV/Cu.The deposition of conductive layer 605 PVD, CVD, electrolytic coating, chemical plating or other appropriate process are used.Conductive layer 605 as RDL operate, will electrical connection from The each point that semiconductor element 124 is extended to outside semiconductor element 124, so as to across encapsulation by the telecommunications of semiconductor element 124 Number laterally redistribute.According to the Design and Features of semiconductor element 124, each several part of conductive layer 605 can electricity it is public or It is electrically isolated.
Insulating barrier 606 is formed on insulating barrier 604 and conductive layer 605.Insulating barrier 606 include SiO2, Si3N4, SiON, Ta2O5, Al2O3 or one or more layers with the other materials similar to insulation and structure attribute.Using PVD, CVD, printing, Spin coating, spraying or other appropriate process carry out depositing insulating layer 606.A part for insulating barrier 606 passes through LDA, etching or other conjunctions Suitable technique is removed, and is used to subsequently be electrically interconnected to expose the part of conductive layer 605 so as to form opening.
Using evaporation, electrolytic coating, chemical plating, globule or silk-screen printing technique, conductive bump material is in conduction On the exposed portion of layer 605.Bump material can be have Al, Sn of optional flux solvent, Ni, Au, Ag, Pb, Bi, Cu, Solder and combinations thereof.For example, bump material can be congruent melting Sn/Pb, high kupper solder or lead-free solder.Using suitable attached or Joint technology, bump material are joined to conductive layer 605.In one embodiment, bump material is molten by heating the material to it Flowed back on point to form spherical balls or projection 607.In some applications, projection 607 by secondary back with improve with The electrical contact of conductive layer 605.In one embodiment, projection 607 is formed at the UBM with wetting layer, barrier layer and adhesive layer On.Projection can also compression engagement to conductive layer 605.The representative of projection 607 can form a type of on conductive layer 605 Interconnection structure.The interconnection structure can also use bonding wire, conductive creme, stud bumps, dimpling block or other electrical interconnections.
Altogether, insulating barrier 602,604 and 606, conductive layer 603,605, and conductive projection 607 form accumulation and mutually linked Structure 610.The number for being included in the insulation in accumulation interconnection structure 610 and conductive layer depends on the complexity of wiring design simultaneously And with its change.Therefore, accumulation interconnection structure 610 may include any number of insulation and conductive layer to promote relevant transistor The electrical interconnection of core 124.In addition, the element being otherwise included within dorsal part interconnection structure or RDL can be integrated into accumulation mutually Link the part of structure 610, so as to manufacture and reduce and be fabricated to relative to including front side and dorsal part interconnection or RDL encapsulation simplification This.
In Figure 13 f, using stacking or other suitable applications techniques, backgrinding tape 614 is applied in accumulation interconnection structure On 610.The insulating barrier 606 and projection 607 of the contact accumulation interconnection structure 610 of backgrinding tape 614.Backgrinding tape 614 is deferred to The profile on the surface of projection 607.Backgrinding tape 614 includes the adhesive tape that thermal resistance is up to 270oC.Backgrinding tape 614 also includes Adhesive tape with hot release function.The example of backgrinding tape 614 includes UV adhesive tapes HT 440 and non-UV adhesive tapes MY-595.The back of the body is ground Mill adhesive tape 614 is follow-up back-grinding and removed from the back surface 624 relative with accumulation interconnection structure 610 of sealant 600 A part for sealant 600 provides structural support.
The back surface 624 of sealant 600 is ground operation so as to planarize and reduce sealing using mill 628 Agent 600 and the thickness of semiconductor element 124.Chemical etching can be used for planarizing and remove sealant 600 and transistor A part for core 124.After grinding operation completion, the rear surface 630 exposed of semiconductor element 124 and modular unit 580 surface 592 and the copline of exposing surface 632 of sealant 600.
In Figure 13 g, it is utilized as reconstruct and makes the backgrinding tape 614 that chip 590 provides structural support, dorsal part balance layer 640 apply on sealant 600, modular unit 580 and semiconductor element 124.In another embodiment, put down in formation dorsal part Weigh before layer 640, backgrinding tape 614 is removed.The CTE of dorsal part balance layer 640 can be conditioned mutually to be linked with balancing to accumulate The CTE of structure 610, so as to reduce the warpage of encapsulation.In one embodiment, the balance of dorsal part balance layer 640 accumulation interconnection structure 610 CTE, such as 30-150ppm/K, and reduce the warpage in encapsulation.Dorsal part balance layer 640 also provides structural support for encapsulation. In one embodiment, dorsal part balance layer 640 has 10-100 μm of thickness.Dorsal part balance layer 640 be also used as it is heat sink with Strengthen the heat dissipation from semiconductor element 124.Dorsal part balance layer 640 can be have appropriate thermal and structure attribute any suitable Balance layer, such as RCC adhesive tapes.
In Figure 13 h, a part for dorsal part balance layer 640 and modular unit 580 is removed to form through hole or opening 644 and by modular unit 580 expose accumulation interconnection structure 610 conductive layer 603.Pass through etching, laser or other conjunctions Suitable technique, using the appropriate clamping with the support tape for structural support or vacuum vacuum foam chuck, form opening 644.In one embodiment, opening 644 is formed by using the LDA of laser 650.The fine filler of modular unit 580 makes Improved laser drill can be realized to form opening 644.Opening 644 can have vertical, slope or step-like sidewalls, and extend Through the surface 583 of insulating barrier 640 and modular unit 580 to expose conductive layer 603.After opening 644 is formed, opening 644 Desmear or cleaning, including particle and organic remains wet-cleaning are carried out, such as utilizes suitable solvent, or alkali and two The single wafer high-pressure injection cleaning of carbonoxide foaming deionized water, so as to remove any particle or remnants from bore process Thing.Using using one or more downstream in O2 and carbon tetrafluoride (CF4), nitrogen (N2) or hydrogen peroxide (H2O2)/ Microwave plasma or reactive ion etching (RIE), it is any to be cleaned from the conductive layer 603 exposed also to perform plasma clean Pollutant.In the embodiment of conductive layer 603 including TiW or Ti adhesive phases, the adhesive phase of conductive layer 603 in single-chip or Etched using Wet-etching agent in batch process, and cleaned followed by cupric oxide.
In Figure 13 i, evaporation, electrolytic coating, chemical plating, globule, silk-screen printing, injection or other suitable works are utilized Skill, on the conductive layer 603 exposed of accumulation interconnection structure 610 of the conductive bump material in opening 644.Bump material can To be that there is Al, Sn of optional flux solvent, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof.For example, bump material can To be congruent melting Sn/Pb, high kupper solder or lead-free solder.Conduction is joined to using suitable attached or joint technology, bump material Layer 603.In one embodiment, bump material is flowed back to form spherical balls by heating the material on its fusing point Or projection 654.In some applications, projection 654 by secondary back to improve the electrical contact with conductive layer 603.UBM layer can be with shape Into under projection 654.Projection can also compression engagement to conductive layer 603.Projection 654 is represented and can formed on conductive layer 603 A type of interconnection structure.The interconnection structure can also use bonding wire, conductive creme, stud bumps, dimpling block or Other are electrically interconnected.Using saw blade or laser cutting tool 656 by the segmentation to form each Fo-PoP 660, and remove Backgrinding tape 614.
Figure 14 illustrates the Fo-PoP 660 after segmentation.Modular unit 580 is around semiconductor element 124 To provide the perpendicular interconnection in Fo-PoP 660 in sealant 600.Modular unit 580 is by the sealant face with fine filler Plate shape is into and the CTE of modular unit 580 is higher than sealant 600, and this provides regulation Fo-PoP 660 overall CTE spirit Activity.Modular unit 580 can have the shape similar with modular unit shown in Fig. 6 e-6i or occupy-place area.It will seal After agent 600 is deposited on modular unit 580 and semiconductor element 124, encapsulation carries out back-grinding process to remove sealant 600 and a part for semiconductor element 124 so that the thickness of modular unit 580 is substantially equal to the thickness of semiconductor element 124 Degree.Dorsal part balance layer 640 is formed on modular unit 580, sealant 600 and semiconductor element 124, so as to provide additional knot Structure supports and prevents the warpages of Fo-PoP 660.Opening 644 is formed through dorsal part balance layer 640 and modular unit 580 to reveal Go out to accumulate the conductive layer 603 of interconnection structure 610.Projection 654 is formed in opening 644, so as to be formed through Fo-PoP's 660 Three-dimensional (3-D) vertical electric interconnection structure.Thus, modular unit 580 does not have the conductive pole for the insertion for being used for vertically being electrically interconnected Or bump material.Opening 644 is formed through modular unit 580 and projection 654 reduces manufacturing step number, while is still vertical It is electrically interconnected and modular unit is provided.
Figure 15 a-15b illustrate the process that modular unit is formed from PCB panel.Figure 15 a show one of PCB panel 670 The section view divided.PCB panel 670 includes polytetrafluoroethylene (PTFE) pre impregnated material (prepreg), FR-4, FR-1, CEM-1 or CEM- 3 combine the one of phenolic aldehyde cotton paper, epoxy material, resin, glass fabric, obscured glass, polyester fiber and other reinforcing fibers or fabric Individual or multiple layer laminates.PCB panel 670 has multiple saw lanes 672, for PCB panel 670 to be divided into modules list Member.In Figure 15 b, using saw blade or laser cutting tool 674, PCB panel 670 is divided into modules by saw lanes 672 Change unit 676.The shape of modular unit 676 or occupy-place area are similar to the PWB modular unit 164-166 shown in Fig. 6 e-6i, But without embedded conductive pole or conductive projection.The CTE of modular unit 676 is more than the sealant material of subsequent deposition CTE, occurs warpage under heat stress so as to reduce.
Figure 16 shows the Fo-PoP 660 similar with Figure 14 embodiment, and wherein modular unit 676 is embedded in sealant 600 In rather than modular unit 580 in.Modular unit 676 is in the sealant 600 around semiconductor element 124 with offer Perpendicular interconnection in Fo-PoP 660.Modular unit 676 is formed from PCB panel, and the CTE of modular unit 676 is higher than Sealant 600, this provides regulation Fo-PoP 660 overall CTE flexibility.The shape of modular unit 676 or occupy-place area The PWB modular units shown in Fig. 6 e-6i can be similar to.Sealant 600 is being deposited on modular unit 676 and semiconductor After on tube core 124, encapsulation carries out back-grinding process so as to remove a part for sealant 600 and semiconductor element 124 so that mould The thickness of block unit 676 is substantially equal to the thickness of semiconductor element 124.Dorsal part balance layer 640 is formed at modular unit 676th, on sealant 600 and semiconductor element 124, so as to provide additional structural supports, and the warpages of Fo-PoP 660 are prevented.Open Mouth 644 is formed through dorsal part balance layer 640 and modular unit 580 to expose the conductive layer 603 of accumulation interconnection structure 610.It is convex Block 654 is formed so as to form the vertical electric interconnection structures of 3-D through Fo-PoP 660 in opening 644.Thus, modular unit 676 do not have the conductive pole or bump material of the insertion for being used for vertically being electrically interconnected.Opening 644 is formed through modular unit 676 The number of manufacturing step is reduced with projection 654, while the modular unit for being vertically electrically interconnected still is provided.
Although one or more embodiments of the present invention have been described in detail, those skilled in the art should realize Arrive, modification can be made to those embodiments in the case of the scope of the present invention referred to without departing from such as following claims And rewriting.

Claims (15)

1. a kind of method for making semiconductor devices, including：
Semiconductor element is provided；
Multiple individual module interconnecting units are provided, each includes core material in the modular interconnection unit and extends through Cross the vertical interconnecting structure of the core material；
First individual module interconnecting unit of the plurality of individual module interconnecting unit is arranged in the periphery of semiconductor element In region；
Sealant is deposited on the semiconductor element and the first individual module interconnecting unit above and around；And
The Part I of the sealant is removed to expose the surface of the semiconductor element, while by the Part II of the sealant Stay in above the first individual module interconnecting unit；And
The Part II of the sealant is removed with the vertical interconnecting structure of exposure the first individual module interconnecting unit.
2. the method for claim 1, it is additionally included in above semiconductor element and the first individual module interconnecting unit and forms interconnection Structure.
3. the method for claim 1, in addition to：Exposing hanging down for the first individual module interconnecting unit relative to the sealant Before straight interconnection structure, insulating barrier is formed on the rear surface of semiconductor element.
4. the method for claim 1 wherein provide multiple individual module interconnecting units also to include：
The first insulating barrier is formed above the first surface of core material；
The second insulating barrier is formed above the second surface of the core material relative with the first surface of core material；
Form the vertical interconnecting structure through core material.
5. the method for claim 1 wherein the interlocking figure that the first individual module interconnecting unit is formed around semiconductor element The part of case.
6. a kind of method for making semiconductor devices, including：
Semiconductor element is provided；
Multiple modular interconnection units are arranged in the outer peripheral areas around semiconductor element and inclined with the semiconductor element Move, wherein the modular interconnection unit includes core material and extends through the conductive interconnecting structure of the core material；
In the semiconductor element and modular interconnection unit above and around deposition sealant;And
The Part I of the sealant is removed, extends to the conductive interconnecting structure of the modular interconnection unit.
7. the method for claim 6, in addition to：
The first insulating barrier is formed above the first surface of core material；
The second insulating barrier is formed above the second surface of the core material relative with the first surface of core material；And
Form the conductive interconnecting structure through core material.
8. the method for claim 6, the wherein conductive interconnecting structure include metal cap and the protective layer formed on metal cap.
9. the method for claim 6, in addition to：
The Part II of the sealant is removed to expose the surface of the semiconductor element.
10. the method for claim 6, it is additionally included in above the semiconductor element and modular interconnection unit and forms interconnection structure.
11. a kind of semiconductor devices, including：
Semiconductor element；
The modular interconnection unit being arranged in the outer peripheral areas around the semiconductor element, wherein the modular interconnection unit It is small including core material and the vertical interconnecting structure for extending through the core material, the height of the wherein modular interconnection unit In the height of the semiconductor element；And
Opening in the sealant being deposited on around the semiconductor element and modular interconnection unit, wherein sealant extends to institute State vertical interconnecting structure.
12. the semiconductor devices of claim 11, in addition to：
The first insulating barrier formed above the first surface of core material；
The second insulating barrier formed above the second surface of the core material relative with the first surface of core material, wherein hanging down Straight interconnection structure is formed through core material.
13. the semiconductor devices of claim 11, the wherein modular interconnection unit have square configuration, rectangular shape, cross Shape, angled or L shape, round-shaped or elliptical shape.
14. the interlocking figure that the semiconductor devices of claim 11, the wherein modular interconnection unit are formed around semiconductor element The part of case.
15. the semiconductor devices of claim 11, in addition to be formed on the semiconductor devices to reduce the insulating barrier of warpage.
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