CN103325421A - Non-volatile memory checkerboard test circuit and detection method thereof - Google Patents
Non-volatile memory checkerboard test circuit and detection method thereof Download PDFInfo
- Publication number
- CN103325421A CN103325421A CN2012100790985A CN201210079098A CN103325421A CN 103325421 A CN103325421 A CN 103325421A CN 2012100790985 A CN2012100790985 A CN 2012100790985A CN 201210079098 A CN201210079098 A CN 201210079098A CN 103325421 A CN103325421 A CN 103325421A
- Authority
- CN
- China
- Prior art keywords
- circuit
- gridiron pattern
- volatility memorizer
- subtracter
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a non-volatile memory checkerboard test circuit, which comprises: a checkerboard address generation circuit, a read control signal generation circuit and a data comparison circuit, wherein the checkerboard address generation circuit comprises N address registers, N adding/subtraction devices with carries/borrows, and an adding/subtraction control circuit, the carry/borrow of the highest bit adding/subtraction device is adopted as a detection end signal, and the detection end signal can judge whether a tested address achieves the maximum value or the minimum value so as to control detection end of the checkerboard test circuit. According to the present invention, the detection end judgment method is simple; and compared with the method in the prior art, the method of the present invention has the following characteristic that: detection end signal formation does not require the additional extreme value register and the additional extreme value comparator so as to substantially simplify the circuit and the design. The invention discloses a non-volatile memory checkerboard testing circuit detection method.
Description
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) field, particularly relate to a kind of non-volatility memorizer gridiron pattern test circuit.The invention still further relates to a kind of detection method of non-volatility memorizer gridiron pattern test circuit.
Background technology
As shown in Figure 1, be the circuit structure diagram of existing non-volatility memorizer gridiron pattern test circuit; Existing non-volatility memorizer gridiron pattern test circuit produces circuit 2 by gridiron pattern address production electric circuit 1, read operation control signal, gridiron pattern data comparison circuit 3, address comparison circuit form, wherein address comparison circuit is comprised of the comparer 6 of the value register 5 in the address of a N position, a N position, and the N bit address of the value register 5 in the N bit address that gridiron pattern address production electric circuit 1 produces and address is worth to compare produces one and detect end signal and control withdrawing from that gridiron pattern tests most.This method is less than or equal to 2 applicable to N bit address correspondence
NThe situation of the non-volatility memorizer 4 of individual storage unit.But the shortcoming of prior art is, the value register 5 in address of a N position and the comparer 6 of a N position must be arranged, and Area comparison is large.
Summary of the invention
Technical matters to be solved by this invention provides a kind of non-volatility memorizer gridiron pattern test circuit, can greatly simplify circuit and design, reduces circuit area.
For solving the problems of the technologies described above, it is 2 that non-volatility memorizer gridiron pattern test circuit provided by the invention is used for capacity
NThe non-volatility memorizer of individual storage unit carries out the gridiron pattern test, and the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit, read control signal produce circuit, data comparison circuit.
Described gridiron pattern address production electric circuit is used for the output test address to described non-volatility memorizer, and described gridiron pattern address production electric circuit comprises the adding of N bit address register, the carry/borrow of N bit strip/subtracter and adds/the down control circuit.
Per 1 add/subtracter can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position.
Described N bit address register and N position add/and the annexation of subtracter is:
The 0th add/subtracter is by the value of the 0th bit address register and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register, produces simultaneously a carry/borrow position, delivers to the input end of the 1st totalizer.
The n position adds/and subtracter adds/the value addition of the carry of subtracter/borrow position and n bit address register by the n-1 position, produce new n bit address and deliver to described n bit address register, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to N-1.
With the N-1 position add/carry of subtracter/borrow position is as detecting end signal, the detection that is used for controlling described gridiron pattern test circuit finishes.
Further be improved to, when described detection end signal was 1, the detection of described gridiron pattern test circuit finished.
Further be improved to, described read control signal produces circuit and produces a read control signal, is used for controlling the reading of data that described non-volatility memorizer is positioned at place, described test address; Described detection end signal is input to described read control signal and produces circuit, and when described detection end signal was 1, described read control signal produced the circuit power cut-off.
Further be improved to, whether described data comparison circuit is identical with desired value for detection of the data that read from described non-volatility memorizer; Described detection end signal is input to described data comparison circuit, when described detection end signal is 1, and described data comparison circuit power cut-off.
For solving the problems of the technologies described above, it is 2 that non-volatility memorizer gridiron pattern test circuit provided by the invention is used for capacity
M+ 2
M1The non-volatility memorizer of individual storage unit carries out the gridiron pattern test, makes M greater than M1, and the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit, read control signal produce circuit, data comparison circuit.
Described gridiron pattern address production electric circuit is used for the output test address to described non-volatility memorizer, and described gridiron pattern address production electric circuit comprises the adding of M+1 bit address register, the carry/borrow of M bit strip/subtracter and adds/the down control circuit.
Per 1 add/subtracter can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position.
Described M+1 bit address register and M position add/and the annexation of subtracter is:
The 0th add/subtracter is by the value of the 0th bit address register and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register, produces simultaneously a carry/borrow position, delivers to the input end of the 1st totalizer.
The n position adds/and subtracter adds/the value addition of the carry of subtracter/borrow position and n bit address register by the n-1 position, produce new n bit address and deliver to described n bit address register, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to M-1.
With the M-1 position add/carry of subtracter/borrow position and M1-1 position add/carry of subtracter/borrow position with value as detecting end signal, the detection that is used for controlling described gridiron pattern test circuit finishes.
Further be improved to, when described detection end signal was 1, the detection of described gridiron pattern test circuit finished.
Further be improved to, described read control signal produces circuit and produces a read control signal, is used for controlling the reading of data that described non-volatility memorizer is positioned at place, described test address; Described detection end signal is input to described read control signal and produces circuit, and when described detection end signal was 1, described read control signal produced the circuit power cut-off.
Further be improved to, whether described data comparison circuit is identical with desired value for detection of the data that read from described non-volatility memorizer; Described detection end signal is input to described data comparison circuit, when described detection end signal is 1, and described data comparison circuit power cut-off.
For solving the problems of the technologies described above, the detection method of non-volatility memorizer gridiron pattern test circuit provided by the invention comprises the steps:
Whether step 3, described data comparison circuit read the data that are positioned at described test address and detect the data that read identical with desired value from described non-volatility memorizer.
Step 4, described gridiron pattern address production electric circuit carry out add operation or reducing to described test address.
Step 5, repeating step three and step 4, until described detection end signal is 1 o'clock, described data comparison circuit power cut-off.
Non-volatility memorizer gridiron pattern test circuit of the present invention adopt add/carry of subtracter/borrow position forms as detecting end signal, be the present invention can adopt add/subtracter carry/borrow position judges whether the address overflows, detect end signal thereby form, determination methods is simple.With respect to prior art, the present invention does not need extra value register and extra value comparer to form the detection end signal, thereby can greatly simplify circuit and design, reduces circuit area.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the circuit structure diagram of existing non-volatility memorizer gridiron pattern test circuit;
Fig. 2 is the circuit structure diagram of the embodiment of the invention one non-volatility memorizer gridiron pattern test circuit;
Fig. 3 is the gridiron pattern address production electric circuit figure of the embodiment of the invention one;
Fig. 4 is the gridiron pattern address production electric circuit figure of the embodiment of the invention two.
Embodiment
As shown in Figure 2, be the circuit structure diagram of the embodiment of the invention one non-volatility memorizer gridiron pattern test circuit.The embodiment of the invention one non-volatility memorizer gridiron pattern test circuit carries out the gridiron pattern test for the non-volatility memorizer 14 that to capacity is 2N storage unit, and the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit 11, read control signal produce circuit 12, data comparison circuit 13.
Described gridiron pattern address production electric circuit 11 by address bus be connected non-volatility memorizer 14 and connect, be used for the output test address to described non-volatility memorizer 14.As shown in Figure 3, Fig. 3 is the circuit diagram of the gridiron pattern address production electric circuit 11a of the embodiment of the invention one; Described gridiron pattern address production electric circuit 11a comprises the adding of N bit address register 15, the carry/borrow of N bit strip/subtracter 16 and adds/the down control circuit.
Per 1 add/subtracter 16 can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position.
Described N bit address register 15 and N position add/and the annexation of subtracter 16 is:
The 0th add/subtracter 16 is by the value of the 0th bit address register 15 and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register 15, producing simultaneously a carry/borrow position is C
0, deliver to the input end of the 1st totalizer.
The n position adds/and subtracter 16 adds/the value addition of the carry of subtracter 16/borrow position and n bit address register 15 by the n-1 position, produce new n bit address and deliver to described n bit address register 15, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to N-1.
With the N-1 position add/subtracter 16 carry/the borrow position is C
N-1As detecting end signal, be used for controlling the detection end of described gridiron pattern test circuit.In the example one of the present invention, when described detection end signal was 1, the detection of described gridiron pattern test circuit finished.
Described read control signal produces circuit 12 and produces a read control signal, by control bus be connected non-volatility memorizer 14 and connect, this read control signal is used for controlling the reading of data of described non-volatility memorizer 14; Described detection end signal is input to described read control signal and produces circuit 12, and when described detection end signal was 1, described read control signal produced circuit 12 power cut-offs.
Described data comparison circuit 13 by data bus be connected non-volatility memorizer 14 and connect, whether identical with desired value for detection of the data that from described non-volatility memorizer 14, read; Described detection end signal is input to described data comparison circuit 13, when described detection end signal is 1, and described data comparison circuit 13 power cut-offs.
The detection method of the embodiment of the invention one non-volatility memorizer gridiron pattern test circuit comprises the steps:
Whether step 3, described data comparison circuit 13 read the data that are positioned at described test address and detect the data that read identical with desired value from described non-volatility memorizer 14.
Add operation or reducing are carried out in step 4,11 pairs of described test addresses of described gridiron pattern address production electric circuit.
When add operation is carried out in described test address, the 0th bit test address and 1 addition, n bit test address and n-1 position add/the carry digit addition of subtracter.When the N-1 position add/carry digit of subtracter is C
N-1Be 1 o'clock, reach maximal value.
When reducing was carried out in described test address, subtracted each other the 0th bit test address and 1, and n bit test address adds with the n-1 position/and subtract each other the borrow position of subtracter.When the N-1 position add/the borrow position of subtracter is C
N-1Be 1 o'clock, reach minimum value.
Step 5, repeating step three and step 4 are until described detection end signal is 1 to be C
N-1Being 1 o'clock, also is described test address when reaching maximal value or minimum value, described data comparison circuit 13 power cut-offs.
The embodiment of the invention two non-volatility memorizer gridiron pattern test circuits also can be with reference to circuit structure diagram as shown in Figure 2.It is 2 that the embodiment of the invention two non-volatility memorizer gridiron pattern test circuits are used for capacity
M+ 2
M1The non-volatility memorizer 14 of individual storage unit carries out the gridiron pattern test, makes M greater than M1, and the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit 11, read control signal produce circuit 12, data comparison circuit 13.
Described gridiron pattern address production electric circuit 11 by address bus be connected non-volatility memorizer 14 and connect, be used for the output test address to described non-volatility memorizer 14.
As shown in Figure 4, be the circuit diagram of the gridiron pattern address production electric circuit 11b of the embodiment of the invention two; Described gridiron pattern address production electric circuit 11b comprises the adding of M+1 bit address register 15, the carry/borrow of M bit strip/subtracter 16 and adds/the down control circuit.
Per 1 add/subtracter 16 can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position.
Described M+1 bit address register 15 and M position add/and the annexation of subtracter 16 is:
The 0th add/subtracter 16 is by the value of the 0th bit address register 15 and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register 15, producing simultaneously a carry/borrow position is C
0, deliver to the input end of the 1st totalizer.
The n position adds/and subtracter 16 adds/the value addition of the carry of subtracter 16/borrow position and n bit address register 15 by the n-1 position, produce new n bit address and deliver to described n bit address register 15, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to M-1.
With the M-1 position add/subtracter 16 carry/the borrow position is C
M-1Add with the M1-1 position/subtracter 16 carry/the borrow position is C
M1-1With value as detecting end signal, the detection that is used for controlling described gridiron pattern test circuit finishes.
Described read control signal produces circuit 12 and produces a read control signal, by control bus be connected non-volatility memorizer 14 and connect, this read control signal is used for controlling the reading of data of described non-volatility memorizer 14; Described detection end signal is input to described read control signal and produces circuit 12, and when described detection end signal was 1, described read control signal produced circuit 12 power cut-offs.
Described data comparison circuit 13 by data bus be connected non-volatility memorizer 14 and connect, whether identical with desired value for detection of the data that from described non-volatility memorizer 14, read; Described detection end signal is input to described data comparison circuit 13, when described detection end signal is 1, and described data comparison circuit 13 power cut-offs.
The detection method of the embodiment of the invention two non-volatility memorizer gridiron pattern test circuits comprises the steps:
Whether step 3, described data comparison circuit 13 read the data that are positioned at described test address and detect the data that read identical with desired value from described non-volatility memorizer 14.
Add operation or reducing are carried out in step 4,11 pairs of described test addresses of described gridiron pattern address production electric circuit.
When add operation is carried out in described test address, the 0th bit test address and 1 addition, n bit test address and n-1 position add/the carry digit addition of subtracter.When the M-1 position add/carry digit of subtracter is C
M-1And the M1-1 position add/carry digit of subtracter is C
M1-1Be 1 o'clock all, reach maximal value.
When reducing was carried out in described test address, subtracted each other the 0th bit test address and 1, and n bit test address adds with the n-1 position/and subtract each other the borrow position of subtracter.When the M-1 position add/the borrow position of subtracter is C
M-1And the M1-1 position add/the borrow position of subtracter is C
M1-1Be 1 o'clock all, reach minimum value.
Step 5, repeating step three and step 4 are until described detection end signal is 1 to be C
N-1Being 1 o'clock, also is described test address when reaching maximal value or minimum value, described data comparison circuit 13 power cut-offs.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. non-volatility memorizer gridiron pattern test circuit, being used for capacity is 2
NThe non-volatility memorizer of individual storage unit carries out the gridiron pattern test, it is characterized in that, the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit, read control signal produce circuit, data comparison circuit;
Described gridiron pattern address production electric circuit is used for the output test address to described non-volatility memorizer, and described gridiron pattern address production electric circuit comprises the adding of N bit address register, the carry/borrow of N bit strip/subtracter and adds/the down control circuit;
Per 1 add/subtracter can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position;
Described N bit address register and N position add/and the annexation of subtracter is:
The 0th add/subtracter is by the value of the 0th bit address register and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register, produces simultaneously a carry/borrow position, delivers to the input end of the 1st totalizer;
The n position adds/and subtracter adds/the value addition of the carry of subtracter/borrow position and n bit address register by the n-1 position, produce new n bit address and deliver to described n bit address register, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to N-1;
With the N-1 position add/carry of subtracter/borrow position is as detecting end signal, the detection that is used for controlling described gridiron pattern test circuit finishes.
2. non-volatility memorizer gridiron pattern test circuit as claimed in claim 1 is characterized in that: when described detection end signal was 1, the detection of described gridiron pattern test circuit finished.
3. non-volatility memorizer gridiron pattern test circuit as claimed in claim 1 is characterized in that: described read control signal produces circuit and produces a read control signal, is used for controlling the reading of data that described non-volatility memorizer is positioned at place, described test address; Described detection end signal is input to described read control signal and produces circuit, and when described detection end signal was 1, described read control signal produced the circuit power cut-off.
4. non-volatility memorizer gridiron pattern test circuit as claimed in claim 1, it is characterized in that: whether described data comparison circuit is identical with desired value for detection of the data that read from described non-volatility memorizer; Described detection end signal is input to described data comparison circuit, when described detection end signal is 1, and described data comparison circuit power cut-off.
5. non-volatility memorizer gridiron pattern test circuit, being used for capacity is 2
M+ 2
M1The non-volatility memorizer of individual storage unit carries out the gridiron pattern test, makes M greater than M1, it is characterized in that, the gridiron pattern test circuit comprises: gridiron pattern address production electric circuit, read control signal produce circuit, data comparison circuit;
Described gridiron pattern address production electric circuit is used for the output test address to described non-volatility memorizer, and described gridiron pattern address production electric circuit comprises the adding of M+1 bit address register, the carry/borrow of M bit strip/subtracter and adds/the down control circuit;
Per 1 add/subtracter can both realize 1 bit data with one advance/borrow position or data add and subtract mutually, and export new data and new advancing/borrow position;
Described M+1 bit address register and M position add/and the annexation of subtracter is:
The 0th add/subtracter is by the value of the 0th bit address register and 1 addition/subtract, and produces the 0th new bit address and delivers to described the 0th bit address register, produces simultaneously a carry/borrow position, delivers to the input end of the 1st totalizer;
The n position adds/and subtracter adds/the value addition of the carry of subtracter/borrow position and n bit address register by the n-1 position, produce new n bit address and deliver to described n bit address register, produce simultaneously n position carry/borrow position, wherein n is the value between 1 to M-1;
With the M-1 position add/carry of subtracter/borrow position and M1-1 position add/carry of subtracter/borrow position with value as detecting end signal, the detection that is used for controlling described gridiron pattern test circuit finishes.
6. non-volatility memorizer gridiron pattern test circuit as claimed in claim 5 is characterized in that: when described detection end signal was 1, the detection of described gridiron pattern test circuit finished.
7. non-volatility memorizer gridiron pattern test circuit as claimed in claim 5 is characterized in that: described read control signal produces circuit and produces a read control signal, is used for controlling the reading of data that described non-volatility memorizer is positioned at place, described test address; Described detection end signal is input to described read control signal and produces circuit, and when described detection end signal was 1, described read control signal produced the circuit power cut-off.
8. non-volatility memorizer gridiron pattern test circuit as claimed in claim 5, it is characterized in that: whether described data comparison circuit is identical with desired value for detection of the data that read from described non-volatility memorizer; Described detection end signal is input to described data comparison circuit, when described detection end signal is 1, and described data comparison circuit power cut-off.
9. such as the detection method of the described non-volatility memorizer gridiron pattern of claim 1 to 8 test circuit, it is characterized in that, comprise the steps:
Step 1, in described gridiron pattern address production electric circuit, set the initial value of described test address and output to described non-volatility memorizer;
Step 2, described read control signal produce circuit and produce described read control signal;
Whether step 3, described data comparison circuit read the data that are positioned at described test address and detect the data that read identical with desired value from described non-volatility memorizer;
Step 4, described gridiron pattern address production electric circuit carry out add operation or reducing to described test address;
Step 5, repeating step three and step 4, until described detection end signal is 1 o'clock, described data comparison circuit power cut-off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210079098.5A CN103325421B (en) | 2012-03-23 | 2012-03-23 | non-volatile memory checkerboard test circuit and detection method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210079098.5A CN103325421B (en) | 2012-03-23 | 2012-03-23 | non-volatile memory checkerboard test circuit and detection method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103325421A true CN103325421A (en) | 2013-09-25 |
| CN103325421B CN103325421B (en) | 2016-02-10 |
Family
ID=49194113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210079098.5A Active CN103325421B (en) | 2012-03-23 | 2012-03-23 | non-volatile memory checkerboard test circuit and detection method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103325421B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776194A (en) * | 2016-12-08 | 2017-05-31 | 上海东软载波微电子有限公司 | The method of testing and system of register-bit band |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1462451A (en) * | 2001-04-25 | 2003-12-17 | 皇家菲利浦电子有限公司 | Integrated circuit with self-test device for embedded non-volatile memory and related test method |
| CN1627516A (en) * | 2003-12-10 | 2005-06-15 | 上海华虹Nec电子有限公司 | Test module and test method in use for electrical erasable memory built in chip |
| US20070192657A1 (en) * | 2006-02-14 | 2007-08-16 | Marc Laurent | Configuring flash memory |
| CN101872649A (en) * | 2009-04-27 | 2010-10-27 | 复旦大学 | Test method of one-time programmable resistance memory |
-
2012
- 2012-03-23 CN CN201210079098.5A patent/CN103325421B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1462451A (en) * | 2001-04-25 | 2003-12-17 | 皇家菲利浦电子有限公司 | Integrated circuit with self-test device for embedded non-volatile memory and related test method |
| CN1627516A (en) * | 2003-12-10 | 2005-06-15 | 上海华虹Nec电子有限公司 | Test module and test method in use for electrical erasable memory built in chip |
| US20070192657A1 (en) * | 2006-02-14 | 2007-08-16 | Marc Laurent | Configuring flash memory |
| CN101872649A (en) * | 2009-04-27 | 2010-10-27 | 复旦大学 | Test method of one-time programmable resistance memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776194A (en) * | 2016-12-08 | 2017-05-31 | 上海东软载波微电子有限公司 | The method of testing and system of register-bit band |
| CN106776194B (en) * | 2016-12-08 | 2018-12-28 | 上海东软载波微电子有限公司 | The test method and system of register-bit band |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103325421B (en) | 2016-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102533062B1 (en) | Method and Apparatus for Improving Fault Tolerance in Non-Volatile Memory | |
| US9235542B2 (en) | Signal switching circuit and peripheral component interconnect express connector assembly having the signal switching circuit | |
| KR101212759B1 (en) | Data transfer method with data error check, semiconductor memory and memory system with data error check | |
| CN102970013A (en) | Resetting method and resetting control device of register inside chip based on scanning chain | |
| US9292125B2 (en) | Digital filter, touch sense device including the digital filter, and method for performing the digital filtering | |
| JP6169776B2 (en) | Apparatus and method for detecting clock tampering | |
| CN104485962B (en) | A kind of Portable Data-Acquisition System and its acquisition method | |
| TW201337296A (en) | Automatic test equipment | |
| TWI510797B (en) | Method and system for global low power capture scheme for cores | |
| US20180180651A1 (en) | System and method for testing network-side harmonic component of motor train unit | |
| TW201514987A (en) | Oversampling method for data signal and device using the same | |
| US10193537B2 (en) | Random data generation circuit, memory storage device and random data generation method | |
| CN102200565B (en) | A kind of apparatus for testing chip | |
| CN204256724U (en) | A kind of server memory testing apparatus | |
| CN103325421A (en) | Non-volatile memory checkerboard test circuit and detection method thereof | |
| TWI516946B (en) | Method and apparatus for performing de-skew control | |
| WO2011119405A3 (en) | Method and circuit for testing and characterizing high speed signals using an on-chip oscilloscope | |
| CN105406839A (en) | Circuit and electronic device | |
| CN103325423B (en) | The automatic compare test circuit of data of non-volatility memorizer | |
| CN108536423A (en) | Random data generation circuit, memory storage apparatus and random data production method | |
| US9568553B2 (en) | Method of integrated circuit scan clock domain allocation and machine readable media thereof | |
| TWI598739B (en) | Hard disc expanding device | |
| TWI666826B (en) | Board edge connector | |
| CN106528392A (en) | Aurora protocol-based B3G (beyond third generation) testing tool | |
| CN104467753A (en) | Jump edge detection method and device with glitches capable of being removed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140113 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140113 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |