CN103312162A - Voltage doubler circuit and radio frequency identification label chip comprising voltage doubler circuit - Google Patents
Voltage doubler circuit and radio frequency identification label chip comprising voltage doubler circuit Download PDFInfo
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- CN103312162A CN103312162A CN2012100606417A CN201210060641A CN103312162A CN 103312162 A CN103312162 A CN 103312162A CN 2012100606417 A CN2012100606417 A CN 2012100606417A CN 201210060641 A CN201210060641 A CN 201210060641A CN 103312162 A CN103312162 A CN 103312162A
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Abstract
The invention provides a voltage doubler circuit and a radio frequency identification label chip comprising the voltage doubler circuit, and belongs to the technical field of an integrated circuit (IC) design. In the voltage doubler circuit, NMOS transistors in two transmission paths are replaced by PMOS transistors. The two PMOS transistors are connected in series so as to form a first transmission path, and the other two PMOS transistors are connected in series so as to form a second transmission path. The voltage doubler circuit is high in working efficiency and is not limited by a preparation technology and is especially applicable to the RFID label chip.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, relate to voltage-multiplying circuit, relate in particular to radio-frequency (RF) identification (RFID) label chip that all uses the transistorized voltage-multiplying circuit of PMOS and comprise this voltage-multiplying circuit in the transmission channel.
Background technology
In the IC chip design, often need to use the normal power voltage (V that provides greater than IC itself
DD) voltage source, therefore, usually can the charge pump circuit module be set with booster tension in the IC chip, wherein voltage-multiplying circuit is exactly one of common charge pump circuit.
Figure 1 shows that the voltage-multiplying circuit structural representation of prior art.As shown in Figure 1, in this example, voltage-multiplying circuit 10 comprises four transmission mos transistors 110,120,210,220 and two electric capacity 130,230.Wherein, MOS transistor 110 and 210 is nmos pass transistor, and MOS transistor 120 and 220 is the PMOS transistor; Nmos pass transistor 110 and PMOS transistor 120 are connected in series, to form first transmission channel basically; B point place between the drain terminal/source end of the source of nmos pass transistor 110 end/drain terminal and PMOS transistor 120 arranges electric capacity 130, and the level that B is ordered can be controlled the conducting of nmos pass transistor 210 and PMOS transistor 220 or close; And when 120 conductings of PMOS transistor, the current potential of electric capacity 130 can export output end vo ut to.Equally, nmos pass transistor 210 and PMOS transistor 220 are connected in series, to form second transmission channel basically; A point place between the drain terminal/source end of the source of nmos pass transistor 210 end/drain terminal and PMOS transistor 220 arranges electric capacity 230, and the level that A is ordered can be controlled conducting or the shutoff of nmos pass transistor 110 and PMOS transistor 120; And when 220 conductings of PMOS transistor, the current potential of electric capacity 230 can export output end vo ut to.
The basic functional principle of voltage-multiplying circuit shown in Figure 1 below is described.
Clock signal clk A on being offset to electric capacity 230 (equals normal power voltage V when becoming high level from low level when supposing high level
DD), the clock signal clk B that is offset on the electric capacity 130 side by side becomes low level from high level; Through behind the electric capacity, the A point becomes high level, and the B point is dragged down is low level;
When the B point becomes low level, the grid end of nmos pass transistor 210 and PMOS transistor 220 biasing low level, nmos pass transistor 210 turn-offs, and (for example it equals V to incoming level Vin
DD) be cut off 220 conductings of PMOS transistor, the level signal that A is ordered (for example, 2V
DD) can be transferred to output end vo ut; Simultaneously, this moment, the A point became high level, the grid end biasing high level of nmos pass transistor 110 and PMOS transistor 120, nmos pass transistor 110 conductings, incoming level Vin can be to electric capacity 130 chargings, and PMOS transistor 120 turn-offs simultaneously, and the level signal that B is ordered can be by the 120 transmission outputs of PMOS transistor;
Therefore, keep in the process of high level at the low level of B point maintenance thereafter, A point, the B point that electric capacity 130 connects is connected to incoming level Vin because of nmos pass transistor 110 conductings, thereby keeps incoming level (V
DD).
On the contrary, when the clock signal clk A on being offset to electric capacity 230 became low level from high level, the clock signal clk B that is offset on the electric capacity 130 side by side became high level from low level; Through behind the electric capacity, the B point becomes high level (2V
DD), the A point is dragged down is low level;
When the B point becomes high level, the grid end biasing high level of nmos pass transistor 210 and PMOS transistor 220, nmos pass transistor 210 conductings, incoming level Vin transfers to the A point and electric capacity 230 is charged, PMOS transistor 220 turn-offs, and the level signal that A is ordered can be by the 220 transmission outputs of PMOS transistor; Simultaneously, this moment, the A point became low level, the grid end biasing high level of nmos pass transistor 110 and PMOS transistor 120, and nmos pass transistor 110 turn-offs 120 conductings of PMOS transistor, the level signal that B is ordered (for example, 2V
DD) can be transferred to output end vo ut.
Therefore, keep in the process of high level at the low level of A point maintenance thereafter, B point, same, because nmos pass transistor 210 conductings, the A point is connected with incoming level Vin, thereby remains incoming level (V
DD).
Circulation just can make output end vo ut equal 2V substantially and so forth
DD
But nmos pass transistor 110 and 210 threshold voltage vt h are greater than 0, at normal power voltage V
DDFluctuation takes place and be under the lower situation normal power voltage V of input
DDBe difficult to effectively be transmitted, thereby the current potential that A point and B are ordered is difficult to be recharged draw high and promotes V
DD, be lower than V generally speaking
DD, fill in next time and can not reach 2V in high
DD, therefore, make output end vo ut less than 2V
DD, energy is underutilized, and the operating efficiency of voltage-multiplying circuit 10 reduces greatly.
For this reason, industry is improved voltage-multiplying circuit shown in Figure 1 10, uses threshold voltage to manage the particular device of (or being called " Native NMOS ", depletion type NMOS) close to zero NMOS nmos pass transistor 110 and 210, thereby raises the efficiency.But because the existence of the substrate transformation effect (Body Effect) of Native NMOS, its threshold value can only be close to zero, generally is greater than zero, therefore, still can have the energy loss of transmission, and the operating efficiency of voltage-multiplying circuit is difficult to effective raising.
Summary of the invention
The objective of the invention is to, improve the operating efficiency of voltage-multiplying circuit.
For realizing above purpose or other purposes, the invention provides following technical scheme.
According to an aspect of of the present present invention, a kind of voltage-multiplying circuit (30) is provided, it comprises:
The one PMOS transistor (310);
Be connected in series with a described PMOS transistor (310) and form second MOS transistor (320) of first transmission channel;
The 3rd PMOS transistor (410);
Be connected in series with described the 3rd PMOS transistor (410) and form the 4th MOS transistor (420) of second transmission channel.
According to the voltage-multiplying circuit (30) of one embodiment of the invention, wherein, voltage-multiplying circuit (30) also comprises:
Be respectively applied to control first logical circuit (311), second logical circuit (321), the 3rd logical circuit (411) and the 4th logical circuit (421) of the turn-on and turn-off of a described PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420);
First electric capacity (330), its first end are connected to a PMOS transistor (310) on first transmission channel and the Section Point (D) between second MOS transistor (320), and its second termination is gone into the 4th clock signal (CLKB); And
Second electric capacity (430), its first end are connected to the 3rd PMOS transistor (410) on second transmission channel and the first node (C) between the 4th MOS transistor (420), and its second termination is gone into the 3rd clock signal (CLKA);
Wherein, the level signal of described Section Point (D) is fed and inputs to described first logical circuit (311) and the 4th logical circuit (421), simultaneously, second clock signal (CLKBM) inputs to described first logical circuit (311) and the 4th logical circuit (421);
The level signal of described first node (C) is fed and inputs to described second logical circuit (321) and the 3rd logical circuit (411), and simultaneously, first clock signal (CLKAM) inputs to described second logical circuit (321) and the 3rd logical circuit (411);
The input (Vin) of described voltage-multiplying circuit (30) connects the source end/drain terminal of a described PMOS transistor (310) and the 3rd PMOS transistor (410) simultaneously, and the output (Vout) of described voltage-multiplying circuit (30) connects the drain terminal/source end of described the 2nd PMOS transistor (320) and the 4th PMOS transistor (420) simultaneously.
Voltage-multiplying circuit (30) according to further embodiment of this invention, wherein, described first logical circuit (311), second logical circuit (321), the 3rd logical circuit (411) and/or the 4th logical circuit (421) be used for that the current potential of output low level is 0 substantially, the current potential of high level be substantially 2 times to normal power voltage (V
DD) signal, turn-off during with the conducting when this low level biasing of the grid end of controlling a PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) respectively, in this high level biasing.
In the voltage-multiplying circuit of described arbitrary embodiment (30) before, a described PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) can be depletion type PMOS transistor or enhancement mode PMOS transistor.
In the voltage-multiplying circuit of described arbitrary embodiment (30) before, preferably, described first electric capacity (330) and second electric capacity (430) are mos capacitance.
In the voltage-multiplying circuit of described arbitrary embodiment (30) before, the phase relation of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) is set so that the output voltage of the output of described voltage-multiplying circuit (30) equals to double normal power voltage (V substantially
DD).
In the voltage-multiplying circuit of described arbitrary embodiment (30) before, preferably, the low level of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) and high level are respectively 0 current potential and normal power voltage (V
DD).
In the voltage-multiplying circuit of described arbitrary embodiment (30) before, preferably, low level and the high potential of described first node (C) and Section Point (D) are respectively normal power voltage (V
DD), 2 times to normal power voltage (2V
DD).
According to another aspect of the present invention, a kind of RFID label chip is provided, it comprises any voltage-multiplying circuit (30) that the above reaches.
According to the RFID label chip of one embodiment of the invention, it also comprises: four phase clocks for generation of the signal of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) produce circuit (50).
Technique effect of the present invention is, by the nmos pass transistor in the transmission channel is replaced with the PMOS transistor, and, four PMOS transistors in the voltage-multiplying circuit can be controlled its turn-on and turn-off by four logical circuits respectively, make the efficiency of transmission height of PMOS transistor when conducting of this replacement, therefore, the energy conversion loss of this voltage-multiplying circuit is little, and operating efficiency is greatly enhanced.And it is to realize by circuit design, and it is little that the raising of operating efficiency is prepared process technology limit, especially is used in the big RFID label chip of working power voltage fluctuation range to use.
Description of drawings
From following detailed description by reference to the accompanying drawings, will make above-mentioned and other purposes of the present invention and advantage clear more fully, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the voltage-multiplying circuit structural representation of prior art;
Fig. 2 is the basic structure schematic diagram according to the multiplication of voltage operating circuit of one embodiment of the invention;
Fig. 3 is the sequential schematic diagram of voltage-multiplying circuit when work embodiment illustrated in fig. 2;
Fig. 4 is the circuit module structural representation relevant with voltage-multiplying circuit in the RFID label chip according to one embodiment of the invention.
Embodiment
What introduce below is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Understand easily, according to technical scheme of the present invention, do not changing under the connotation of the present invention, but one of ordinary skill in the art can propose other implementations of mutual alternative.Therefore, following embodiment and accompanying drawing only are the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or restriction to technical solution of the present invention.
Be to improve the operating efficiency of voltage-multiplying circuit, those skilled in the art set about from device architecture and the performance of improving nmos pass transistor more, with promote as shown in Figure 1 nmos pass transistor 110 and 210 efficiency of transmission.And in the present invention, emphatically trigger to improve the operating efficiency of the circuit of multiplication of voltage from the circuit structure of voltage-multiplying circuit.
Figure 2 shows that the basic structure schematic diagram according to the multiplication of voltage operating circuit of one embodiment of the invention.As shown in Figure 2, have two transmission channels between the input Vin of voltage-multiplying circuit 30 and the output end vo ut, input Vin can import normal power voltage V
DDWherein, article one, transmission channel is formed by two PMOS transistors 310 that are connected in series and PMOS transistor 320 substantially, the drain terminal of PMOS transistor 310/source end is connected with input Vin, source end/the drain terminal of PMOS transistor 310 is connected with the drain terminal of PMOS transistor 320/source end, and the source end/drain terminal of PMOS transistor 320 exports output end vo ut to; The second transmission channel is formed by two PMOS transistors 410 that are connected in series and PMOS transistor 420 substantially, the drain terminal of PMOS transistor 410/source end is connected with input Vin, source end/the drain terminal of PMOS transistor 410 is connected with the drain terminal of PMOS transistor 420/source end, and the source end/drain terminal of PMOS transistor 420 exports output end vo ut to.
Node D place between the source end/drain terminal of PMOS transistor 310 and the drain terminal of the PMOS transistor 320/source end arranges electric capacity 330, an end incoming clock signal CLKB of electric capacity 330, and the other end is connected with node D; Equally, the node C place between the source end/drain terminal of PMOS transistor 410 and the drain terminal of the PMOS transistor 420/source end arranges electric capacity 430, an end incoming clock signal CLKA of electric capacity 430, and the other end is connected with node C.Therefore, the current potential of node D is subjected to the current potential of electric capacity 330 and the normal power voltage V that PMOS transistor 310 transmits
DD(Vin input) influence, the current potential of node C is subjected to the current potential of electric capacity 430 and the normal power voltage V that PMOS transistor 410 transmits
DD(Vin input) influence.
In this article, four different clock signal clk A, CLKB that provide, the high level of CLKAM, CLKBM are V
DD, low level is V
SS(V
SS=0V), concrete sequential example in Fig. 3 of clock signal clk A, CLKB, CLKAM, CLKBM provides.
Continue as shown in Figure 2, be the control transistorized conducting of PMOS and/or shutoff, this voltage-multiplying circuit 30 also comprises four logical circuits 311,321,411,421.Wherein, logical circuit 311 and logical circuit 421 incoming clock signal CLKBM, simultaneously, level signal feedback input logic circuit 311 and the logical circuit 421 of node D, the level signal of logical circuit 311, the 421 couples of clock signal clk BM and node D is handled with output signal bm2 and bm1 respectively, and bm2 and bm1 can be used for controlling the turn-on and turn-off of PMOS transistor 310 and PMOS transistor 420 respectively.When 310 conductings of PMOS transistor, V
DDBe transferred to node D; Simultaneously, 420 conductings of PMOS transistor, the level signal of node C is transmitted and exports Vout to.
Simultaneously, logical circuit 321 and logical circuit 411 incoming clock signal CLKAM, simultaneously, level signal feedback input logic circuit 321 and the logical circuit 411 of node C, the level signal of logical circuit 321, the 411 couples of clock signal clk AM and node C is handled with output signal am2 and am1 respectively, and am2 and am1 can be used for controlling the turn-on and turn-off of PMOS transistor 320 and PMOS transistor 410 respectively.When 410 conductings of PMOS transistor, V
DDBe transferred to node C; Simultaneously, 320 conductings of PMOS transistor, the level signal of node D is transmitted and exports Vout to.
By the phase relation of control clock signal clk A, CLKB, CLKAM, CLKBM, when making PMOS transistor 310 and 420 conductings, PMOS transistor 410 and 320 turn-offs, the level output of node C, the level of node D equals V substantially
DDWhen making PMOS transistor 410 and 320 conductings, PMOS transistor 310 and 420 turn-offs, the level output of node D, the level of node C equals V substantially
DDSimultaneously, the level of node C makes the level of node C be pulled up to 2V by electric capacity 430 by CLKA biasing high level signal before output
DD, and when the level output of node C was kept in 420 conductings of PMOS transistor, the level of node C maintained 2V
DD, therefore, Vout can export 2V
DDEqually, the level of node D makes the level of node D be pulled up to 2V by electric capacity 330 by CLKB biasing high level signal before output
DD, and when the level output of node D was kept in 320 conductings of PMOS transistor, the level of node D maintained 2V
DD, therefore, Vout can export 2V
DD
Figure 3 shows that voltage-multiplying circuit embodiment illustrated in fig. 2 sequential schematic diagram when work, wherein, " Low " represents its low level, and " high " represents its high level.In conjunction with Fig. 3 and Fig. 2, the basic functional principle of the voltage-multiplying circuit of this embodiment is described.
At CLKAM from high level (high level high=V
DD) become low level (low level Low=V
SS) time (CLKA is that low level, CLKB are that high level, CLKBM are low level), node C is relatively low level V
DD(low level Low=V
DD), handling through logical circuit 321 and 411, am1 and am2 are raised to V
DD
When CLKA uprises level from low level (CLKAM is that low level, CLKB are that high level, CLKBM are low level), electric capacity 430 charging, with node C from V
DDBe raised to 2 times of V
DD(high level of node C) handled through logical circuit 321 and 411, and am1 and am2 follow node C and be raised to 2 times of V
DD, the PMOS transistor 410 of am1 control turn-offs fully, cuts off node C and Vin, and the PMOS transistor 320 of am2 control turn-offs fully, cuts off node D and Vout;
When CLKB becomes low level from high level (CLKA is that high level, CLKAM are that low level, CLKBM are low level), with node D from 2 times of V
DD(high level) is pulled low to V
DD(low level) handled through logical circuit 311 and 421, and bm1 and bm2 follow node D from high level 2V
DDBe pulled low to V
DD(bm1 is V
DD, because node C is 2V
DD, PMOS transistor 420 is in conducting state, and Vout exports 2V
DD, further work as CLKBM subsequently and be raised to V
DD, bm1 is dragged down is V
SSThe time, more fully conducting of PMOS transistor 420, Vout is maintained 2VDD);
When CLKBM becomes high level from low level (CLKA is that high level, CLKAM are that low level, CLKB are high level), handle through logical circuit 311 and 421, bm1 and bm2 are further from V
DDBe pulled low to low level V
SS(0 current potential), the PMOS transistor 420 complete conductings of bm1 control, the level signal (2V of node C
DD) link to each other with Vout through PMOS transistor 420, Vout is 2 times of V
DDThe PMOS transistor 310 complete conductings of bm2 control, node D links to each other with Vin through PMOS transistor 310, and node D remains input voltage V
DD(because bm2 is 0, PMOS transistor, 310 transmission V
DDNot loss, the level of node D can completely reach V
DD);
Then, based on the essentially identical principle of above process, carry out above inverse process, CLKBM becomes high level by low level, and then, CLKB becomes high level by low level, CLKA becomes low level by high level, and CLKAM becomes high level by low level, and node D can become 2 times of V
DD, and the complete conducting by PMOS transistor 320, Vout exports 2V
DD, PMOS transistor 410 conducting fully under the 0 electric potential signal control of am1, node C is communicated with Vin, becomes V
DD(because am1 is 0, PMOS transistor, 410 transmission V
DDNot loss, the level of node C can completely reach V
DD).
Therefore, in the voltage-multiplying circuit 30, four PMOS transistors 310,320,410,420 conducting all can realize that its shutoff also can be by the 2V of grid end by 0 control of Electric potentials of grid end
DDControl of Electric potentials realizes, therefore, all can realize complete conducting (when the needs conducting) and turn-off (when needs turn-off) fully, as PMOS transistor 310,320,410,420 (particularly PMOS transistor 310,410) the efficiency of transmission height of transfer tube, the operating efficiency of voltage-multiplying circuit effectively improves.
When voltage-multiplying circuit 30 is applied to RFID (radio-frequency (RF) identification) label chip, the normal power voltage V in the RFID label chip
DDFluctuation range big, for example, normal power voltage V
DDNormal voltage when being 1.8V, it can fluctuate in 1.0V to 2.2V scope.At normal power voltage V
DDFluctuation range when big, the nmos pass transistor in the transmission channel in traditional voltage-multiplying circuit (as shown in Figure 1) is difficult to realize complete conducting or shutoff more, therefore, efficiency of transmission is lower.If for improving efficiency of transmission, with the operating voltage reduction of nmos pass transistor, this may cause nmos pass transistor by 2 times of V again
DD(V
DDDuring for higher value) punch through damage.Therefore, the voltage-multiplying circuit 30 of example shown in Figure 2 especially is suitable for and is applied in the RFID label chip.
For example, when voltage-multiplying circuit 10 embodiment illustrated in fig. 1 is applied to the RFID label chip, if V
DDFluctuate to 1.0V (smaller value), the operating efficiency of voltage-multiplying circuit 10 has only about 20%; And if V when being applied to the RFID label chip for voltage-multiplying circuit embodiment illustrated in fig. 2 30
DDFluctuate to 1.0V (smaller value), voltage-multiplying circuit 30 still can be exported the multiplication of voltage near 2V, and operating efficiency still can reach 50% to 65%.
Figure 4 shows that circuit module structural representation relevant with voltage-multiplying circuit in the RFID label chip according to one embodiment of the invention.This RFID label chip comprises that voltage-multiplying circuit 30, four phase clocks produce circuit 50 and normal power voltage module 70, and normal power voltage module 70 provides normal power voltage V for the input (Vin) of voltage-multiplying circuit 20
DD, four phase clocks produce circuit 50 for generation of four different clock signals (CLKA, CLKB, CLKAM, CLKBM), handle back output through voltage-multiplying circuit 30 multiplication of voltages and equal 2V substantially
DDVoltage signal.
It will be appreciated that, the multiplication of voltage output size of the voltage-multiplying circuit 30 among Fig. 2 and Fig. 4 not only depends on its operating efficiency, and (operating efficiency is more high, expression energy conversion efficiency height, the output voltage of output is more close to the twice input voltage), also depend on the size of the output loading of voltage-multiplying circuit 30; More than in the description about the operation principle of voltage-multiplying circuit 30, multiplication of voltage is output as 2V
DDBe not have the situation gained of output loading.Also it will be appreciated that, though, can improve the transistorized efficiency of transmission of PMOS greatly, other working loss is not considered in the output of voltage-multiplying circuit.
In embodiment illustrated in fig. 2, electric capacity 330 and/or 430 can be chosen as mos capacitance, and is simple in structure so relatively, prepares under MOS technology easily.
It will be appreciated that PMOS transistor 310,320,410,420 can be depletion type PMOS transistor, its cut-in voltage V
TScope be preferably more than or equal to? (0 to and be less than or equal between the VDD); PMOS transistor 310,320,410,420 also can be enhancement mode PMOS transistor, its cut-in voltage V
TScope be preferably? (more than or equal to-VDD to and be less than or equal to 0, those skilled in the art can specifically arrange the transistorized concrete threshold voltage of PMOS according to the announcement of the above operation principle.
The RFID label chip that above example has mainly illustrated voltage-multiplying circuit of the present invention and used this voltage-multiplying circuit.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be in not departing from its purport and scope implements with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, and under situation about not breaking away from as the defined spirit of the present invention of appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (10)
1. a voltage-multiplying circuit (30) is characterized in that, comprising:
The one PMOS transistor (310);
Be connected in series with a described PMOS transistor (310) and form second MOS transistor (320) of first transmission channel;
The 3rd PMOS transistor (410);
Be connected in series with described the 3rd PMOS transistor (410) and form the 4th MOS transistor (420) of second transmission channel.
2. voltage-multiplying circuit as claimed in claim 1 (30) is characterized in that, this voltage-multiplying circuit (30) also comprises:
Be respectively applied to control first logical circuit (311), second logical circuit (321), the 3rd logical circuit (411) and the 4th logical circuit (421) of the turn-on and turn-off of a described PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420);
First electric capacity (330), its first end are connected to a PMOS transistor (310) on first transmission channel and the Section Point (D) between second MOS transistor (320), and its second termination is gone into the 4th clock signal (CLKB); And
Second electric capacity (430), its first end are connected to the 3rd PMOS transistor (410) on second transmission channel and the first node (C) between the 4th MOS transistor (420), and its second termination is gone into the 3rd clock signal (CLKA);
Wherein, the level signal of described Section Point (D) is fed and inputs to described first logical circuit (311) and the 4th logical circuit (421), simultaneously, second clock signal (CLKBM) inputs to described first logical circuit (311) and the 4th logical circuit (421);
The level signal of described first node (C) is fed and inputs to described second logical circuit (321) and the 3rd logical circuit (411), and simultaneously, first clock signal (CLKAM) inputs to described second logical circuit (321) and the 3rd logical circuit (411);
The input (Vin) of described voltage-multiplying circuit (30) connects the source end/drain terminal of a described PMOS transistor (310) and the 3rd PMOS transistor (410) simultaneously, and the output (Vout) of described voltage-multiplying circuit (30) connects the drain terminal/source end of described the 2nd PMOS transistor (320) and the 4th PMOS transistor (420) simultaneously.
3. voltage-multiplying circuit as claimed in claim 2 (30), it is characterized in that, the current potential that described first logical circuit (311), second logical circuit (321), the 3rd logical circuit (411) and/or the 4th logical circuit (421) are used for output low level is 0 substantially, the current potential of high level be substantially 2 times to normal power voltage (V
DD) signal, turn-off during with the conducting when this low level biasing of the grid end of controlling a PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) respectively, in this high level biasing.
4. voltage-multiplying circuit as claimed in claim 1 or 2 (30), it is characterized in that a described PMOS transistor (310), second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) are depletion type PMOS transistor or enhancement mode PMOS transistor.
5. as claim 2 or 3 described voltage-multiplying circuits (30), it is characterized in that described first electric capacity (330) and second electric capacity (430) are mos capacitance.
6. as claim 2 or 3 described voltage-multiplying circuits (30), it is characterized in that, the phase relation of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) is set so that the output voltage of the output of described voltage-multiplying circuit (30) equals to double normal power voltage (V substantially
DD).
7. voltage-multiplying circuit as claimed in claim 6 (30), it is characterized in that low level and the high level of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) are respectively 0 current potential and normal power voltage (V
DD).
8. as claim 2 or 3 described voltage-multiplying circuits (30), it is characterized in that low level and the high potential of described first node (C) and Section Point (D) are respectively normal power voltage (V
DD), 2 times to normal power voltage (2V
DD).
9. a radio frequency identification label chip is characterized in that, comprises as each described voltage-multiplying circuit (30) in the claim 1 to 8.
10. radio frequency identification label chip as claimed in claim 9, it is characterized in that, also comprise: four phase clocks for generation of the signal of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) produce circuit (50).
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| CN201210060641.7A CN103312162B (en) | 2012-03-08 | 2012-03-08 | Voltage-multiplying circuit and comprise its radio frequency identification label chip |
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|---|---|---|---|
| CN201210060641.7A CN103312162B (en) | 2012-03-08 | 2012-03-08 | Voltage-multiplying circuit and comprise its radio frequency identification label chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162674A (en) * | 2018-11-08 | 2020-05-15 | 三星电子株式会社 | Charge pump and memory device including the same |
| CN111162674B (en) * | 2018-11-08 | 2024-05-03 | 三星电子株式会社 | Charge pump and memory device including the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111162674A (en) * | 2018-11-08 | 2020-05-15 | 三星电子株式会社 | Charge pump and memory device including the same |
| CN111162674B (en) * | 2018-11-08 | 2024-05-03 | 三星电子株式会社 | Charge pump and memory device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103312162B (en) | 2016-01-13 |
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