CN103311433A - Manufacturing method of resistive random access memory - Google Patents

Manufacturing method of resistive random access memory Download PDF

Info

Publication number
CN103311433A
CN103311433A CN2012100586767A CN201210058676A CN103311433A CN 103311433 A CN103311433 A CN 103311433A CN 2012100586767 A CN2012100586767 A CN 2012100586767A CN 201210058676 A CN201210058676 A CN 201210058676A CN 103311433 A CN103311433 A CN 103311433A
Authority
CN
China
Prior art keywords
metal oxide
functional layer
electrode
binary metal
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100586767A
Other languages
Chinese (zh)
Other versions
CN103311433B (en
Inventor
刘明
赵盛杰
谢常青
刘琦
吕航炳
张满红
霍宗亮
胡媛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201210058676.7A priority Critical patent/CN103311433B/en
Publication of CN103311433A publication Critical patent/CN103311433A/en
Application granted granted Critical
Publication of CN103311433B publication Critical patent/CN103311433B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Memories (AREA)

Abstract

A method of manufacturing a resistive random access memory, the method comprising: forming a first electrode; forming a resistance change functional layer on the first electrode, wherein the resistance change functional layer comprises at least one layer of first binary metal oxide and at least one layer of second binary metal oxide, and the first binary metal oxide and the second binary metal oxide are alternately laminated; carrying out a thermal annealing process; and forming a second electrode on the resistance change functional layer. The metal ions of different metal oxides have difference, and are diffused at the interface of the two metal oxides through an annealing process to form a composite dielectric intermediate and form a structural defect, so that the electrical characteristics of the resistance change functional layer are optimized, and the uniformity of the conversion parameters is improved.

Description

The manufacture method of resistance-variable storing device
Technical field
The present invention relates to semiconductor device and manufacturing technology, more particularly, relate to a kind of manufacture method of resistance-variable storing device.
Background technology
Popular along with the Portable personal device, non-volatility memorizer becomes the research and development emphasis in the semi-conductor industry gradually owing to have and still can keep remember condition and operate advantage such as low-power consumption when non-transformer supply.Non-volatility memorizer in the market is main flow with flash memory (flash) still, but operating voltage is excessive because flash memory exists, service speed is slow, endurance is got well inadequately and owing to shortcomings such as the continuous attenuate of tunnel oxide causes that the retention time falls short of in the device dimensions shrink process, present research and development emphasis has turned to the novel non-volatility memorizer that can replace flash memory gradually.
Resistance-variable storing device (RRAM) since have write operation voltage low, write the erasing time short, the retention time long, non-destructive reads, many-valued storage, simple in structure and storage density advantages of higher, therefore becomes the research emphasis in the present novel non-volatility memorizer spare gradually.The storage principle of resistance-variable storing device is to be based upon on the reversible resistive characteristic of resistive material, that is to say, the resistive material under the signal of telecommunication can high-impedance state (High Resistance State, HRS) and low resistance state (Low Resistance State realizes reversible transformation between LRS).
At present, also have certain dispute at the transformation mechanism of electric resistance changing memory, but the demonstration widely of some mechanism processes has been arranged, solid-state electrolytic solution electric resistance changing memory is exactly wherein a kind of.The basic structure of solid-state electrolytic solution resistance change memory device, as shown in Figure 1, mainly comprise: bottom electrode 11, memory function layer 12 and top electrode 13, it is the metal of inertia that bottom electrode adopts under the electric field action, top electrode adopts the metal of easy oxidation under the electric field action, the material that the memory function layer adopts phase-change material, binary metal oxide material or organic material etc. to have the resistive characteristic.
For the resistance-variable storing device that adopts the binary metal oxide material as the resistive functional layer, industry is interpreted as the mechanism of its electric resistance changing: under the signal of telecommunication, form local conductive filament in the binary metal oxide, conductive filament may be made up of the oxygen room that oxide self decomposes out, also may be formed by the metal ion that electrode is introduced, and the growth course of conductive filament all is at random, and is wayward, therefore causes the discreteness of resistance-variable storing device device transition parameters bigger.
Therefore, improve the discreteness of resistance-variable storing device device transition parameters, improve the uniformity of transition parameters, become the focus of present resistance-variable storing device device research.
Summary of the invention
The embodiment of the invention provides a kind of manufacture method of resistance-variable storing device, optimizes the resistive functional layer, improves the uniformity of transition parameters.
For achieving the above object, the embodiment of the invention provides following technical scheme:
A kind of manufacture method of resistance-variable storing device, described method comprises:
Form first electrode;
Form the resistive functional layer at described first electrode, wherein, described resistive functional layer comprises one deck first binary metal oxide and one deck second binary metal oxide at least at least, and described first binary metal oxide and second binary metal oxide are alternately laminated;
Carry out thermal anneal process;
Form second electrode in described resistive functional layer.
Alternatively, adopt technique for atomic layer deposition to form the resistive functional layer at described first electrode.
Alternatively, described first binary metal oxide is hafnium oxide, and described second binary metal oxide is titanium oxide.
Alternatively, the precursor that adopts in the ald is that unsaturated reaction formation hafnium oxide takes place for TEMAHf and deionized water; The precursor that adopts in the ald is that unsaturated reaction formation titanium oxide takes place for titanium tetrachloride and deionized water.
Alternatively, the chemical dosage ratio that unsaturated reaction forms hafnium oxide taking place is Hf: O=1: 1.5; The chemical dosage ratio that unsaturated reaction formation titanium oxide takes place is Ti: O=1: 1.6.
Alternatively, the gas in the described thermal anneal process is oxygen, nitrogen or their mist.
Alternatively, the annealing region in the described thermal anneal process is 200-1050 ℃, and the scope of annealing time is 30s-30min.
Compared with prior art, technique scheme has the following advantages:
The manufacture method of resistance-variable storing device of the present invention, two kinds of resistive functional layers that binary metal oxide is alternately laminated have been formed, the metal ion of different metal oxides there are differences, as ionic radius with to affinity of oxygen element etc., like this, pass through annealing process, spreading at the interface of two kinds of metal oxides, form compound dielectric intermediate, form fault of construction, thereby optimize the electrology characteristic of resistive functional layer, improve the uniformity of transition parameters.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the basic structure schematic diagram of resistance-variable storing device device;
Fig. 2 is the flow chart of the manufacture method of resistance-variable storing device of the present invention;
Fig. 3-6 is the schematic diagram according to each fabrication stage of the resistance-variable storing device of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
In order to optimize the electrology characteristic of resistive functional layer, improve the uniformity of resistance-variable storing device transition parameters, as shown in Figure 2, the invention provides a kind of manufacture method of resistance-variable storing device, comprising:
Form first electrode;
Form the resistive functional layer at described first electrode, wherein, described resistive functional layer comprises one deck first binary metal oxide and one deck second binary metal oxide at least at least, and described first binary metal oxide and second binary metal oxide are alternately laminated;
Carry out thermal anneal process;
Form second electrode in described resistive functional layer.
In manufacture method of the present invention, two kinds of resistive functional layers that binary metal oxide is alternately laminated have been formed, the metal ion of different metal oxides there are differences, as ionic radius with to affinity of oxygen element etc., like this, pass through annealing process, spreading at the interface of two kinds of metal oxides, form compound dielectric intermediate, form fault of construction, thereby optimize the electrology characteristic of resistive functional layer, improve the uniformity of transition parameters.
In the present invention, the resistive functional layer is by first binary metal oxide and the alternately laminated structure of second binary metal oxide, and first binary metal oxide is different binary metal oxide materials, for example ZrO with second binary metal oxide 2, HfO 2, TiO 2, SiO 2, WO x, NiO, CuO x, ZnO, TaO x, Y 2O 3Etc..
In the present invention, by thermal anneal process, promote spreading at the interface of these two kinds of metal oxides, form compound dielectric intermediate, form fault of construction, thereby optimize the electrology characteristic of resistive functional layer, improve the uniformity of transition parameters.
In order to understand the present invention better, below with reference to the diagram of each fabrication stage, the manufacture method of above-mentioned resistance-variable storing device embodiment is described in detail.
At first, provide substrate 200, with reference to shown in Figure 3.
In this embodiment, substrate 200 can comprise the Si substrate, can also be formed with SiO on the Si substrate 2Insulating barrier.
In other embodiments, described substrate can also include but not limited to other semiconductors or compound semiconductor, as carborundum, GaAs, indium arsenide or indium phosphide.According to the known designing requirement of prior art (for example p-type substrate or n type substrate), substrate 200 can comprise various doping configurations.In addition, can also comprise other devices in the substrate.
Then, form first electrode 202 at described substrate 200, as shown in Figure 3.
In this embodiment, electron beam evaporation process be can utilize, Ti layer and Pt layer on described substrate 200, formed successively as first electrode 202, bottom electrode just, the thickness of described Ti layer can be 20nm, and the thickness of described Pt layer can be 80nm, and the Ti layer is Pt layer and SiO 2The adhesion layer of insulating barrier.
In other embodiments, described first electrode can also be for comprising the single or multiple lift structure of inert metal, inert metal compound or other suitable metal materials, described inert metal example comprises W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, the example of described inert metal compound comprises TiN, TaN, ITO, IZO, can adopt electron beam evaporation, chemical vapour deposition (CVD), pulsed laser deposition, ald, magnetron sputtering or other suitable methods to form.
Then, form resistive functional layer 204 at described first electrode 202, with reference to shown in Figure 4.
In this embodiment, deposit one deck hafnium oxide (HfO by ALD (ald) technology at first electrode 202 2) 204-1, thickness can be 3-10nm, then the thicker titanium oxide (TiO of deposit one deck thereon 2) 204-2, thickness can be 20-30nm, then deposit one deck hafnium oxide (HfO again on titanium oxide 2) 204-3, thickness can be 3-10nm, thereby has formed the resistive functional layer 204 of the stepped construction of being made up of hafnium oxide-titanium oxide-hafnium oxide.
When adopting the ALD technology to deposit, generally include step:
S1, the substrate that will have first electrode places reaction chamber, vacuumizes and heats, and reaches the preparation condition of required technology;
S2 feeds first kind of precursor, and under the air-flow effect, precursor is realized saturated, irreversible chemisorbed at substrate surface;
S3 feeds inert gas, purges substrate surface, under the air-flow effect, with the byproduct of reaction of excessive precursor and the chemisorbed reaction chamber that blows off;
S4 feeds second kind of reaction precursor, in substrate surface generation chemisorbed, thereby with step S2 in be adsorbed on substrate surface first kind of precursor generation chemical reaction form solid-state film;
S5 feeds inert gas at this, purges substrate surface, removes excessive second kind and reacts precursor and byproduct of reaction;
S6, repeating step S2-S5 is up to forming required film thickness.
In order to guarantee the saturated absorption of first kind of reaction precursor, S2-S3 can be repeated repeatedly, and in order to guarantee the saturated absorption of reaction precursor in second, also S4-S5 can be repeated repeatedly.
In the present embodiment, adopt ALD deposition techniques hafnium oxide (HfO 2) time, the presoma of employing is tetramethyl ethyl ester-metal hafnium amine salt (TEMAHf), another kind of presoma adopts deionized water (H 2O).Wherein deionized water adopts and feeds reaction chamber from the volatilization mode, and the volatilization pressure under the TEMAHf normal temperature is less, adopts the method for heating, and heating-up temperature is 100 ℃.Inert gas adopts nitrogen (N 2).On concrete technological parameter, preferable reaction temperature is 250 ℃ in the experiment; Reaction pressure control is below 2mBar; Inert gas flow control is at 200sccm; The reactant service time, TEMAHf control is at 550ms, deionized water control is at 500ms, the time control of inert gas purge is at 2000ms, under such process conditions, by control reduce slightly the dosage of reactants water and faster reaction cycle time realize unsaturated reaction, the stoichiometric proportion of the hafnia film of formation is about Hf: O=1: 1.5.
In the present embodiment, adopt ALD deposition techniques titanium oxide (TiO 2) time, the presoma of employing is titanium tetrachloride (TiCl 4), another kind of presoma adopts deionized water (H 2O).Both all adopt from the volatilization mode and feed reaction chamber, and inert gas adopts nitrogen (N 2).On concrete technological parameter, select 250 ℃ of reaction temperatures in the experiment according to qualifications; Reaction pressure control is below 2mBar; Inert gas flow control is at 200sccm; The reactant service time, titanium tetrachloride control is at 200ms, deionized water control is at 250ms, the time control of inert gas purge is at 1500ms, under such process conditions, by control reduce slightly the dosage of reactants water and faster reaction cycle time realize unsaturated reaction, the stoichiometric proportion of the thin film of titanium oxide of formation is about Ti: O=1: 1.6.
Structure, material and the preparation technology of above resistive functional layer only are example, in other embodiments, can also adopt other materials, other technological parameters to form the resistive functional layer of other structures.
Then, carry out thermal anneal process.
In the present embodiment, the gas of thermal anneal process can be oxygen, nitrogen or their mist etc., and flow can be 0-15L/min; preferably, can be 2L/min, annealing region can be 200-1050 ℃; preferably, can be 400-850 ℃, annealing time can be 30s-30min; preferably can be 30s-20min; after the annealing, stop heating, keep Annealing Protection atmosphere; take out wafer after naturally cooling to low temperature, generally in the time of 200 ℃, take out.By annealing process, spreading at the interface of two kinds of metal oxides, as shown in Figure 5, form compound dielectric intermediate 204-4, form fault of construction, thereby optimize the electrology characteristic of resistive functional layer, improve the uniformity of transition parameters.
At last, form second electrode 206 in resistive functional layer 204, as shown in Figure 6.
In the present embodiment, can utilize the method for electron beam evaporation, deposit Cu and carry out photoetching in described resistive functional layer 204, adopt stripping technology to form second electrode 206, top electrode just, thickness can be 50nm, thereby forms the typical storage devices structure of metal-oxide-metal.In other embodiments, can also adopt other suitable methods to form second electrode of material requested.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet is not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.

Claims (7)

1. the manufacture method of a resistance-variable storing device is characterized in that, described method comprises:
Form first electrode;
Form the resistive functional layer at described first electrode, wherein, described resistive functional layer comprises one deck first binary metal oxide and one deck second binary metal oxide at least at least, and described first binary metal oxide and second binary metal oxide are alternately laminated;
Carry out thermal anneal process;
Form second electrode in described resistive functional layer.
2. manufacture method according to claim 1 is characterized in that, adopts technique for atomic layer deposition to form the resistive functional layer at described first electrode.
3. manufacture method according to claim 2 is characterized in that, described first binary metal oxide is hafnium oxide, and described second binary metal oxide is titanium oxide.
4. manufacture method according to claim 3 is characterized in that, the precursor that adopts in the ald is that unsaturated reaction formation hafnium oxide takes place for TEMAHf and deionized water; The precursor that adopts in the ald is that unsaturated reaction formation titanium oxide takes place for titanium tetrachloride and deionized water.
5. manufacture method according to claim 4 is characterized in that, the chemical dosage ratio that unsaturated reaction formation hafnium oxide takes place is Hf: O=1: 1.5; The chemical dosage ratio that unsaturated reaction formation titanium oxide takes place is Ti: O=1: 1.6.
6. manufacture method according to claim 1 is characterized in that, the gas in the described thermal anneal process is oxygen, nitrogen or their mist.
7. manufacture method according to claim 1 is characterized in that, the annealing region in the described thermal anneal process is 200-1050 ℃, and the scope of annealing time is 30s-30min.
CN201210058676.7A 2012-03-07 2012-03-07 Manufacturing method of resistive random access memory Active CN103311433B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210058676.7A CN103311433B (en) 2012-03-07 2012-03-07 Manufacturing method of resistive random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210058676.7A CN103311433B (en) 2012-03-07 2012-03-07 Manufacturing method of resistive random access memory

Publications (2)

Publication Number Publication Date
CN103311433A true CN103311433A (en) 2013-09-18
CN103311433B CN103311433B (en) 2015-07-22

Family

ID=49136428

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210058676.7A Active CN103311433B (en) 2012-03-07 2012-03-07 Manufacturing method of resistive random access memory

Country Status (1)

Country Link
CN (1) CN103311433B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140391A (en) * 2015-07-02 2015-12-09 河北大学 Double-charge injection trap memory and preparation method thereof
CN105575991A (en) * 2014-09-04 2016-05-11 财团法人交大思源基金会 Memory structure and method of forming the same
WO2017157074A1 (en) * 2016-03-18 2017-09-21 中国科学院微电子研究所 Selector for use in bipolar resistive memory and manufacturing method for selector
CN110828658A (en) * 2018-08-08 2020-02-21 北京北方华创微电子装备有限公司 Preparation method of resistive random access memory device and resistive random access memory device
CN111009609A (en) * 2019-12-24 2020-04-14 华中科技大学 Superlattice memristor functional layer material, memristor unit and preparation method of superlattice memristor functional layer material
CN114068808A (en) * 2021-11-03 2022-02-18 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same
CN116507195A (en) * 2023-06-21 2023-07-28 武汉大学 Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279601A (en) * 1996-02-14 1996-10-22 Hitachi Ltd Manufacture of semiconductor device
US20050247921A1 (en) * 2004-04-28 2005-11-10 Samsung Electronics Co., Ltd. Memory device using multi-layer with a graded resistance change
US20070200158A1 (en) * 2006-02-27 2007-08-30 Samsung Electronics Co., Ltd. Electrode structure having at least two oxide layers and non-volatile memory device having the same
CN101179095A (en) * 2007-11-13 2008-05-14 北京大学 Field-effect tranisistor realizing memory function and method of producing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279601A (en) * 1996-02-14 1996-10-22 Hitachi Ltd Manufacture of semiconductor device
US20050247921A1 (en) * 2004-04-28 2005-11-10 Samsung Electronics Co., Ltd. Memory device using multi-layer with a graded resistance change
US20070200158A1 (en) * 2006-02-27 2007-08-30 Samsung Electronics Co., Ltd. Electrode structure having at least two oxide layers and non-volatile memory device having the same
CN101179095A (en) * 2007-11-13 2008-05-14 北京大学 Field-effect tranisistor realizing memory function and method of producing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575991A (en) * 2014-09-04 2016-05-11 财团法人交大思源基金会 Memory structure and method of forming the same
CN105575991B (en) * 2014-09-04 2019-04-12 财团法人交大思源基金会 Memory structure and method of forming the same
CN105140391A (en) * 2015-07-02 2015-12-09 河北大学 Double-charge injection trap memory and preparation method thereof
CN105140391B (en) * 2015-07-02 2017-12-08 河北大学 A kind of Double-charge implantation capture memory and preparation method thereof
WO2017157074A1 (en) * 2016-03-18 2017-09-21 中国科学院微电子研究所 Selector for use in bipolar resistive memory and manufacturing method for selector
CN110828658A (en) * 2018-08-08 2020-02-21 北京北方华创微电子装备有限公司 Preparation method of resistive random access memory device and resistive random access memory device
CN111009609A (en) * 2019-12-24 2020-04-14 华中科技大学 Superlattice memristor functional layer material, memristor unit and preparation method of superlattice memristor functional layer material
WO2021128994A1 (en) * 2019-12-24 2021-07-01 华中科技大学 Superlattice memristor functional layer material, and memristor unit and preparation method therefor
CN114068808A (en) * 2021-11-03 2022-02-18 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same
CN116507195A (en) * 2023-06-21 2023-07-28 武汉大学 Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor
CN116507195B (en) * 2023-06-21 2023-10-17 武汉大学 Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor

Also Published As

Publication number Publication date
CN103311433B (en) 2015-07-22

Similar Documents

Publication Publication Date Title
CN103311433B (en) Manufacturing method of resistive random access memory
Carlos et al. Recent progress in solution‐based metal oxide resistive switching devices
JP5339716B2 (en) Resistive memory device and manufacturing method thereof
US8441060B2 (en) Nonvolatile memory element and nonvolatile memory device incorporating nonvolatile memory element
US9324944B2 (en) Selection device and nonvolatile memory cell including the same and method of fabricating the same
US20190148455A1 (en) Two-terminal switching element having bidirectional switching characteristic, resistive memory cross-point array including same, and method for manufacturing two-terminal switching element and cross-point resistive memory array
US8212232B2 (en) Resistance changing device and method for fabricating the same
JP6082383B2 (en) Resistance change type memory device
US20100065803A1 (en) Memory device and manufacturing method thereof
CN104810476A (en) Non-volatile resistive random access memory device and preparation method thereof
KR20130077504A (en) Resistance variable memory device and method for fabricating the same
CN102738386A (en) Resistive random access memory and manufacturing method thereof
US20210273158A1 (en) Memory device and manufacturing method therefor
CN103633243B (en) Preparation method of resistive memory
Hao et al. Atomic Layer Deposition Films for Resistive Random‐Access Memories
KR101176422B1 (en) Nonvolatile resistance random access memory device
KR20100084790A (en) Non-volatile memory device and method of manufacturing the same
JP5939482B2 (en) Resistance change type memory device and manufacturing method thereof
TWI500193B (en) Memory device and manufacturing method thereof
Wang et al. Sol–gel derived amorphous LaNbOx films for forming-free RRAM applications
KR101402085B1 (en) Manufacturing method of resistance switching random access memory using reduction reaction
KR101781002B1 (en) ReRAM and manufacture method thereof
Napolean et al. Temperature effects on an HfO 2-TiO 2-HfO 2 stack layer resistive random access memory cell for low power applications
KR101039191B1 (en) Nonvolatile memory device and method of manufacturing the same
TWI549326B (en) Resistive ram and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant