CN103310071B - A kind of VLSI circuit partitioning method based on multistage GRASP - Google Patents
A kind of VLSI circuit partitioning method based on multistage GRASP Download PDFInfo
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- CN103310071B CN103310071B CN201310259700.8A CN201310259700A CN103310071B CN 103310071 B CN103310071 B CN 103310071B CN 201310259700 A CN201310259700 A CN 201310259700A CN 103310071 B CN103310071 B CN 103310071B
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Abstract
The invention provides a kind of VLSI (very large scale integrated circuit) (VLSI) circuit partitioning method based on the random adaptive process of multistage greed (GRASP), belong to technical field of VLSI design automation.The method mainly can produce the advantage of better initial solution fast in conjunction with GRASP, improve the GradeNDivision method of current main flow.Drip irrigation device is as follows: (1) is in the alligatoring stage, the connection weight devised between a kind of bucket sort method opposite vertexes carries out quicksort, on this basis, by the thought structure initial matching of GRASP, and with short delivery for augmenting path (circle) local improvement matching result; (2) in the initial division stage, and the good initial division set of quality is constructed by the thought of GRASP; (3) at elaboration phase, constantly reduce to divide set size in conjunction with diversity mechanism.The method can provide high-quality division result, can adapt to the demand of the layout design robotization of current VLSI.
Description
Technical field
The present invention relates to a kind of VLSI (very large scale integrated circuit) (VLSI) circuit partitioning method based on the random adaptive process of multistage greed (GRASP), belong to technical field of VLSI design automation, particularly vlsi layout design automation technology.
Background technology
IC industry is the emerging strategic industries of national economy and social development, is to promote informationalized core and basis.In recent years, along with the develop rapidly of semiconductor material science and information industry, the integrated level of integrated circuit (IC) chip is more and more higher, and to VLSI design, particularly layout design automatic technology is had higher requirement.For effectively reducing the complicacy of vlsi layout design, need whole circuit to be divided into some electronic circuits.The result that circuit divides directly affects follow-up floor planning, layout, wiring process, thus affects circuit layout.In addition, high-quality circuit divides the interconnection time delay that can reduce chip chamber, thus improves the performance of system.Therefore, finding the focus that high-quality circuit partitioning method is numerous scholar's research, is also the important component part of VLSI electric design automation (EDA) instrument.
Usually, it is minimize cut line screen that circuit divides target, and requires that the scale of each electronic circuit will roughly balance.Circuit Partitioning Problem belongs to NP difficult problem, needs to seek effective heuristic.When circuit is divided, first to solve the representation of circuit.At present, be hypergraph H={V, E} to the most effective representation of circuit.Wherein, V={v
1, v
2..., v
nthe set of indication circuit element, E={e
1, e
2..., e
nrepresent gauze set.On this basis, typical circuit partitioning method has: based on the iterate improvement method of movement, as FM algorithm, CLIP/CDIP algorithm; GradeNDivision method, as hMetis.GradeNDivision method is formed primarily of three phases: the alligatoring stage, initial division stage, elaboration phase.Wherein, summit larger for some associations, mainly in order to reduce the scale of hypergraph, constantly being shunk, thus being produced the more and more less hypergraph of a series of scale by the alligatoring stage; When enough hour of the scale of hypergraph, enter the initial division stage; Successively upwards map again afterwards, and update division.
GRASP is a kind of widely used heuristic, mainly comprises construction phase and local search phase.Wherein, the initial solution that construction phase adopts the random adaptive mode of greed to produce, the Local Search stage improves the initial solution of structure.
Although hMetis dividing tool can provide the division of better quality, is widely used in eda tool.But, along with industry member improving constantly circuit performance requirement, urgently occur that one provides higher-quality division methods, to adapt to the demand of current vlsi layout design automation.
Summary of the invention
In view of this, the object of the invention is to design one and can obtain high-quality division result, and there is the circuit partitioning method of higher time efficiency.Its basic thought is the advantage that can produce better initial solution in conjunction with GRASP fast, improves, thus obtain a kind of circuit partitioning method of superior performance to the GradeNDivision method of current main flow.
Technical scheme of the present invention: the VLSI circuit partitioning method based on multistage GRASP of the present invention, is first expressed as hypergraph circuit.Then, the quality of summit coupling is improved in the alligatoring stage.Then, in the initial division stage, the good initial division set of structure quality, thus improve division quality further.At elaboration phase, constantly reduce to divide set size in conjunction with diversity mechanism, effectively ensure that time efficiency.Finally, division is optimized further.Specific as follows:
(1) circuit is expressed as hypergraph H
0={ V
0, E
0;
(2) current hypergraph H is calculated
iin the right connection weight in all summits;
(3) connection weight between bucket sort method opposite vertexes is adopted to carry out quicksort.On this basis, by the thought structure initial matching of GRASP;
(4) respectively with the matching result replacing augmentation circle local improvement step (3) that alternately augmenting path and length that length is 2,3 are 4;
(5) according to the result of coupling, start to construct next stage hypergraph H
i+1;
(6) step (2)-(5) are repeated, until the scale of hypergraph is enough little;
(7) use the thought of GRASP to H
icarry out initial division, obtain H
idivision set POP
i;
(8) adopt diversity mechanism, upgrade POP
i;
(9) to POP
imap, the H obtained
i-1initial division set POP
i-1;
(10) POP is optimized with FM
i-1;
(11) step (8)-(10) are repeated, until refine to former figure H
0;
(12) to H
0division carry out V-cycle improvement, obtain last division result.
Advantage of the present invention: through the test result analysis of 18 preferred circuit samples of IBM, in division quality, the division quality that method of the present invention obtains wants general higher than dividing tool hMetis best at present, can improve 5% at most; From time division efficiency, as long as cost hundreds of can realize hundreds thousand of circuit divisions in second on common PC.Can reach a conclusion, method of the present invention is that one can obtain high-quality division result, and has the circuit partitioning method of lower time complexity.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the VLSI circuit partitioning method based on multistage GRASP.
Fig. 2 to be length be 2,3 alternately augmenting path and length be 4 alternately augmentation circle sample.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.
The present embodiment provides a kind of VLSI circuit partitioning method based on multistage GRASP, it is characterized in that comprising the steps:
(1) circuit is expressed as hypergraph H
0={ V
0, E
0;
(2) current hypergraph H is calculated
iin the right connection weight in all summits;
(3) connection weight between bucket sort method opposite vertexes is adopted to carry out quicksort.On this basis, by the thought structure initial matching of GRASP;
(4) respectively with the matching result replacing augmentation circle local improvement step (3) that alternately augmenting path and length that length is 2,3 are 4;
(5) according to the result of coupling, start to construct next stage hypergraph H
i+1;
(6) step (2)-(5) are repeated, until the scale of hypergraph is enough little;
(7) use the thought of GRASP to H
icarry out initial division, obtain H
idivision set POP
i;
(8) adopt diversity mechanism, upgrade POP
i;
(9) to POP
imap, the H obtained
i-1initial division set POP
i-1;
(10) POP is optimized by FM method
i-1;
(11) step (8)-(10) are repeated, until refine to former figure H
0;
(12) to H
0division carry out V-cycle improvement, obtain last division result.
Refer to Fig. 1, Fig. 1 is based on the process flow diagram of the VLSI circuit partitioning method of multistage GRASP.The mathematical model of concrete the method is described below:
Circuit is expressed as hypergraph model H={V, E}, wherein, V={v
1, v
2..., v
nthe set of indication circuit element, E={e
1, e
2..., e
nrepresenting gauze set, super limit e ∈ E is the nonvoid subset of V, | e|>=2.The weight that w (v) is vertex v, expression be the area of circuit component represented by vertex v.Total weight that w (V) is vertex set V.Division is that V is divided into subset V
1, V
2, meet V
1∩ V
2=φ, V
1∪ V
2=V.Note divides P={V
1, V
2, super limit e ∈ E is divided P cutting, and and if only if meets e ∩ V
1≠ φ, e ∩ V
2≠ φ.
Demand fulfillment Area Balanced constraint condition during division.Given balance factor t, the weight lower bound of each subset is L=1/2 (1-t) w (V), upper bound U=1/2 (1+t) w (V).Equilibrium constraint is as follows:
L≤w(V
i)≤U,i＝1,2(1)
The target divided is minimum cut edge number.
104 parts in Fig. 1, hypergraph H
ithe connection weight account form of middle summit to (u, v) is as follows:
105 parts in Fig. 1, detailed process is as follows:
(1) B+1 bucket is constructed, each barrel of correspondence one single-track link table.By H
iall summits bucket is put into (u, v)
wherein c
maxand c
minbe respectively maximal value and the minimum value of connection weight, the value of B is min{ summit logarithm, 1000};
(2) initialization M=φ;
(3) selecting 5 does not have summit to be mated and the maximum summit pair of Connected degree;
(4) from 5 candidate vertices centering Stochastic choice one summits, (u, v) is mated;
(5)M＝M∪{(u,v)}；
(6) (2)-(5) are repeated, until there is not the summit pair that can mate.
106 parts in Fig. 1, detailed process is as follows:
Respectively local improvement is carried out to coupling M according to kind of the short delivery of four shown in Fig. 2 for augmenting path (circle) order.In figure, solid dot represents the summit of having mated, and hollow dots represents the summit of not mating.Below with the 2nd in Fig. 2 kind, namely length is the short delivery of 2 is the local improvement process that example illustrates to M for augmenting path: select arbitrarily a summit to (u, v) ∈ M, find out not by the summit u ' maximum with u Connected degree that mate and the vertex v maximum with v Connected degree ', if meet conn (u, u ')+conn (v, v ') > conn (u, v), so M=M ∪ { (u, u '), (v, v ') }-{ (u, v) }.According to said method, as long as O is (N
c) linear session can find a little do not hand over and length be 2 short-alternately augmenting path.Other three kinds of local improvement processes are similar with it, no longer describe in detail here.
107 parts in Fig. 1, detailed process is as follows:
If in M, v
1with v
2coupling, v
1with v
2be shrunk to a vertex v ∈ V
i+1, its weight w (v)=w (v
1)+w (v
2).Other are not by the summit of mating, and continue reservation and become H
i+1in summit.
109 parts in Fig. 1, H
iin scale enough little be whether be less than 200 for criterion with number of vertex.
110 parts in Fig. 1, detailed process is as follows:
(1) initialization POP
i=φ;
(2) initialization V
1=V
i, V
2=φ;
(3) from V
1in select
the summit that individual yield value (the cut edge value reduction caused is moved on summit) is maximum;
(4) Stochastic choice vertex v from the candidate vertices set of (3);
(5)V
1＝V
1-{v},V
2＝V
2+{v}；
(6) (3)-(5) are repeated, until form one effectively divide P={V
1, V
2;
(7)POP
i＝POP
i∪{P}；
(8) (2)-(7) i+1 time is repeated.
111 parts in Fig. 1, FM algorithm detailed process is as follows:
FM algorithm is made up of a series of iteration.Take turns in iteration one, always move the maximum summit of gain at every turn, just by this summit locking (namely not allowing to move again) after mobile.Until all summits all cannot be moved, one takes turns iteration terminates.Preferably divide the initial division as next round iteration in last round of iteration, the summit then starting to carry out a new round is moved.If take turns Loop partition quality not to be improved a certain, algorithm stops.
112 parts in Fig. 1, detailed process is as follows:
First select POP
iin || POP
i|/2| top-quality division, then choose one to divide apart from minimum division P with these from remaining
i'.Suppose P
1, P
2∈ POP
i, wherein
so P
1and P
2between distance d (P
1, P
2) be defined as the number of vertex not belonging to same subset in the two corresponding division, shown in (3):
Choose P
i' after, upgrade POP
i=POP
ip
i'.
114 parts in Fig. 1, detailed process is as follows:
To POP
iin each division P
imap according to following mode: suppose H
imiddle constriction point is v, and that corresponding is H
i-1in vertex v
1, v
2.At P
i-1in, v
1, v
2with v in identical part.
115 parts in Fig. 1 are identical with 111 parts.
118 parts in Fig. 1, detailed process is as follows:
One time V-cycle is to hypergraph H
0carry out once the process of limited alligatoring, initial division and refinement.Wherein, in coarsening process and Fig. 1,104-109 part is similar, no longer describes in detail here.Concrete difference is: the summit pair belonging to same subset is only considered in the selection right in (3) step 5 candidate vertices of 105 parts; Equally, when 106 part local improvement coupling, the summit of new coupling is to also only considering to belong to same subset.After the alligatoring stage terminates, by H
0division construct an initial division, then with FM refinement step by step.Above-mentioned V-cycle process repeats, and can not improve until divide.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1., based on a VLSI circuit partitioning method of multistage GRASP, it is characterized in that comprising the steps:
(1) circuit is expressed as hypergraph H
0={ V
0, E
0;
(2) current hypergraph H is calculated
iin the right connection weight in all summits;
(3) connection weight between bucket sort method opposite vertexes is adopted to carry out quicksort; On this basis, by the thought structure initial matching of GRASP;
(4) respectively with the matching result replacing augmentation circle local improvement step (3) that alternately augmenting path and length that length is 2,3 are 4;
(5) according to the result of coupling, start to construct next stage hypergraph H
i+1;
(6) step (2)-(5) are repeated, until the scale of hypergraph is enough little;
(7) use the thought of GRASP to H
icarry out initial division, obtain H
idivision set POP
i;
(8) adopt diversity mechanism, upgrade POP
i;
(9) to POP
imap, the H obtained
i-1initial division set POP
i-1;
(10) POP is optimized by FM method
i-1;
(11) step (8)-(10) are repeated, until refine to former figure H
0;
(12) to H
0division carry out V-cycle improvement, obtain last division result;
Wherein, in described step (6): H
iin scale enough little be whether be less than 200 for criterion with number of vertex.
2. the VLSI circuit partitioning method based on multistage GRASP according to claim 1, is characterized in that: the implementation of described step (1) is: circuit is expressed as hypergraph model H={V, E}, wherein, and V={v
1, v
2..., v
nthe set of indication circuit element, E={e
1, e
2..., e
nrepresenting gauze set, super limit e ∈ E is the nonvoid subset of V, | e|>=2; The weight that w (v) is vertex v, expression be the area of circuit component represented by vertex v; Total weight that w (V) is vertex set V; Division is that V is divided into subset V
1, V
2, meet V
1∩ V
2=φ, V
1∪ V
2=V; Note divides P={V
1, V
2, super limit e ∈ E is divided P cutting, and and if only if meets e ∩ V
1≠ φ, e ∪ V
2≠ φ;
Demand fulfillment Area Balanced constraint condition during division; Given balance factor t, the weight lower bound of each subset is L=1/2 (1-t) w (V), upper bound U=1/2 (1+t) w (V); Equilibrium constraint is as follows:
L≤w(V
i)≤U,i＝1,2(1)
The target divided is minimum cut edge number.
3. the VLSI circuit partitioning method based on multistage GRASP according to claim 2, is characterized in that: in described step (2), hypergraph H
ithe connection weight account form of middle summit to (u, v) is as follows:
4. the VLSI circuit partitioning method based on multistage GRASP according to claim 3, is characterized in that: the implementation of described step (3) comprises the following steps:
(31) B+1 bucket is constructed, each barrel of correspondence one single-track link table; By H
iall summits bucket is put into (u, v)
wherein c
maxand c
minbe respectively maximal value and the minimum value of connection weight, the value of B is min{ summit logarithm, 1000};
(32) initialization M=φ;
(33) selecting 5 does not have summit to be mated and the maximum summit pair of Connected degree;
(34) from 5 candidate vertices centering Stochastic choice one summits, (u, v) is mated;
(35)M＝M∪{(u,v)}；
(36) (32)-(35) are repeated, until there is not the summit pair that can mate.
5. the VLSI circuit partitioning method based on multistage GRASP according to claim 4, is characterized in that: the implementation of described step (7) comprises the following steps:
(71) initialization POP
i=φ;
(72) initialization V
1=V
i, V
2=φ;
(73) from V
1in select
the summit that individual yield value is maximum; Wherein said yield value represents that the cut edge value reduction caused is moved on summit;
(74) Stochastic choice vertex v from the candidate vertices set of step (73);
(75)V
1＝V
1-{v},V
2＝V
2+{v}；
(76) (73)-(75) are repeated, until form one effectively divide P={V
1, V
2;
(77)POP
i＝POP
i∪{P}；
(78) step (72)-(77) i+1 time is repeated.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101610A (en) * | 2007-07-13 | 2008-01-09 | 上海大学 | Large scale integration circuit division method based on multi-level division method |
| CN102682176A (en) * | 2012-05-18 | 2012-09-19 | 冷明 | Method for dividing large-scale integrated circuit based on cellular automaton and empowerment hypergraph |
| CN102693340A (en) * | 2012-05-19 | 2012-09-26 | 孙凌宇 | Large scale integrated circuit partitioning method on basis of multilevel partitioning method and weighted hypergraph |
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|---|---|---|---|---|
| US6532578B2 (en) * | 2001-05-16 | 2003-03-11 | International Business Machines Corporation | Method of configuring integrated circuits using greedy algorithm for partitioning of N points in P isothetic rectangles |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101610A (en) * | 2007-07-13 | 2008-01-09 | 上海大学 | Large scale integration circuit division method based on multi-level division method |
| CN102682176A (en) * | 2012-05-18 | 2012-09-19 | 冷明 | Method for dividing large-scale integrated circuit based on cellular automaton and empowerment hypergraph |
| CN102693340A (en) * | 2012-05-19 | 2012-09-26 | 孙凌宇 | Large scale integrated circuit partitioning method on basis of multilevel partitioning method and weighted hypergraph |
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