CN101101610A - Large scale integration circuit division method based on multi-level division method - Google Patents
Large scale integration circuit division method based on multi-level division method Download PDFInfo
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Abstract
Modifying partitioning approach in multiple levels, the disclosed method implements conversion from circuit wire mesh to undirected graphs, which are saved as undirected graph files with weights. Then, starting up partitioning program in multiple levels for undirected graph, the method partitions undirected weighted graph generated. Possessing better practicability, the method raises efficiency and performance for partitioning circuit effectively and markedly.
Description
Technical field:
The present invention relates to a kind of large scale integrated circuit division methods that large scale integrated circuit is used that designs based on multilevel partitioning.
Background technology:
Circuit is divided in to use in the hardware description language design large scale integrated circuit and occupies an important position.Fast development along with integrated technology, integrated hundreds of thousands door even millions of gate circuit become a reality on a chip, therefore in large scale integrated circuit design, use circuit to divide, lowered effectively integrated circuit is simulated or comprehensive requirements such as complicacy.It also is an important ring of stratification design philosophy that circuit is divided, circuit can divided on the different stage: carry out system-level division a system divides to one group of printed circuit board (PCB), carry out the division of plate level the circuit on the printed circuit board (PCB) is divided into a core assembly sheet, carry out the chip-scale division circuit in the chip is divided into littler circuit.Circuit is divided in addition, and an important reasons is exactly to satisfy the requirement of encapsulation property, the number of door and the relation between the input and output pin number are subjected to the Rent rule constrain in the circuit, the number of the number of output pin and gate circuit all can not unrestrictedly increase on each chip, in addition to the requirement of large scale integrated circuit encapsulation property, so must divide to large scale integrated circuit.Working out a good circuit division methods is to improve the necessary condition that large scale integrated circuit is divided system performance.
See also shown in Figure 1, circuit division methods in the circuit division system of prior art, the first step is described the circuit 101 be divided with hardware description language, obtains circuit source code 102; In second step, the source code of lexical analysis circuit obtains corresponding word symbol 103; In the 3rd step, enterprising lang method is analyzed on the lexical analysis basis, obtains corresponding grammer phrase 104; In the 4th step, enterprising lang justice is analyzed on the grammatical analysis basis, obtains corresponding type information 105; The 5th step generated intermediate code on the semantic analysis basis, the circuit gauze 106 that structure is corresponding; In the 6th step, the gauze according to intermediate code generates calls 109 pairs of circuit of partition program and divides; In the 7th step,, obtain revising back gauze 107 according to the gauze of dividing the results modification correspondence; The 8th step, carry out circuit output to revising the back gauze, obtain dividing the back circuit and describe source code 108.
The partitioning that some kinds of logical circuits are arranged from the circuit division system of prior art, these partitionings are from interconnection line number minimum, and the different aspects such as the even distribution of logical unit number of circuit subclass realize after dividing, wherein:
A kind of partitioning based on migration at first, produces the initial division at random of circuit, and same circuit logic unit can not belong to two circuit subclass simultaneously.In the migration optimizing phase, this partitioning is respectively chosen a circuit logic unit and is carried out to exchange in two circuit subclass, these two circuit logic unit belong to two different circuit subclass and income maximum respectively, divide quality thereby all utilize exchange process to improve circuit to greatest extent at every turn.In this process, the partitioning record cuts off and reaches minimum value circuit division result constantly, and in case exchanged two circuit logic unit selecting, in the optimization of whole transition process remainder improves, make them no longer selected these two circuit logic unit lockings, repeat said process up to all possible circuit logic unit all after migration, roll back to the moment that the accumulated earnings maximum promptly cuts off minimum value then.The circuit that this program obtains is divided unstable result, and discreteness is very big, has therefore limited the scale that this partitioning can be dealt with problems.
The nested partitioning of another kind of level, at first, select a circuit logic unit, this circuit logic unit is put on 0, then those are put on 1 with the circuit logic unit that this circuit logic unit links to each other, also not putting on number for those afterwards, still and put on the adjacent circuit logic unit, circuit logic unit of number, is to add 1 on the circuit logic unit number that links to each other with its label; Number is put in circuit logic unit up to half, and label procedure just finishes.Those circuit logic unit sets of having put on number are made as a circuit subclass, and other circuit logic unit are another circuit subclass.Only when the approaching periphery of the initial circuit logical block of choosing, it is better relatively that the circuit that obtains is divided the result for this partitioning, and therefore the circuit that obtains is divided also instability of result.
Also have a kind of multilevel partitioning, at first, adopt to mate at random some circuit logic unit is combined, obtain the alligatoring circuit diagram of next flat seam, repeat this process till the alligatoring circuit diagram is enough little, promptly obtain a minimum circuit figure.Then, adopt partitioning that minimum circuit figure is carried out obtaining initial two divisions to dividing.Afterwards, returning initial circuit figure from minimum circuit figure projection, in the refinement circuit of each flat seam is divided, selecting the circuit logic unit of financial value maximum to move optimization according to greedy principle, the circuit that gets is to the end divided the result.The above-mentioned relatively two kinds of methods of this partitioning are more suitable for dividing at VLSI (very large scale integrated circuit), but are optimized owing to adopting randomized policy to mate with greedy principle, and the ability of therefore fleeing from local optimum is limited.
Summary of the invention:
The objective of the invention is to deficiency, a kind of improved large scale integrated circuit division methods based on multilevel partitioning is provided, improve efficient and performance that large scale integrated circuit is divided at the prior art existence.For achieving the above object, design of the present invention is as follows:
Realize of the conversion of circuit gauze, and save as the non-directed graph file of cum rights value, start the multilevel partition program of non-directed graph then, the tax power non-directed graph that generates is divided to non-directed graph.
In the alligatoring stage of multilevel partitioning, find the solution ordering by the nuclear value of the node attribute being composed all nodes in the power non-directed graph, non-strict descending based on node nuclear value, be in the not node of matching status according to this order visit, according to certain rule it is mated, thereby the node that connectivity is good combines.
In the optimizing phase of multilevel partitioning, adopt the immune clone optimizer to improve the local search approach of greedy principle, division in each flat seam figure projection is optimized, by suitable clone operations, clonal vaviation operation, the operation of immunoprophylaxis vaccine, Immune Clone Selection operation, method after feasible the improvement is when utilizing heuristic information search locally optimal solution, freely the solution space of potentialization is searched for greatlyyer, increase ability of searching optimum.
According to above-mentioned inventive concept, technical scheme of the present invention is achieved in that a kind of large scale integrated circuit division methods based on multilevel partitioning, it is characterized in that concrete steps are as follows,
The running program of above-mentioned step 6 is:
6.1 construct the gauze that the circuit source code is described the circuit correspondence based on intermediate code, generate the complete circuit gauze; A complete circuit gauze is regarded a root module as, it is made of by signal is interconnected the submodule example and the circuit logic unit of stratification, and each submodule inside is connected and composed by signal by the example of port, circuit logic unit, nested submodule;
6.2 travel through complete circuit gauze, and to the name of the basic circuit logical block in circuit identification number; Establish the signal connected mode between each logical block, be implemented to the conversion of non-directed graph, the basic circuit logical block node V among this figure
iExpression, signal limit E among this figure
jExpression; Node V
iWeights represent the size of basic circuit logical block, limit E
jWeights represent the weights of the conversion of signal link between the basic circuit logical block;
6.3 the non-directed graph that is converted to is saved as the non-directed graph file of cum rights value.
The running program of above-mentioned step 7 is:
7.1 read the non-directed graph file of cum rights value, adopt the compression storage format that figure is stored;
7.2 enter into the alligatoring stage of multilevel partitioning, adopt matcher that some node is combined, obtain the roughening picture of next flat seam, repeat this process till roughening picture is enough little, promptly obtain a minimal graph;
7.3 enter into the initial division stage of multilevel partitioning, the initialization antibody population, wherein each antibody adopts partition program to obtain initial two divisions in the antibody population, and adopts the operation of immunoprophylaxis vaccine to carry out initial two optimizations of dividing;
7.4 enter into the optimizing phase of multilevel partitioning, return initial graph from the minimal graph projection, in the refinement figure of each flat seam, set clone's scale parameter, adopt the immune clone optimizer that division is optimized;
7.5 the division result that will finally obtain is stored in non-directed graph and divides in the file.
In the above-mentioned step 7.2, described matcher is:
7.2.1 all nodes are in not matching status among the mark figure;
7.2.2 carry out the nuclear value of all nodes among the figure finds the solution based on the node attribute;
7.2.3 carry out non-strict descending sort according to the nuclear value of node, and be in the not node v of matching status according to this order visit; If node v also has adjacent node not mate, choose so and be in the adjacent node u that do not have matching status and the limit weights maximum and node v coupling, and to mark these two nodes be matching status; If node v all of its neighbor matched nodes is in matching status, node v still is in not matching status so, directly copies in coarsening process in the roughening picture of next flat seam;
7.2.4 the repetition previous step finishes until visit.
In the above-mentioned step 7.4, described immune clone optimizer is:
Return refinement figure 7.4.1 will go up division projection after the flat seam roughening picture antibody population optimization, as antibody population initial division when anterior layer when anterior layer;
7.4.2 the optimum population optimal dividing BEST that is divided into is set in the antibody population initial division, and the cycle counter COUNTER of immune clone program is changed to zero;
7.4.3 the affinity degree of calculating antibody population, according to the antibody cloning scale parameter of setting, each antibody carries out clone operations, clonal vaviation operation, the operation of immunoprophylaxis vaccine, Immune Clone Selection operation in the antagonist population;
7.4.4 if optimum division is better than population optimal dividing BEST in the new antibodies population, new population optimal dividing BEST more then;
7.4.5 cycle counter COUNTER adds one;
7.4.6 repeat 7.4.3,7.4.4,7.4.5 step, arrive the given upper limit until cycle counter COUNTER.
The running program of above-mentioned step 8 is:
8.1 read the corresponding division result that non-directed graph is divided file storage;
8.2 by revising the gauze of circuit correspondence, move the module of appointment with dividing as a result the basic circuit logical block of correspondence.
The present invention has following conspicuous outstanding substantive distinguishing features and remarkable advantage compared with prior art:
1, improved the efficient that circuit is divided
The present invention is based on the large scale integrated circuit division methods of multilevel partitioning, owing to realize of the conversion of circuit gauze to cum rights value non-directed graph file, start the multilevel partition program of non-directed graph then, the tax power non-directed graph that generates is divided, thereby avoided partitioning directly to divide on the net in circuitry lines, and can carry out the modification of circuit gauze again by behind the more excellent division result of the parameter acquiring that partitioning is set, thereby improve the efficient that circuit is divided effectively.
2, improved the performance that circuit is divided
The present invention is based on the large scale integrated circuit division methods of multilevel partitioning, because in the alligatoring stage of multilevel partitioning, mate according to certain rule by the node attribute, thereby the node that connectivity is good combines, maximization reduces the bar number and the limit weights sum on limit, thereby helping the initial division stage obtains a good initial division, the projection optimization in the optimizing phase to initial division.The present invention is based on the large scale integrated circuit division methods of multilevel partitioning, in the optimizing phase of multilevel partitioning, adopt the immune clone optimizer to improve the local search approach of greedy principle, division in each flat seam figure projection is optimized, find the circuit more excellent to divide the result effectively, finally improved the performance that circuit is divided significantly than prior art.
Description of drawings:
By of the description of following example to the large scale integrated circuit division methods that the present invention is based on multilevel partitioning, can further understand purpose of the present invention, specific structural features and advantage in conjunction with its accompanying drawing.
Fig. 1 is the flow chart of circuit division methods in the circuit division system of prior art.
Fig. 2 is the flow chart that the present invention is based on the large scale integrated circuit division methods of multilevel partitioning.
Fig. 3 is of the present invention to composing the flow chart of the compression storage format that power non-directed graph file stores.
Fig. 4 is the process flow diagram of the matcher of alligatoring stage enforcement of the present invention.
Fig. 5 is a process flow diagram of the optimizing phase of the present invention implementing the immune clone optimizer.
Fig. 6 is the process flow diagram of enforcement immunoprophylaxis vaccine operation of the present invention.
Fig. 7 experimental result table that to be the present invention compare based on the non-directed graph partition program MeTiS of multilevel partitioning with prior art.
Embodiment:
In order more to be expressly understood the technology contents of the large scale integrated circuit division methods that the present invention is based on multilevel partitioning, especially exemplified by following example in detail.
See also shown in Figure 2ly, describe the circuit 201 be divided, obtain circuit source code 202 with hardware description language; The source code of lexical analysis circuit obtains corresponding word symbol 203; Enterprising lang method is analyzed on the lexical analysis basis, obtains corresponding grammer phrase 204; Enterprising lang justice is analyzed on the grammatical analysis basis, obtains corresponding type information 205; On the semantic analysis basis, the bosom code 206 that structure is corresponding; Gauze 207 based on the circuit correspondence of bosom code structure textual description after the conversion of non-directed graph, saves as the non-directed graph file 210 of cum rights value through the circuit gauze; Start the multilevel partition program 216 of non-directed graph, read the non-directed graph file of cum rights value, obtain adopting Figure 21 2 of compression storage format storage; Enter into the alligatoring stage of multilevel partitioning, call matcher 217, some figure node is combined, obtain the roughening picture 213 of each flat seam; Enter into the initial division stage of multilevel partitioning, call 218 pairs of minimal graphs of partition program and carry out, obtain minimal graph initial two and divide 214 dividing; Enter into the optimizing phase of multilevel partitioning, return initial graph from the minimal graph projection, in the refinement figure of each flat seam, call 219 pairs of divisions of optimizer and be optimized, the optimization that obtains each flat seam refinement figure divides 215; The initial graph that finally obtains is divided the result be stored as non-directed graph division file 211; Detecting after the non-directed graph partition program finishes division, dividing the file from non-directed graph and read corresponding division result, revising the gauze of circuit correspondence, obtaining dividing gauze 208 after the modification of correspondence as a result according to division information; Travel through amended gauze, the circuit that obtains is divided the result be stored as circuit description document 209 with hardware description language.
For the non-directed graph file of the cum rights value of multilevel partitioning, the compression storage format of present embodiment as shown in Figure 3.Storage organization uses the information of xadj array 303 storage nodes, uses the information of adjncy array 302 storage adjacent nodes.Suppose that group address starts from scratch, node numbering is started from scratch, and then the adjacent node list storage of i node is in array adjncy, and the position is from array adjncy[xadj[i]] to adjncy[xadj[i+1]-1].Legend 301 comprises 7 nodes and 12 limits altogether, the adjacent node tabulation of adjncy array 302 each node of storage, so size is 24.Xadj array 303 is specified the initial sum final position of the corresponding adjacent node tabulation of each node, and the reference position of i node is the final position of i-1 node, so size is 8.When figure is the non-directed graph of cum rights value, compress the weights information that storage organization uses vwgt array 305 storage nodes, size is the number of node; Use the information of adjwgt array 304 storage limit weights, size is the twice of limit number, and is used with the array adjncy that stores adjacent node information.The weights of i node leave vwgt[i in], and adjacent node adjncy[j] between the weights information on limit leave adjwgt[j in].
For the alligatoring stage of multilevel partitioning, the matcher idiographic flow of present embodiment as shown in Figure 4, step is as follows:
A01: all nodes are in not matching status among the mark figure;
A02: the nuclear value of carrying out all nodes among the figure based on the node attribute is found the solution, and the attribute of node can adopt in-degree, out-degree, degree, the node limit weights sum of node, the maximal value in the weights of node limit etc.;
A03: carry out non-strict descending sort according to the nuclear value of node;
A04: being in not according to this order visit, whether the node of matching status finishes; If visit does not finish, promptly exist node v not accessed, then change steps A 05; Otherwise visit finishes, and then matcher finishes;
A05: whether node v all of its neighbor node is in matching status; If exist adjacent node not mated, change steps A 06; Otherwise node v all of its neighbor node all is in matching status, changes steps A 11;
A06: choose and be in that not have adjacent node matching status and the limit weights maximum be candidate's node;
A07: if exist a plurality of candidate's nodes, then change steps A 08, otherwise have only single candidate's adjacent node, change steps A 10;
A08: in a plurality of candidate's nodes, select bigger that adjacent node u of nuclear value;
A09: node v and adjacent node u coupling also merge, and the node weights after the merging are node v and the addition of adjacent node u weights, and the limit that merges postjunction is the merging on node v and adjacent node u limit, changes steps A 04;
A10: select single candidate's adjacent node u, change steps A 09;
A11: node v still is in not matching status, directly copies in coarsening process in the roughening picture, changes steps A 04.
For the optimizing phase of multilevel partitioning, the immune clone optimizer idiographic flow of present embodiment as shown in Figure 5, step is as follows:
B01: will go up division projection after the flat seam roughening picture antibody population optimization and return refinement figure, as antibody population initial division when anterior layer when anterior layer;
B02: the optimum population optimal dividing BEST that is divided into is set in the antibody population initial division;
B03: the cycle counter COUNTER of immune clone program is changed to zero;
B04: if cycle counter COUNTER arrives the given upper limit, then optimizer finishes, otherwise changes step B05;
B05: the affinity degree of calculating antibody population;
B06: according to the antibody cloning scale parameter of setting, each antibody carries out clone operations in the antagonist population;
B07: each antibody carries out the clonal vaviation operation in the antibody population;
B08: each antibody carries out the operation of immunoprophylaxis vaccine in the antibody population;
B09: antibody population is carried out the Immune Clone Selection operation according to the optimal dividing principle;
B10: if optimum division is better than population optimal dividing BEST in the new antibodies population, then change step B11, otherwise change step B12;
B15: more new population optimal dividing BEST is division optimum in the new antibodies population;
B16: cycle counter COUNTER adds one, changes step B06;
A kind of computing formula that can be for reference when step B05 calculates similarity between two antibody is as follows:
D in the following formula
A1A2The expression antibody A
1And A
2Between similarity, V represents the node set of non-directed graph, P
A1And P
A2Represent antibody A respectively
1And A
2The division of storage;
When each individuality carries out k for clone operations in the step B06 antagonist population, antibody A
iClone's scale q
i(k) a kind of computing formula that can be for reference is as follows:
Q in the following formula
i(k) expression k is for antibody A
iClone's scale, n
cThe relevant setting value of expression clone's scale, f (A
i(k)) be expressed as A
iAntibody antigen affinity degree, available antibodies A
iThe value of cuing off that storage is divided is calculated;
Θ
iBe expressed as antibody A
iWith the affinity of other antibody, Int (x) expression is greater than the smallest positive integral of x.
For the initial division stage and the optimizing phase of multilevel partitioning, the antibody immunoprophylaxis vaccine operation of present embodiment, by the financial value that to analyze based on current divided characteristic information be boundary node, make and vaccine inoculation according to greedy principle, make the new antibodies quality after the operation of immunoprophylaxis vaccine be improved, a kind of implementation method idiographic flow that can be for reference as shown in Figure 6, step is as follows:
C01: with the division of the current preservation of antibody as initial division P;
C02: antibody optimal dividing GOOD is set is changed to initial division P and cycle counter I is changed to zero;
C03: the inline degree and the degree of outreaching that calculate all nodes based on given initial division P;
C04: the migration financial value that calculates all boundary nodes;
C05: the financial value of all boundary nodes is inserted into respectively in the hash data structure of two node subclass;
C06: if cycle counter I arrives the given upper limit, EOP (end of program) then, otherwise change step C07;
C07: enter transition process, migratory direction arrives a light side for the heavy side of node subclass sum in dividing;
C08: from the hash data structure of current migratory direction starting point place one side, selecting the node of financial value maximum according to greedy principle is by the migration node;
C09: with node v migration and new the cuing off of dividing of calculating;
C10: the inline degree of adjacent node and the degree of outreaching that recomputate node v;
C12: the financial value that in the hash structure, upgrades adjacent node; If adjacent node node u is inserted into financial value in the node subclass hash structure at node u place so because the migration of node v becomes boundary node; If node u deletes financial value so because the migration of node v becomes non-boundary node from the node subclass hash structure at node u place; If be always boundary node before and after the node u migration, then only need to upgrade the financial value that is in the hash structure;
C14: be better than antibody optimal dividing GOOD if current division cuts off, then change step C15, otherwise change step C16;
C15: more new antibodies optimal dividing GOOD is current division;
C16: cycle counter I adds one, changes step C06;
In the present embodiment, adopt ANSIC to realize that operating system is WIN2000, operate on the Althon2200 chip of AMD of 1800MHZ based on the large scale integrated circuit division methods of multilevel partitioning, in save as 512M.The used test benchmark circuit of experimental program is 18 groups of circuit test benchmark ISPD98 that professor Alpert of IBM Corporation Austin research laboratory in 1998 provides.ISPD98 is based on a series of internal electron products that the Austin of IBM Corporation, Burlington, Rochester design department provide through being converted to, and comprises bus arbiter, bus electric bridge chip, internal memory and peripheral element expansion bus interface, communications adapter, Memory Controller Hub, processor and graphics adapter etc.Estimating existing correlation technique of the present invention is the famous non-directed graph partition program MeTiS based on multilevel partitioning, by the Karypis of Minnesota university professor is provided.Repeatability and the fairness of experimental program pin in order to guarantee experimental result, every group of circuit test reference map 20 comparison example checkings have been carried out, and fixedly select random number seed and immune clone optimizer parameter for use, wherein population scale is 8, the clonal vaviation coefficient is 0.3, and clone's scale parameter is 24 to be that each antibody is on average cloned 3 times.Because calculated amount such as antibody vaccine inoculation operation collection characteristic information are bigger, therefore divide in order to obtain best fit approximation within reasonable time, establishing iterations is 15.For experimental result, the evaluation index that we adopt is that the division that obtains in 20 case verifications cuts off minimum value (MinCut) and division cuts off mean value (AveCut)." node " in the form of Fig. 7 is the number of basic circuit logical block in this test benchmark circuit, and add up for the signal weights on " limit ".Experimental result has been showed the good performance of large scale integrated circuit division methods that the present invention is based on multilevel partitioning, compares MeTiS and cuts off minimum value in division and obtained 35.0% improvement, cuts off mean value in division and has obtained 55.1% improvement.
Claims (6)
1. large scale integrated circuit division methods based on multilevel partitioning is characterized in that concrete steps are as follows:
Step 1 is described this circuit with hardware description language, generates the source code of this circuit;
Step 2, the source code of this circuit is from left to right read in lexical analysis one by one, the character stream that constitutes source code is scanned and decomposes, thereby identify word one by one;
Step 3, grammatical analysis is resolved into all kinds of grammer phrases with word sequence on basis of lexical analysis, according to the syntax rule of hardware description language, determine whether whole character stream constitutes correct program on the grammer;
Step 4, semantic analysis, the audit source code has or not semantic error on the basis of grammatical analysis, for the intermediate code generation phase is collected type information;
Step 5, intermediate code generates, and on the basis of grammatical analysis and semantic analysis, source code is generated intermediate code, represents with the bosom form;
Step 6, the non-directed graph file of cum rights value generates, and the gauze based on the circuit correspondence of intermediate code structure textual description after the conversion of non-directed graph, saves as the non-directed graph file of cum rights value through the circuit gauze;
Step 7, non-directed graph is divided, and starts the multilevel partition program of non-directed graph, reads the non-directed graph file of cum rights value, and the weighted graph that generates is divided, and the division result who finally obtains is stored in non-directed graph divides in the file;
Step 8 is revised gauze, is detecting after the non-directed graph partition program finishes division, divides the file from non-directed graph and reads corresponding division result, revises the gauze of circuit correspondence according to division information;
Step 9, circuit output travels through amended gauze, the circuit that obtains is divided the result be stored in the circuit description document with hardware description language.
2. by the described large scale integrated circuit division methods of claim 1, it is characterized in that, be in the running program of described step 6 based on multilevel partitioning:
6.1 construct the gauze that the circuit source code is described the circuit correspondence based on intermediate code, generate the complete circuit gauze; A complete circuit gauze is regarded a root module as, it is made of by signal is interconnected the submodule example and the circuit logic unit of stratification, and each submodule inside is connected and composed by signal by the example of port, circuit logic unit, nested submodule;
6.2 travel through complete circuit gauze, and to the name of the basic circuit logical block in circuit identification number; Establish the signal connected mode between each logical block, be implemented to the conversion of non-directed graph, the node V of the logical block among this figure
iExpression, signal limit E among this figure
jExpression; Node V
iWeights represent the size of logical block, limit E
jWeights represent the weights of the conversion of signal link between the logical block;
6.3 the non-directed graph that is converted to is saved as the non-directed graph file of cum rights value.
3. by the described large scale integrated circuit division methods of claim 1, it is characterized in that, be in the running program of described step 7 based on multilevel partitioning:
7.1 read the non-directed graph file of cum rights value, adopt the compression storage format that figure is stored;
7.2 enter into the alligatoring stage of multilevel partitioning, adopt matcher that some node is combined, obtain the roughening picture of next flat seam, repeat this process till roughening picture is enough little, promptly obtain a minimal graph;
7.3 enter into the initial division stage of multilevel partitioning, the initialization antibody population, wherein each antibody adopts partition program to obtain initial two divisions in the antibody population, and adopts the operation of immunoprophylaxis vaccine to carry out initial two optimizations of dividing;
7.4 enter into the optimizing phase of multilevel partitioning, return initial graph from the minimal graph projection, in the refinement figure of each flat seam, set clone's scale parameter, adopt the immune clone optimizer that division is optimized;
7.5 the division result that will finally obtain is stored in non-directed graph and divides in the file.
4. by the described large scale integrated circuit division methods of claim 1, it is characterized in that, be in the running program of described step 8 based on multilevel partitioning:
8.1 read the corresponding division result that non-directed graph is divided file storage;
8.2 by revising the gauze of circuit correspondence, move the module of appointment with dividing as a result the basic circuit logical block of correspondence.
5. by the described large scale integrated circuit division methods of claim 3, it is characterized in that, be at the matcher of described step 7.2 based on multilevel partitioning:
7.2.1 all nodes are in not matching status among the mark figure;
7.2.2 carry out the nuclear value of all nodes among the figure finds the solution based on the node attribute;
7.2.3 carry out non-strict descending sort according to the nuclear value of node, and be in the not node v of matching status according to this order visit; If node v also has adjacent node not mate, choose so and be in the adjacent node u that do not have matching status and the limit weights maximum and node v coupling, and to mark these two nodes be matching status; If node v all of its neighbor matched nodes is in matching status, node v still is in not matching status so, directly copies in coarsening process in the roughening picture of next flat seam;
7.2.4 the repetition previous step finishes until visit.
6. by the described large scale integrated circuit division methods of claim 3, it is characterized in that, be at the immune clone optimizer of described step 7.4 based on multilevel partitioning:
Return refinement figure 7.4.1 will go up division projection after the flat seam roughening picture antibody population optimization, as antibody population initial division when anterior layer when anterior layer;
7.4.2 the optimum population optimal dividing BEST that is divided into is set in the antibody population initial division, and the cycle counter COUNTER of immune clone program is changed to zero;
7.4.3 the affinity degree of calculating antibody population, according to the antibody cloning scale parameter of setting, each antibody carries out clone operations, clonal vaviation operation, the operation of immunoprophylaxis vaccine, Immune Clone Selection operation in the antagonist population;
7.4.4 if optimum division is better than population optimal dividing BEST in the new antibodies population, new population optimal dividing BEST more then;
7.4.5 cycle counter COUNTER adds one;
7.4.6 repeat 7.4.3,7.4.4,7.4.5 step, arrive the given upper limit until cycle counter COUNTER.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102663216A (en) * | 2012-05-16 | 2012-09-12 | 孙凌宇 | Core value calculating method of large-scale integrated circuit based on node attribute function |
| CN102682176A (en) * | 2012-05-18 | 2012-09-19 | 冷明 | Method for dividing large-scale integrated circuit based on cellular automaton and empowerment hypergraph |
| CN103310071A (en) * | 2013-06-26 | 2013-09-18 | 福州大学 | Circuit dividing method for VLSI based on GRASP |
| CN103714385A (en) * | 2013-12-30 | 2014-04-09 | 北京航天测控技术有限公司 | Analogue circuit fault diagnosis method based on improved type clone selection algorithm |
| CN103870342A (en) * | 2014-04-06 | 2014-06-18 | 冷明 | Task core value calculating method on the basis of node attribute function in cloud computing environment |
| CN103885839B (en) * | 2014-04-06 | 2017-02-22 | 孙凌宇 | Cloud computing task scheduling method based on multilevel division method and empowerment directed hypergraphs |
| CN110853327A (en) * | 2019-11-02 | 2020-02-28 | 杭州雅格纳科技有限公司 | Ship cabin equipment data field debugging and collecting method and device based on single chip microcomputer |
| CN112784510A (en) * | 2021-03-10 | 2021-05-11 | 国微集团(深圳)有限公司 | Conditional cycle circuit segmentation method based on balanced weight and minimum edge segmentation |
-
2007
- 2007-07-13 CN CNB2007100437653A patent/CN100492377C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102663216B (en) * | 2012-05-16 | 2013-10-16 | 孙凌宇 | Core value calculating method of large-scale integrated circuit based on node attribute function |
| CN102663216A (en) * | 2012-05-16 | 2012-09-12 | 孙凌宇 | Core value calculating method of large-scale integrated circuit based on node attribute function |
| CN102682176A (en) * | 2012-05-18 | 2012-09-19 | 冷明 | Method for dividing large-scale integrated circuit based on cellular automaton and empowerment hypergraph |
| CN103310071B (en) * | 2013-06-26 | 2016-01-06 | 福州大学 | A kind of VLSI circuit partitioning method based on multistage GRASP |
| CN103310071A (en) * | 2013-06-26 | 2013-09-18 | 福州大学 | Circuit dividing method for VLSI based on GRASP |
| CN103714385A (en) * | 2013-12-30 | 2014-04-09 | 北京航天测控技术有限公司 | Analogue circuit fault diagnosis method based on improved type clone selection algorithm |
| CN103714385B (en) * | 2013-12-30 | 2017-02-01 | 北京航天测控技术有限公司 | Analogue circuit fault diagnosis method based on improved type clone selection algorithm |
| CN103870342A (en) * | 2014-04-06 | 2014-06-18 | 冷明 | Task core value calculating method on the basis of node attribute function in cloud computing environment |
| CN103870342B (en) * | 2014-04-06 | 2016-12-07 | 冷明 | Task core value calculating method based on node attribute function in cloud computing environment |
| CN103885839B (en) * | 2014-04-06 | 2017-02-22 | 孙凌宇 | Cloud computing task scheduling method based on multilevel division method and empowerment directed hypergraphs |
| CN110853327A (en) * | 2019-11-02 | 2020-02-28 | 杭州雅格纳科技有限公司 | Ship cabin equipment data field debugging and collecting method and device based on single chip microcomputer |
| CN110853327B (en) * | 2019-11-02 | 2021-04-02 | 杭州雅格纳科技有限公司 | Ship cabin equipment data field debugging and collecting method and device based on single chip microcomputer |
| CN112784510A (en) * | 2021-03-10 | 2021-05-11 | 国微集团(深圳)有限公司 | Conditional cycle circuit segmentation method based on balanced weight and minimum edge segmentation |
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