CN103296205A - Low power consumption resistive random access memory and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 239000010410 layer Substances 0.000 claims abstract description 37
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 33
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 33
- 239000010408 film Substances 0.000 claims abstract description 28
- XHCLAFWTIXFWPH-UHFFFAOYSA-N [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] Chemical class [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] XHCLAFWTIXFWPH-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910001935 vanadium oxide Inorganic materials 0.000 claims abstract description 21
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 32
- 238000004544 sputter deposition Methods 0.000 claims description 20
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- 239000013077 target material Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 150000002736 metal compounds Chemical class 0.000 claims description 4
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000001659 ion-beam spectroscopy Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
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- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000002356 single layer Substances 0.000 abstract description 2
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
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Abstract
一种低功耗阻变存储器，由下电极、阻变层和上电极组成并构成叠层结构，其中阻变层为氧化钒薄膜和二氧化硅薄膜叠层结构，各层的厚度分别为：下电极50-200nm、氧化钒薄膜5-100nm、二氧化硅薄膜1-50nm、上电极50-200nm；其制备方法是分别通过磁控溅射、离子束溅射或电子束蒸发方法依次制备各层薄膜。本发明的优点是：该阻变存储器通过在电极和氧化钒薄膜间插入一层二氧化硅，可有效降低了阻变存储器件的reset电流，降低器件的功耗，相对于单层的氧化钒薄膜的阻变器件，功耗能可降低一个数量级。
A low-power resistive variable memory, which is composed of a lower electrode, a resistive layer and an upper electrode and forms a laminated structure, wherein the resistive layer is a laminated structure of a vanadium oxide film and a silicon dioxide film, and the thicknesses of each layer are: The lower electrode is 50-200nm, the vanadium oxide film is 5-100nm, the silicon dioxide film is 1-50nm, and the upper electrode is 50-200nm; the preparation method is to sequentially prepare each layer film. The advantages of the present invention are: the resistive memory can effectively reduce the reset current of the resistive memory device by inserting a layer of silicon dioxide between the electrode and the vanadium oxide film, and reduce the power consumption of the device. Compared with a single layer of vanadium oxide Thin-film resistive switching devices can reduce power consumption by an order of magnitude.
Description
技术领域 technical field
本发明属于微电子技术领域，特别是一种低功耗阻变存储器及其制备方法。 The invention belongs to the technical field of microelectronics, in particular to a low-power resistive variable memory and a preparation method thereof.
背景技术 Background technique
近年来计算机技术、互联网技术飞速发展，非挥发性存储器件在半导体行业中扮演越来越重要的角色。而目前市场上非挥发性存储器仍以闪存（Flash）为主流，但随着半导体技术节点的不断向前推进，在22nm以下的特征尺寸，基于传统浮栅结构的Flash技术正遭受到严重的技术瓶颈。阻变存储器（RRAM）由于其阻变特性发生在几个纳米的区域，所以阻变存储器可以高密度集成；高密度集成的基本条件是器件必须满足低功耗的要求，才能解决器件高密度局部散热的问题。 In recent years, with the rapid development of computer technology and Internet technology, non-volatile memory devices play an increasingly important role in the semiconductor industry. At present, flash memory (Flash) is still the mainstream of non-volatile memory in the market, but with the continuous advancement of semiconductor technology nodes, the feature size below 22nm, the Flash technology based on the traditional floating gate structure is suffering serious technical challenges. bottleneck. Resistive RAM (RRAM) can be integrated at a high density because its resistive characteristics occur in a region of a few nanometers; the basic condition for high-density integration is that the device must meet the requirements of low power consumption in order to solve the high-density partial The problem of heat dissipation.
因此，研究人员在探索改进阻变存储器中，都在追求较低的操作电流（主要由reset电流来评判）、较低的功耗。L. Goux等人在文献：Ultralow sub-500nA operating current high-performance TiN\Al2O3\HfO2\Hf\TiN bipolar RRAM achieved through understanding-based stack-engineering 中通过在界面处插入Al2O3层获得了500nA的reset操作电流。H.Y.Lee等人在文献：Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM中通过在TiN和HfOx的界面插入一层Ti层实现了100uA左右的reset电流和较高的擦洗次数。 Therefore, researchers are pursuing lower operating current (mainly judged by the reset current) and lower power consumption when exploring and improving RRAM. L. Goux et al. In the literature: Ultralow sub-500nA operating current high-performance TiN\Al 2 O 3 \HfO 2 \Hf\TiN bipolar RRAM achieved through understanding-based stack-engineering by inserting Al 2 O 3 at the interface layer has a reset operating current of 500nA. HYLee et al . in the literature: Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO 2 Based RRAM achieved a reset current of about 100uA and a higher of scrubbing times.
二氧化硅作为一种与CMOS兼容的材料，有廉价、容易制备的优点。但是到目前为止仍然没有文献和专利报道通过界面处插入一层二氧化硅能降低器件的功耗。 As a material compatible with CMOS, silicon dioxide has the advantages of being cheap and easy to prepare. But so far there are still no literature and patent reports that inserting a layer of silicon dioxide at the interface can reduce the power consumption of the device.
发明内容 Contents of the invention
本发明的目的是针对阻变存储器在高密度集成时存在的功耗问题，提供一种低功耗阻变存储器及其制备方法，该阻变存储器通过使用在电极和氧化钒和之间插入一层二氧化硅介质层，可以有效地降低阻变存储器件的功耗，同时提高了高阻态的一致性。 The object of the present invention is to provide a low power consumption resistive memory and its preparation method for the power consumption problem of resistive memory in high-density integration. The resistive memory is inserted between the electrode and vanadium oxide A silicon dioxide dielectric layer can effectively reduce the power consumption of the resistive memory device, and at the same time improve the consistency of the high-resistance state.
本发明的技术方案： Technical scheme of the present invention:
一种低功耗阻变存储器，由下电极、阻变层和上电极组成并构成叠层结构，其中阻变层为氧化钒薄膜和二氧化硅薄膜叠层结构，各层的厚度分别为：下电极50-200 nm、氧化钒薄膜5-100nm、二氧化硅薄膜1-50nm、上电极50-200 nm。 A low-power resistive variable memory, which is composed of a lower electrode, a resistive layer and an upper electrode and forms a laminated structure, wherein the resistive layer is a laminated structure of a vanadium oxide film and a silicon dioxide film, and the thicknesses of each layer are: The lower electrode is 50-200 nm, the vanadium oxide film is 5-100 nm, the silicon dioxide film is 1-50 nm, and the upper electrode is 50-200 nm.
所述上、下电极的材料为导电金属、金属合金和导电金属化合物，其中导电金属为Al、Ti、Ni、Cu、Ag、W、Au或Pt；金属合金为Pt/Ti、、Cu/Ti、Cu/Au、或Cu/Al且比例任意；导电金属化合物为TiN、TaN、ITO或AZO。 The materials of the upper and lower electrodes are conductive metals, metal alloys and conductive metal compounds, wherein the conductive metals are Al, Ti, Ni, Cu, Ag, W, Au or Pt; the metal alloys are Pt/Ti, Cu/Ti , Cu/Au, or Cu/Al in any ratio; the conductive metal compound is TiN, TaN, ITO or AZO.
一种所述低功耗阻变存储器的制备方法，以硅片为衬底，利用热氧化的方法首先制备二氧化硅绝缘层，再在二氧化硅绝缘层上利用离子束溅射的方法制备Ti粘附层，然后在Ti粘附层上制备低功耗阻变存储器，步骤如下： A method for preparing the low-power resistive variable memory, using a silicon wafer as a substrate, first preparing a silicon dioxide insulating layer by thermal oxidation, and then preparing the silicon dioxide insulating layer by ion beam sputtering Ti adhesion layer, and then prepare low power consumption resistive variable memory on the Ti adhesion layer, the steps are as follows:
1）在Ti粘附层上采用磁控溅射工艺或电子束蒸发工艺制备下电极； 1) Prepare the lower electrode on the Ti adhesion layer by magnetron sputtering process or electron beam evaporation process;
2）在下电极上采用直流溅射或射频溅射法沉积氧化钒薄膜，溅射工艺条件为：本底真空小于10-4 Pa、衬底温度为18-400℃、工作压强0.1-2Pa、氧分压为5-30%、溅射功率为50-250W； 2) The vanadium oxide thin film is deposited on the lower electrode by DC sputtering or radio frequency sputtering. The partial pressure is 5-30%, and the sputtering power is 50-250W;
3）在氧化钒薄膜上采用化学气相沉积（CVD）或物理气相沉积（PVD）制备二氧化硅薄膜，化学气相沉积工艺条件为：采用PECVD方法制备，本底真空小于10-5Pa、工作压强为0.1-5Pa、射频功率为50-300W、反应气体为SiH4 和N2O，SiH4流量为50-600sccm、N2O流量为20-50sccm；物理气相沉积工艺条件为：溅射方法为射频磁控溅射，以二氧化硅为靶材，本底真空小于10-4 Pa、衬底温度为18-800℃、工作压强0.1-2Pa、溅射功率为50-250W； 3) The silicon dioxide film is prepared on the vanadium oxide film by chemical vapor deposition ( CVD) or physical vapor deposition (PVD). 0.1-5Pa, RF power 50-300W, reaction gas SiH 4 and N 2 O, SiH 4 flow 50-600sccm, N 2 O flow 20-50sccm; physical vapor deposition process conditions: sputtering method is RF magnetron sputtering, with silicon dioxide as the target material, the background vacuum is less than 10 -4 Pa, the substrate temperature is 18-800°C, the working pressure is 0.1-2Pa, and the sputtering power is 50-250W;
4）在二氧化硅薄膜上采用直流磁控溅射工艺或电子束蒸发工艺制备上电极。 4) The upper electrode is prepared on the silicon dioxide film by DC magnetron sputtering process or electron beam evaporation process.
所述制备下电极、上电极的工艺参数，磁控溅射工艺条件为：以金属靶为靶材，本底真空小于10-4 Pa、衬底温度为18-800℃、工作压强0.1-2Pa、溅射功率为50-250W；电子束蒸发工艺条件为：本底真空小于10-4 Pa，采用低熔点的金属作为蒸发源，加热方式为干锅加热或电子束加热。 The process parameters for preparing the lower electrode and the upper electrode, the magnetron sputtering process conditions are as follows: a metal target is used as the target material, the background vacuum is less than 10 -4 Pa, the substrate temperature is 18-800°C, and the working pressure is 0.1-2Pa , The sputtering power is 50-250W; the electron beam evaporation process conditions are: the background vacuum is less than 10 -4 Pa, the metal with a low melting point is used as the evaporation source, and the heating method is dry pot heating or electron beam heating.
所述制备好上电极的器件通过PECVD的方法生长一层二氧化硅作为保护层，工艺参数为：本底真空小于10-5Pa、工作压强为0.1-5Pa、射频功率为50-300W、反应气体为SiH4 和N2O，SiH4 流量为50-600sccm、N2O流量为20-50sccm。 The device on which the upper electrode has been prepared grows a layer of silicon dioxide as a protective layer by PECVD. The process parameters are: the background vacuum is less than 10 -5 Pa, the working pressure is 0.1-5Pa, the radio frequency power is 50-300W, the reaction The gas is SiH 4 and N 2 O, the flow rate of SiH 4 is 50-600 sccm, and the flow rate of N 2 O is 20-50 sccm.
本发明的优点和有益效果是： Advantage and beneficial effect of the present invention are:
该阻变存储器通过在电极和氧化钒薄膜间插入一层二氧化硅，可有效降低了阻变存储器件的reset电流，降低器件的功耗，相对于单层的氧化钒薄膜的阻变器件，功耗能可降低一个数量级。 By inserting a layer of silicon dioxide between the electrode and the vanadium oxide film, the resistive memory can effectively reduce the reset current of the resistive memory device and reduce the power consumption of the device. Compared with the resistive device with a single layer of vanadium oxide film, Power consumption can be reduced by an order of magnitude.
附图说明 Description of drawings
图 1为该低功耗阻变存储器结构示意图。 Figure 1 is a schematic diagram of the structure of the low-power resistive memory.
图中：1.下电极 2.氧化钒薄膜 3.二氧化硅薄膜 4.上电极
In the figure: 1.
图 2为该阻变存储器的电流电压特性曲线。 Figure 2 is the current-voltage characteristic curve of the RRAM.
图 3为该阻变存储器擦写操作（endurance）测试图。 Figure 3 is a test diagram of the resistive memory erase and write operation (endurance).
具体实施方式 Detailed ways
实施例：Example:
一种低功耗阻变存储器，如图1所示，由铜下电极1、阻变层和铝上电极4组成并构成叠层结构，其中阻变层为氧化钒薄膜3和二氧化硅薄膜4叠层结构，各层的厚度分别为：铜下电极100 nm、氧化钒薄膜70nm、二氧化硅薄膜10nm、铝上电极100 nm。
A low-power resistive variable memory, as shown in Figure 1, consists of a copper lower electrode 1, a resistive layer and an aluminum
该阻变存储器的制备方法，以硅片为衬底，利用热氧化的方法首先制备二氧化硅绝缘层，再在二氧化硅绝缘层上利用离子束溅射的方法制备5 nm厚的Ti粘附层，然后在Ti粘附层上制备低功耗阻变存储器，步骤如下： The preparation method of the resistive variable memory uses a silicon wafer as a substrate, firstly prepares a silicon dioxide insulating layer by thermal oxidation, and then prepares a 5 nm thick Ti paste on the silicon dioxide insulating layer by ion beam sputtering. Adhesive layer, and then prepare a low-power resistive variable memory on the Ti adhesive layer, the steps are as follows:
1）在Ti粘附层上采用直流磁控溅射工艺制备下电极，直流磁控溅射工艺条件为：以金属靶为靶材，本底真空5×10-4 Pa、衬底温度为300℃、工作压强0.5Pa、溅射功率为50W； 1) The lower electrode was prepared on the Ti adhesion layer by DC magnetron sputtering process. The DC magnetron sputtering process conditions were as follows: a metal target was used as the target material, the background vacuum was 5×10 -4 Pa, and the substrate temperature was 300 ℃, working pressure 0.5Pa, sputtering power 50W;
2）在下电极上采用射频磁控溅射制备70nm厚的氧化钒薄膜，溅射工艺条件为：直径Φ60mm氧化钒靶材，溅射模式为射频（RF）磁控溅射，本底真空小于5×10-4 Pa、衬底温度为22℃、工作压强1Pa、溅射功率为100W，反应气体O2、Ar流量分比为为16、64 Sccm； 2) A 70nm thick vanadium oxide film is prepared on the lower electrode by radio frequency magnetron sputtering. The sputtering process conditions are: a diameter of Φ60mm vanadium oxide target, the sputtering mode is radio frequency (RF) magnetron sputtering, and the background vacuum is less than 5 ×10 -4 Pa, the substrate temperature is 22°C, the working pressure is 1Pa, the sputtering power is 100W, and the reaction gas O 2 and Ar flow ratios are 16 and 64 Sccm;
3）在氧化钒薄膜上采用射频磁控溅射工艺沉积10nm二氧化硅薄膜, 溅射工艺：直径Φ60mm二氧化硅靶材，溅射模式为射频（RF）磁控溅射，本底真空小于5×10-4 Pa、衬底温度为22℃、工作压强1Pa、溅射功率为100W，反应气体Ar流量20 Sccm； 3) Deposit 10nm silicon dioxide film on the vanadium oxide film by radio frequency magnetron sputtering process, sputtering process: diameter Φ60mm silicon dioxide target, sputtering mode is radio frequency (RF) magnetron sputtering, the background vacuum is less than 5×10 -4 Pa, the substrate temperature is 22°C, the working pressure is 1Pa, the sputtering power is 100W, and the reaction gas Ar flow rate is 20 Sccm;
4）在二氧化硅薄膜上采用直流磁控溅射工艺制备上电极，直流磁控溅射工艺条件为：以金属靶为靶材，本底真空5×10-4 Pa、衬底温度为300℃、工作压强1Pa、溅射功率为100W； 4) The upper electrode is prepared on the silicon dioxide film by DC magnetron sputtering process. The DC magnetron sputtering process conditions are as follows: a metal target is used as the target material, the background vacuum is 5×10 -4 Pa, and the substrate temperature is 300 ℃, working pressure 1Pa, sputtering power 100W;
5）将制备好上电极的器件通过PECVD的方法生长一层二氧化硅作为保护层，工艺参数为：本底真空5×10-4Pa、工作压强为3Pa、射频功率为150W、反应气体为SiH4 和N2O，SiH4 流量为50sccm、N2O流量为20sccm。
5) Grow a layer of silicon dioxide as a protective layer on the device with the upper electrode prepared by PECVD. The process parameters are: background vacuum 5×10 -4 Pa,
电学特性通过半导体参数分析仪测试，图 2为该阻变存储器的电流电压特性曲线，图中表明：该器件的电学特性为典型的双极性特性，限流为5μA时reset电流为2μA，得到了比较低的功耗。图3为该器件的擦写的循环次数，图中表明该器件在直流扫描模式下有800次的循环次数，并且高阻态有较好的一致性。 The electrical characteristics are tested by a semiconductor parameter analyzer. Figure 2 is the current-voltage characteristic curve of the resistive variable memory. The figure shows that the electrical characteristics of the device are typical bipolar characteristics, and the reset current is 2 μA when the current limit is 5 μA. A relatively low power consumption. Figure 3 shows the number of erasing and writing cycles of the device, which shows that the device has a cycle number of 800 in the DC scanning mode, and the high-impedance state has a good consistency.
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| CN109704596A (en) * | 2019-03-01 | 2019-05-03 | 昆山福钻新材料科技有限公司 | A kind of antireflective conductive film of index matching and preparation method thereof |
| CN109980083A (en) * | 2019-04-17 | 2019-07-05 | 河南大学 | A kind of small area electrode resistance-variable storing device of filament mechanism and preparation method thereof |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109704596A (en) * | 2019-03-01 | 2019-05-03 | 昆山福钻新材料科技有限公司 | A kind of antireflective conductive film of index matching and preparation method thereof |
| CN109980083A (en) * | 2019-04-17 | 2019-07-05 | 河南大学 | A kind of small area electrode resistance-variable storing device of filament mechanism and preparation method thereof |
| CN109980083B (en) * | 2019-04-17 | 2024-06-07 | 河南大学 | Small-area electrode resistance random access memory with filament mechanism and preparation method thereof |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
| CN113130741B (en) * | 2021-02-26 | 2022-09-13 | 华中科技大学 | A kind of vanadium oxide gate tube with high thermal resistance thermal insulation layer and preparation method thereof |
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