CN103296205A - Low power consumption resistive random access memory and manufacturing method thereof - Google Patents
Low power consumption resistive random access memory and manufacturing method thereof Download PDFInfo
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- CN103296205A CN103296205A CN2013102730381A CN201310273038A CN103296205A CN 103296205 A CN103296205 A CN 103296205A CN 2013102730381 A CN2013102730381 A CN 2013102730381A CN 201310273038 A CN201310273038 A CN 201310273038A CN 103296205 A CN103296205 A CN 103296205A
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Abstract
A low power consumption resistive random access memory consists of a bottom electrode, a resistive random layer and a top electrode. The bottom electrode, the resistive random layer and the top electrode form a laminated structure, wherein the resistive random layer is a laminated structure of a vanadium oxide thin film and a silicon dioxide thin film, the thickness of the lower electrode is 50-200 nm, the thickness of the vanadium oxide thin film is 5-100 nm, the thickness of silicon dioxide thin film is 1-50 nm and the thickness of the upper electrode is 50-200 nm. The manufacturing method of the low power consumption resistive random access memory is that every layer of thin film is sequentially manufactured through a method of magnetron sputtering, ion beam sputtering or electron beam evaporation. The low power consumption resistive random access memory and the manufacturing method thereof have the advantages that due to the fact that a layer of silicon dioxide is inserted between the electrode and the vanadium oxide thin film in the resistive random access memory, reset currents of the resistive random access memory device can be reduced effectively, the power consumption of the device is reduced, and the power consumption can be reduced by one order of magnitude compared with that of a resistive random device of a single-layer vanadium oxide thin film.
Description
Technical field
The invention belongs to microelectronics technology, particularly a kind of low-power consumption resistance-variable storing device and preparation method thereof.
Background technology
Computer technology, Internet technology develop rapidly in recent years, non-volatility memorizer spare is played the part of more and more important role in semicon industry.And non-volatility memorizer is main flow with flash memory (Flash) still in the market, but along with constantly the pushing ahead of semiconductor technology node, and the characteristic size below 22nm just is being subjected to serious technical bottleneck based on the Flash technology of traditional floating gate structure.Resistance-variable storing device (RRAM) is because its resistive characteristic occurs in the zone of several nanometers, so resistance-variable storing device is can high density integrated; Superintegrated primary condition is the requirement that device must satisfy low-power consumption, could solve the problem of the local heat radiation of device high density.
Therefore, the researcher is pursuing lower operating current (mainly being passed judgment on by the reset electric current), lower power consumption in exploring the improvement resistance-variable storing device.L. people such as Goux is at document: Ultralow sub-500nA operating current high-performance TiN Al
2O
3HfO
2Hf among the TiN bipolar RRAM achieved through understanding-based stack-engineering by inserting Al at the interface
2O
3Layer has obtained the reset operating current of 500nA.People such as H.Y.Lee are at document: Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO
2Pass through at TiN and HfO among the Based RRAM
xThe interface insert one deck Ti layer and realized reset electric current about 100uA and higher scouring number of times.
Silicon dioxide has the advantage of cheapness, easy preparation as a kind of and cmos compatible material.But up to the present still there are not document and patent report by inserting the power consumption that layer of silicon dioxide can reduce device at the interface.
Summary of the invention
The objective of the invention is the power problems that when high density is integrated, exists at resistance-variable storing device, a kind of low-power consumption resistance-variable storing device and preparation method thereof is provided, this resistance-variable storing device by use electrode and vanadium oxide and between insert the layer of silicon dioxide dielectric layer, can reduce the power consumption of resistance-change memory device effectively, improve the consistency of high-impedance state simultaneously.
Technical scheme of the present invention:
A kind of low-power consumption resistance-variable storing device, form and constitute laminated construction by bottom electrode, change resistance layer and top electrode, wherein change resistance layer is vanadium oxide film and silica membrane laminated construction, and the thickness of each layer is respectively: bottom electrode 50-200 nm, vanadium oxide film 5-100nm, silica membrane 1-50nm, top electrode 50-200 nm.
The material of described upper and lower electrode is conducting metal, metal alloy and conductive metallic compound, and wherein conducting metal is Al, Ti, Ni, Cu, Ag, W, Au or Pt; Metal alloy be Pt/Ti,, Cu/Ti, Cu/Au or Cu/Al and ratio be any; Conductive metallic compound is TiN, TaN, ITO or AZO.
A kind of preparation method of described low-power consumption resistance-variable storing device, be substrate with the silicon chip, utilize the method for thermal oxidation at first to prepare silicon dioxide insulating layer, utilize the method for ion beam sputtering to prepare the Ti adhesion layer at silicon dioxide insulating layer again, at Ti adhesion layer preparation low-power consumption resistance-variable storing device, step is as follows then:
1) adopt magnetron sputtering technique or electron beam evaporation process to prepare bottom electrode at the Ti adhesion layer;
2) adopt direct current sputtering or radio frequency sputtering method deposition vanadium oxide film at bottom electrode, the sputtering technology condition is: base vacuum is less than 10
-4Pa, underlayer temperature are that 18-400 ℃, operating pressure 0.1-2Pa, partial pressure of oxygen are that 5-30%, sputtering power are 50-250W;
3) adopt chemical vapor deposition (CVD) or physical vapor deposition (PVD) to prepare silica membrane at vanadium oxide film, the chemical vapor deposition method condition is: adopt the preparation of PECVD method, base vacuum is less than 10
-5Pa, operating pressure are that 0.1-5Pa, radio-frequency power are that 50-300W, reacting gas are SiH
4And N
2O, SiH
4Flow is 50-600sccm, N
2The O flow is 20-50sccm; The physical gas-phase deposition condition is: sputtering method is rf magnetron sputtering, is target with silicon dioxide, and base vacuum is less than 10
-4Pa, underlayer temperature are that 18-800 ℃, operating pressure 0.1-2Pa, sputtering power are 50-250W;
4) adopt magnetically controlled DC sputtering technology or electron beam evaporation process to prepare top electrode at silica membrane.
The technological parameter of described preparation bottom electrode, top electrode, the magnetron sputtering technique condition is: be target with the metallic target, base vacuum is less than 10
-4Pa, underlayer temperature are that 18-800 ℃, operating pressure 0.1-2Pa, sputtering power are 50-250W; The electron beam evaporation process condition is: base vacuum is less than 10
-4Pa adopts low-melting metal as evaporation source, and mode of heating is for doing pot heating or electron beam heating.
The described device for preparing top electrode is grown layer of silicon dioxide as protective layer by the method for PECVD, and technological parameter is: base vacuum is less than 10
-5Pa, operating pressure are that 0.1-5Pa, radio-frequency power are that 50-300W, reacting gas are SiH
4And N
2O, SiH
4Flow is 50-600sccm, N
2The O flow is 20-50sccm.
Advantage of the present invention and beneficial effect are:
This resistance-variable storing device is by inserting layer of silicon dioxide between electrode and vanadium oxide film, can effectively reduce the reset electric current of resistance-change memory device, reduce the power consumption of device, with respect to the resistive device of the vanadium oxide film of individual layer, power consumption can reduce an order of magnitude.
Description of drawings
Fig. 1 is this low-power consumption resistance variation memory structure schematic diagram.
Among the figure: 1. bottom electrode 2. vanadium oxide films 3. silica membranes 4. top electrodes
Fig. 2 is the current-voltage characteristic curve of this resistance-variable storing device.
Fig. 3 is the erasable operation of this resistance-variable storing device (endurance) resolution chart.
Embodiment
Embodiment:
A kind of low-power consumption resistance-variable storing device, as shown in Figure 1, form and constitute laminated construction by copper bottom electrode 1, change resistance layer and aluminium top electrode 4, wherein change resistance layer is vanadium oxide film 3 and silica membrane 4 laminated construction, and the thickness of each layer is respectively: copper bottom electrode 100 nm, vanadium oxide film 70nm, silica membrane 10nm, aluminium top electrode 100 nm.
The preparation method of this resistance-variable storing device, be substrate with the silicon chip, utilize the method for thermal oxidation at first to prepare silicon dioxide insulating layer, utilize the method for ion beam sputtering to prepare the thick Ti adhesion layer of 5 nm at silicon dioxide insulating layer again, at Ti adhesion layer preparation low-power consumption resistance-variable storing device, step is as follows then:
1) adopt magnetically controlled DC sputtering technology to prepare bottom electrode at the Ti adhesion layer, the magnetically controlled DC sputtering process conditions are: be target with the metallic target, and base vacuum 5 * 10
-4Pa, underlayer temperature are that 300 ℃, operating pressure 0.5Pa, sputtering power are 50W;
2) adopt rf magnetron sputtering to prepare the thick vanadium oxide film of 70nm at bottom electrode, the sputtering technology condition is: diameter of phi 60mm vanadium oxide target, sputter pattern are radio frequency (RF) magnetron sputtering, and base vacuum is less than 5 * 10
-4Pa, underlayer temperature are that 22 ℃, operating pressure 1Pa, sputtering power are 100W, reacting gas O
2, Ar flow proportion by subtraction is for being 16,64 Sccm;
3) adopt rf magnetron sputtering process deposits 10nm silica membrane at vanadium oxide film, sputtering technology: diameter of phi 60mm silicon dioxide target, sputter pattern are radio frequency (RF) magnetron sputtering, and base vacuum is less than 5 * 10
-4Pa, underlayer temperature are that 22 ℃, operating pressure 1Pa, sputtering power are 100W, reacting gas Ar flow 20 Sccm;
4) adopt magnetically controlled DC sputtering technology to prepare top electrode at silica membrane, the magnetically controlled DC sputtering process conditions are: be target with the metallic target, and base vacuum 5 * 10
-4Pa, underlayer temperature are that 300 ℃, operating pressure 1Pa, sputtering power are 100W;
5) device that will prepare top electrode is grown layer of silicon dioxide as protective layer by the method for PECVD, and technological parameter is: base vacuum 5 * 10
-4Pa, operating pressure are that 3Pa, radio-frequency power are that 150W, reacting gas are SiH
4And N
2O, SiH
4Flow is 50sccm, N
2The O flow is 20sccm.
Electrology characteristic is by the test of analyzing parameters of semiconductor instrument, Fig. 2 is the current-voltage characteristic curve of this resistance-variable storing device, show among the figure: this electric properties of devices is typical bipolarity characteristic, and the reset electric current was 2 μ A when current limliting was 5 μ A, had obtained lower power consumption.Fig. 3 is the erasable cycle-index of this device, show among the figure that this device has 800 times cycle-index under the direct current scan pattern, and high-impedance state has consistency preferably.
Claims (5)
1. low-power consumption resistance-variable storing device, it is characterized in that: form and constitute laminated construction by bottom electrode, change resistance layer and top electrode, wherein change resistance layer is vanadium oxide film and silica membrane laminated construction, and the thickness of each layer is respectively: bottom electrode 50-200 nm, vanadium oxide film 5-100nm, silica membrane 1-50nm, top electrode 50-200 nm.
2. according to claim 1 a low-power consumption resistance-variable storing device, it is characterized in that: the material of stating described upper and lower electrode is conducting metal, metal alloy and conductive metallic compound, and wherein conducting metal is Al, Ti, Ni, Cu, Ag, W, Au or Pt; Metal alloy be Pt/Ti,, Cu/Ti, Cu/Au or Cu/Al and ratio be any; Conductive metallic compound is TiN, TaN, ITO or AZO.
3. preparation method of low-power consumption resistance-variable storing device according to claim 1, it is characterized in that: be substrate with the silicon chip, utilize the method for thermal oxidation at first to prepare silicon dioxide insulating layer, utilize the method for ion beam sputtering to prepare the Ti adhesion layer at silicon dioxide insulating layer again, at Ti adhesion layer preparation low-power consumption resistance-variable storing device, step is as follows then:
1) adopt magnetron sputtering technique or electron beam evaporation process to prepare bottom electrode at the Ti adhesion layer;
2) adopt direct current sputtering or radio frequency sputtering method deposition vanadium oxide film at bottom electrode, the sputtering technology condition is: base vacuum is less than 10
-4Pa, underlayer temperature are that 18-400 ℃, operating pressure 0.1-2Pa, partial pressure of oxygen are that 5-30%, sputtering power are 50-250W;
3) adopt chemical vapor deposition (CVD) or physical vapor deposition (PVD) to prepare silica membrane at vanadium oxide film, the chemical vapor deposition method condition is: adopt the preparation of PECVD method, base vacuum is less than 10
-5Pa, operating pressure are that 0.1-5Pa, radio-frequency power are that 50-300W, reacting gas are SiH
4And N
2O, SiH
4Flow is 50-600sccm, N
2The O flow is 20-50sccm; The physical gas-phase deposition condition is: sputtering method is rf magnetron sputtering, is target with silicon dioxide, and base vacuum is less than 10
-4Pa, underlayer temperature are that 18-800 ℃, operating pressure 0.1-2Pa, sputtering power are 50-250W;
4) adopt magnetically controlled DC sputtering technology or electron beam evaporation process to prepare top electrode at silica membrane.
4. according to the preparation method of the described low-power consumption resistance-variable storing device of claim 3, it is characterized in that: the technological parameter of described preparation bottom electrode, top electrode, the magnetron sputtering technique condition is: be target with the metallic target, base vacuum is less than 10
-4Pa, underlayer temperature are that 18-800 ℃, operating pressure 0.1-2Pa, sputtering power are 50-250W; The electron beam evaporation process condition is: base vacuum is less than 10
-4Pa adopts low-melting metal as evaporation source, and mode of heating is for doing pot heating or electron beam heating.
5. according to the preparation method of the described low-power consumption resistance-variable storing device of claim 3, it is characterized in that: the described device for preparing top electrode is grown layer of silicon dioxide as protective layer by the method for PECVD, and technological parameter is: base vacuum is less than 10
-5Pa, operating pressure are that 0.1-5Pa, radio-frequency power are that 50-300W, reacting gas are SiH
4And N
2O, SiH
4Flow is 50-600sccm, N
2The O flow is 20-50sccm.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109704596A (en) * | 2019-03-01 | 2019-05-03 | 昆山福钻新材料科技有限公司 | A kind of antireflective conductive film of index matching and preparation method thereof |
| CN109980083A (en) * | 2019-04-17 | 2019-07-05 | 河南大学 | A kind of small area electrode resistance-variable storing device of filament mechanism and preparation method thereof |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
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| CN101542728A (en) * | 2006-11-22 | 2009-09-23 | 日本电气株式会社 | Nonvolatile storage device |
| US20100155684A1 (en) * | 2008-12-22 | 2010-06-24 | Electronics And Telecommunications Research Institute | Non-volatile memory device and method of forming the same |
| CN102916129A (en) * | 2012-11-07 | 2013-02-06 | 天津理工大学 | Resistance random access memory based on vanadium oxide/zinc oxide laminated structure and preparation method thereof |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1783336A (en) * | 2004-08-21 | 2006-06-07 | 三星电子株式会社 | Antiferromagnetic/paramagnetic resistive device,non-volatile memory and method for fabricating the same |
| CN101542728A (en) * | 2006-11-22 | 2009-09-23 | 日本电气株式会社 | Nonvolatile storage device |
| US20100155684A1 (en) * | 2008-12-22 | 2010-06-24 | Electronics And Telecommunications Research Institute | Non-volatile memory device and method of forming the same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109704596A (en) * | 2019-03-01 | 2019-05-03 | 昆山福钻新材料科技有限公司 | A kind of antireflective conductive film of index matching and preparation method thereof |
| CN109980083A (en) * | 2019-04-17 | 2019-07-05 | 河南大学 | A kind of small area electrode resistance-variable storing device of filament mechanism and preparation method thereof |
| CN109980083B (en) * | 2019-04-17 | 2024-06-07 | 河南大学 | Small-area electrode resistance random access memory with filament mechanism and preparation method thereof |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
| CN113130741B (en) * | 2021-02-26 | 2022-09-13 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
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Application publication date: 20130911 |