CN103295509A - Shift register and display device - Google Patents
Shift register and display device Download PDFInfo
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- CN103295509A CN103295509A CN2012100434088A CN201210043408A CN103295509A CN 103295509 A CN103295509 A CN 103295509A CN 2012100434088 A CN2012100434088 A CN 2012100434088A CN 201210043408 A CN201210043408 A CN 201210043408A CN 103295509 A CN103295509 A CN 103295509A
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Abstract
According to a shift register, a heightening unit of a level of shifting registering module of the shift register is electrically connected with a heightening grid electrode node and an outputting node, and acts based on a first clock signal and the voltage of the heightening grid electrode node. A heightening control unit is electrically connected with the heightening grid electrode node and the outputting node and acts based on a reset signal and a coupling signal. A first threshold voltage compensation unit of the heightening control unit is connected with the reset signal and the coupling signal, and is electrically connected with the heightening grid electrode node. The heightening control unit is electrically connected with the heightening control unit, and acts based on the reset signal, the coupling signal and a second clock signal. A lowering unit is electrically connected with the heightening unit, and electrically connected with a lowering control unit through a lowering grid electrode node.
Description
Technical field
The invention relates to a kind of shift registor and display device.
Background technology
Advantages such as flat display apparatus is frivolous owing to it, low power consumption have been widely used on the products such as communication, information and consumer electronics.Generally speaking, flat display apparatus comprises a display panel, scan driving circuit and a data drive circuit.Wherein scan drive circuit has a shift registor, and it is in order to transmit scanning drive signal, to drive the multi-strip scanning line that is electrically connected with the shift register module in regular turn.
Figure 1A and Figure 1B are respectively the circuit of shift registor of existing single kenel (be example with N-type) thin film transistor (TFT) and the synoptic diagram of signal thereof.From Figure 1A can find transistor T 5 ' grid (nodes X ') voltage be respectively VGH-Vt_ in operational phase I and II
T1And 2*VGH-VGL-Vt_
T1Wherein, Vt_
T1For transistor T 1 ' critical voltage value (threshold voltage), that is transistor T 5 ' grid voltage and transistor T 1 ' the Vt value relevant.Therefore, long-time operation causes transistor critical voltage value Vt rising may cause the transistor switch remarkable action of available circuit to cause circuit malfunction.
In addition, the transistor T 5 of available circuit ' the possible drain current path of grid (nodes X ') (be present in transistor T 4 ' and transistor T 1 ') shown in Figure 1A, and the big young pathbreaker of the leakage current of transistor unit influences nodes X voltage.Fig. 2 is transistor unit (be example with N-type) (V under difference drain electrode-source electrode bias voltage
DS=0.5, V
DS=10) drain electrode-source current (I
DS) and gate-to-source bias voltage (V
GS) curve map.Can find identical V
GSUnder the situation, V
DSThe leakage current of bigger then transistor unit is also bigger.And can be found in operational phase II by the signal graph of Figure 1B, transistor T 1 ' and the V of T4 '
DSBe 2* (VGH-VGL)-Vt_
T1If with VGH=15V, VGL=-5V, Vt_
T1=5V substitution is calculated, this V
DSBe equivalent to 35V, real symbolic animal of the birth year is when high value.Its leakage current under this operating conditions, may cause the nodes X of available circuit ' current potential can't keep and make transistor T 5 ' can't be in the normal output of operational phase II one high levle.
Summary of the invention
Because above-mentioned problem, purpose of the present invention can solve shift registor and the display device that existing issue promotes usefulness for providing a kind of.
For reaching above-mentioned purpose, have multistage shift register module according to a kind of shift registor of the present invention and be connected in series.One of them grade shift register module comprises to be drawn high unit, and draws high control module, and drag down control module and and drag down the unit.Draw high that gate node is drawn high in unit and one and an output node is electrically connected, and according to one first clock signal (clock signal) and draw high the voltage of gate node and start.Draw high control module and draw high gate node and be electrically connected with output node, and the start according to a reset signal and a coupled signal, the one first limit voltage compensating unit of drawing high control module connects reset signal and coupled signal, and with draw high gate node and be electrically connected.Drag down control module and be electrically connected with drawing high control module, and the start according to reset signal, coupled signal and a second clock signal.Drag down the unit and be electrically connected with drawing high the unit, and drag down gate node and drag down control module and be electrically connected via one.
In one embodiment, the first limit voltage compensating unit comprises one first compensation transistor, a first transistor and one first building-out capacitor.One first end of one first end of first compensation transistor, one first end of first building-out capacitor and the first transistor and a gate terminal are electrically connected via one first common node.One gate terminal of first compensation transistor connects reset signal, and one second end of first building-out capacitor connects coupled signal.One second end of the first transistor with draw high gate node and be electrically connected.
In one embodiment, second end of the first transistor is electrically connected with one the 4th transistor via drawing high gate node.The 4th a transistorized gate terminal with drag down gate node and be electrically connected.The 4th transistorized one first end with draw high gate node and be electrically connected.
In one embodiment, draw high control module and more comprise bias voltage reduction unit (bias reducing unit), it is electrically connected with output node and the first common node, and is electrically connected with the 4th transistorized one second end via a node.
In one embodiment, draw high the unit and comprise one the 5th transistor, the 5th a transistorized gate terminal is electrically connected with drawing high gate node, and the 5th transistorized one first end connects this first clock signal, and the 5th transistorized one second end is electrically connected with output node.
In one embodiment, the high levle of reset signal shifts to an earlier date high levle one phase differential of coupled signal.
In one embodiment, drag down control module and have one second limit voltage compensating unit, the second limit voltage compensating unit connects reset signal and second clock signal, and via dragging down gate node and dragging down the unit and be electrically connected.
In one embodiment, the second limit voltage compensating unit comprises one second compensation transistor, one the 3rd transistor and one second building-out capacitor.One first end of second compensation transistor, one first end of second building-out capacitor and the 3rd transistorized one first end and a gate terminal are electrically connected via one second common node.One gate terminal of second compensation transistor connects reset signal, and one second end of second building-out capacitor connects the second clock signal.The 3rd transistorized one second end with drag down gate node and be electrically connected.
In one embodiment, drag down the unit and comprise one the 6th transistor, the 6th a transistorized gate terminal is electrically connected with dragging down gate node, and the 6th transistorized one first end is electrically connected with output node.
In one embodiment, one of the shift register module preceding secondary moves one of temporary module output and draws high the voltage of gate node as reset signal.
In one embodiment, coupled signal moves an output node of temporary module from previous stage.
For reaching above-mentioned purpose, comprise a display panel, data scanning driving circuit and a scan driving circuit according to a kind of display device of the present invention.Wherein, scan drive circuit has above-mentioned shift registor.
From the above, in shift registor of the present invention, the control module of drawing high of one of them grade shift register module comprises one first limit voltage compensating unit, it can be at doing the compensation of a limit voltage with drawing high transistor that the unit is connected, makes it transmit one during a certain specific operation and be not subjected to high levle (VGH) voltage that limit voltage influences to drawing high the unit.By this, the present invention can avoid long-time operation to cause the transistor critical voltage value to raise and cause transistor switch remarkable action and circuit malfunction, and then lifting and overall efficiency.
Description of drawings
Figure 1A and Figure 1B are respectively the circuit of existing shift registor and the synoptic diagram of signal thereof;
Fig. 2 is the drain electrode-source current of transistor unit under difference drain electrode-source electrode bias voltage and the curve map of gate-to-source bias voltage;
Fig. 3 A is the block schematic diagram of the wherein one-level shift register module of a shift registor of preferred embodiment of the present invention;
Fig. 3 B is a circuit diagram of implementing aspect of the shift register module of Fig. 3 A;
Fig. 4 is the signal schematic representation of the shift register module of Fig. 3 B;
Fig. 5 shows accurate position and the relation of each signal among Fig. 4;
Fig. 6 is the transistorized switch list of shift register module each in each operating period shown in Fig. 3 B;
Fig. 7 is the current potential table of each node of shift register module in each operating period shown in Fig. 3 B;
Fig. 8 shows drain current path A, the B that the shift register module shown in Fig. 3 B is possible;
Fig. 9 is the configuration diagram of a kind of shift registor of preferred embodiment of the present invention;
Figure 10 is the signal schematic representation of shift registor shown in Figure 9;
Another changes the configuration diagram of the shift registor of aspect to Figure 11 for the present invention;
Figure 12 is the signal schematic representation of shift registor shown in Figure 11;
Another changes the configuration diagram of the shift registor of aspect to Figure 13 for the present invention;
Figure 14 is the signal schematic representation of shift registor shown in Figure 13;
Figure 15 A is the block schematic diagram of the wherein one-level shift register module of a shift registor of another variation aspect of the present invention;
Figure 15 B is the circuit diagram that one of the shift register module shown in Figure 15 A is implemented aspect; And
Shift register module shown in shift register module shown in Figure 16 A and Figure 16 B is respectively one of the shift register module shown in Fig. 3 A and Figure 15 A and changes aspect.
Drawing reference numeral:
1,1a, 1b, 1c: shift register module
11: draw high the unit
12: draw high control module
121: the first limit voltage compensating units
122: bias voltage reduces the unit
13: drag down control module
131: the second limit voltage compensating units
14: drag down the unit
A: the first common node
B: the second common node
C, X ', Y ': node
CK2: first clock signal
CK3: second clock signal
C1, C2, Cvt1, Cvt2: electric capacity
INI: initialize signal
RST, RST-1, RST-2: reset signal
T0: phase differential
T1 '～T6 ', T1～T8, Tc1, Tc2, Tr1～Tr3, T_ini: transistor
S (n): coupled signal
S (n+1): output node
SR1, SR2, SR3: shift registor
VGH: high levle
VGL: low level
VREF, VREF2: with reference to accurate position
VST: signal is initiated in scanning
X: draw high gate node
Y: drag down gate node
Embodiment
Hereinafter with reference to correlative type, a kind of shift registor and display device according to preferred embodiment of the present invention are described, wherein components identical will be illustrated with identical reference marks.
Fig. 3 A is the block schematic diagram of the wherein one-level shift register module 1 of a shift registor of preferred embodiment of the present invention, and Fig. 3 B is the circuit diagram that one of this shift register module 1 is implemented aspect.
Draw high unit 11 and and draw high gate node X and an output node S (n+1) (n for 〉=0 integer) and is electrically connected, and foundation one first clock signal C K2 and draw high the voltage of gate node X and start.
Draw high control module 12 and be electrically connected with output node S (n+1) with drawing high gate node X, and the start according to a reset signal RST and a coupled signal S (n).In this, coupled signal S (n) is an output node S (n) who moves temporary module from previous stage; In other embodiments, coupled signal also can be copied the signal of being exported by output node S (n) from system.Draw high control module 12 and have one first limit voltage compensating unit, 121, the first limit voltage compensating units 121 and connect reset signal RST and coupled signals, and with draw high gate node X and be electrically connected.
Drag down control module 13 and be electrically connected with drawing high control module 11, and the start according to reset signal RST, coupled signal and a second clock signal CK3.
Drag down unit 14 and be electrically connected with drawing high unit 11, and drag down gate node Y and drag down control module 13 and be electrically connected via one.
Below describe in detail and draw high unit 11, draw high control module 12, drag down control module 13 and drag down unit 14.
Draw high unit 11 and comprise one the 5th transistor T 5, one gate terminal of the 5th transistor T 5 with draw high gate node X and be electrically connected, one first end of the 5th transistor T 5 connects the first clock signal C K2, one second end of the 5th transistor T 5 is electrically connected to export one with output node S (n+1) and drives signal, drives the sweep signal that signal can for example be used as display panel.
The first limit voltage compensating unit 121 comprises one first compensation transistor Tc1, a first transistor T1 and one first building-out capacitor Cvt1.One first end of one first end of the first compensation transistor Tc1, one first end of the first building-out capacitor Cvt1 and the first transistor T1 and one gate terminal are electrically connected via one first common node a.The gate terminal of the first compensation transistor Tc1 connects reset signal RST, and one second end of the first compensation transistor Tc1 connects one with reference to accurate position VREF.One second end of the first building-out capacitor Cvt1 connects coupled signal S (n).In this, the first building-out capacitor Cvt1 is as the usefulness of coupling capacitance.One second end of the first transistor T1 is electrically connected with drawing high gate node X, and the grid of unit 11 is drawn high in control.
In addition, second end of the first transistor T1 is electrically connected with one the 4th transistor T 4 via drawing high gate node X.One gate terminal of the 4th transistor T 4 is electrically connected with dragging down gate node Y, and the 4th transistorized one first end is electrically connected with drawing high gate node X, and the 4th transistorized one second end is connected with a node c.
In addition, draw high control module 12 and more comprise bias voltage reduction unit (bias reducing unit) 122, it is electrically connected with output node S (n+1) and the first common node a, and is electrically connected with one second end of the 4th transistor T 4 via node c.Bias voltage reduces unit 122 and comprises transistor Tr 1, Tr2, Tr3.Wherein, transistor Tr 1, Tr3 grid, drain electrode mutual connection separately forms a diode connection, and is connected in output node S (n+1).The drain electrode of the source electrode of transistor Tr 1 and transistor Tr 2 is connected in node c.The source electrode of transistor Tr 2 is connected to a low level VGL, and its grid is connected in and drags down gate node Y.The source electrode of transistor Tr 3 is connected in the first common node a.Bias voltage reduces unit 122 can be in the operating period (operation period) of output node S (n+1) output high levle signal, reduce the node voltage difference on the drain current path of drawing high gate node X and suppress leakage current, and then promote the usefulness of displacement working storage; This can further specify below advantage.
Drag down control module 13 and have one second limit voltage compensating unit 131.The second limit voltage compensating unit 131 connects reset signal RST and second clock signal CK3, and via dragging down gate node Y and dragging down unit 14 and be electrically connected.The second limit voltage compensating unit 131 comprises one second compensation transistor Tc2, one the 3rd transistor T 3 and one second building-out capacitor Cvt2.One first end (drain electrode) of one first end (drain electrode) of the second compensation transistor Tc2, one first end of the second building-out capacitor Cvt2 and the 3rd transistor T 3 and one gate terminal are electrically connected via one second common node b.In this, the second building-out capacitor Cvt2 is the usefulness as coupling capacitance.The gate terminal of the second compensation transistor Tc2 connects reset signal RST, and one second end (source electrode) connects one with reference to accurate position VREF.One second end of the second building-out capacitor Cvt2 connects second clock signal CK3.One second end (source electrode) of the 3rd transistor T 3 is electrically connected with dragging down gate node Y, and control drags down the grid of unit 14 and transistor T 4, Tr2.
Drag down unit 14 and comprise one the 6th transistor T 6.One gate terminal of the 6th transistor T 6 is electrically connected with dragging down gate node Y, and one first end (drain electrode) of the 6th transistor T 6 is electrically connected with output node S (n+1), and one second end (source electrode) connects a low level VGL.
In addition, the grid of transistor T 2, T7 is subjected to coupled signal S (n) and output node signal S (n+1) control respectively.The grid of transistor T 8 is connected in the second common node b, and the connection of one first end drags down gate node Y, and one second end connects one with reference to accurate position VREF.In other embodiments, transistor T 8 can omit, and its function can be replaced by transistor T 3.One first end of capacitor C 1 is connected in draws high gate node X, and one second end is connected in output node S (n+1).One first end of capacitor C 2 is connected in and drags down gate node Y, and one second end is connected in a low level VGL.Capacitor C 1, C2 are storage unit, except suppressing effect of leakage, also can reduce noise.In other embodiments, capacitor C 1 can be omitted, and second end of capacitor C 2 can be connected in other any direct current (DC) voltage.
More than explanation is to be example with the N-type transistor, but as long as accurate position do suitably to adjust also applicable to the P-type transistor.
Fig. 4 is the signal schematic representation of the shift register module 1 of Fig. 3 B, and wherein, ts represents the sweep trace opening time, the ta 〉=0 expression clock signal C K2 interval adjacent with CK3, and t0 represents an interval of the high levle of the high levle of reset signal RST and coupled signal S (n).In this, the high levle of reset signal RST shifts to an earlier date the high levle one phase differential t0 of coupled signal S (n), and the preferably is phase differential t0 〉=ts.Fig. 5 shows accurate position and the relation of each signal of Fig. 4.Wherein, can reset one with reference to accurate position VREF for making the first limit voltage compensating unit 121, the high levle of reset signal RST needs the accurate position greater than VREF.Fig. 6 is the transistorized switch list of shift register module 1 each in each operating period shown in Fig. 3 B.Fig. 7 is the current potential table of each node of shift register module 1 in each operating period shown in Fig. 3 B.Below please refer to Fig. 3 B to Fig. 7 with the start situation of explanation shift register module 1 in each operating period.
Operating period Rst
Reset signal RST is a high levle and greater than the high levle with reference to accurate position VREF, so transistor T c1, Tc2, T1, T3, T8 are for opening (ON).The first common node a and the second common node b will be reset to a high levle VREF.The accurate position that drags down gate node Y is reset to position VREF-Vt_ surely
T8(Vt_
T8Critical voltage value for transistor T 8), its value is greater than VGL+Vt_
T6(Vt_
T6Critical voltage value for transistor T 6), thus transistor T 6 for ON and export a low level VGL to output node S (n+1).Transistor Tr 2, T4 also are ON.The voltage of drawing high gate node X this moment is reset to position surely between VGL～VREF-Vt_
T1In design, the standard of drawing high gate node X is positioned at is VGL during this as far as possible, and make transistor T 5 be OFF (can make transistor Tr 2, T4, T1 have a suitable transistor breadth length ratio reaches).If but the accurate position of nodes X during this makes transistor T 5 be ON, then the signal of clock signal C K2 is VGL, conflicts so can't cause with the output of transistor T 6.
Operating period A
Reset signal RST is low level VGL, so transistor T c1, Tc2 are OFF.The second common node b still is high levle VREF, so transistor T 8 is ON, and makes the accurate position that drags down gate node Y still be VREF-Vt_
T8So transistor T 6 is ON, and export a low level VGL to output node S (n+1).Transistor Tr 2, T4 are ON also, and drawing high gate node X voltage at this moment is a low level VGL, so transistor T 5 is OFF.And the current potential of the first common node a will be discharged to accurate position through transistor T 1 and be VGL+Vth_
T1(Vt_
T1Critical voltage value for transistor T 1), and this moment transistor T 1 be OFF.
Operating period B
Coupled signal S (n) is a high levle VGH, makes transistor T 2 for ON and transmits a low level VGL to node Y, so transistor Tr 2, T4, T6 are OFF.Node a will be coupled (coupling) to VGH+Vth_ by capacitor C vt1
T1, and see through transistor T 1 and be sent to nodes X and make its accurate position be VGH, make transistor T 5 for the low level VGL of ON and transmission clock signal CK2 to output node S (n+1).And the current potential of node b sees through transistor T 3 and is discharged to accurate position and is VGL+Vth_
T3(Vt_
T3Critical voltage value for transistor T 3), and transistor T 3 this moment be OFF.Therefore transistor T 8 is OFF.
Operating period C
The first clock signal C K2 is a high levle VGH, and nodes X will be coupled to VGH*2-VGL, so transistor T 5 is ON and transmits high levle VGH to output node S (n+1).So transistor T 7 is for ON and be sent to accurate position VGL to node Y, so that transistor T 6, Tr2, T4 are OFF.And transistor Tr 3, Tr1 are ON and transmit VGH-Vt_ respectively
Tr3(Vt_
Tr3Critical voltage value for transistor Tr 3) and VGH-Vt_
Tr1(Vt_
Tr1Critical voltage value for transistor Tr 1) to node a and c.Node b still is VGL+Vth_
T3, and make transistor T 8 OFF.
Operating period D
Second clock signal CK3 is a high levle VGH, and the accurate position of node b will be coupled to VGH+Vth_
T3So transistor T 8 is ON, the accurate position of node Y is VGH+Vth_
T3-Vth_
T8, suppose Vth_
T3=Vth_
T8, then the accurate position of node Y is VGH.So transistor T 6 is for ON and export a low level VGL to output node S (n+1).And transistor Tr 2, T4 also are ON, and nodes X voltage at this moment is a low level VGL, make transistor T 5 be OFF.Node a will be discharged to VGL+Vt_ this moment
T1
Operating period E
Second clock signal CK3 is a low level VGL, and the accurate position of node b will be coupled to VGL+Vth_
T3, make transistor T 8 be OFF, but the accurate position of node Y is still remained in high levle VGH by capacitor C 2, so transistor T 6 is ON and exports a low level VGL to node S (n+1).Because the high levle VGH of node Y, transistor Tr 2, T4 also are ON, and nodes X voltage at this moment is a low level VGL, make transistor T 5 be OFF.This moment, node a still was VGL+Vt_
T1
Because transistor T 1, T3 need conducting one high levle (High) in operating period, so present embodiment can be done limit voltage compensation at this transistor T 1, T3 by the first limit voltage compensating unit 121 and the second limit voltage compensating unit 131, can distinguish B and D during operation and transmit a high levle (VGH) to drawing high unit 11 and dragging down the gate terminal of unit 14 and the influence that not drifted about by limit voltage own.In other embodiments, compensating unit 121,131 also can be only at one of them of transistor T 1 and T3 or in draw high control module 12, drag down select more transistor control module 13 in and arrange in pairs or groups ordered pair when suitable its compensate, this looks closely the situation that the transistor limit voltage drifts about in the control module.The circuit of present embodiment is to be compensated for as a preferred embodiment so that transistor T 1 and T3 are done limit voltage.
In addition, the bias voltage of present embodiment reduction unit 122 is arranged at and draws high on gate node X possible drain current path A, the B, as shown in Figure 8.Utilizing bias voltage to reduce unit 122 can be when operating period C, and the node voltage poor (as the voltage difference of nodes X and node c and the voltage difference of nodes X and node a) that reduces on nodes X possibility leakage path A, the B suppresses leakage current.In other embodiments, bias voltage reduces unit 122 can only be selected path A or B one of them does drain current suppressing, and the circuit of present embodiment is to reduce so that path A and B are carried out bias voltage.
Fig. 9 is the configuration diagram of a kind of shift registor SR1 of preferred embodiment of the present invention, and it can for example be applied to scan driving circuit.Figure 10 is the signal schematic representation of shift registor SR1.Shift registor SR1 comprises multistage shift register module and is connected in series, and one of them grade shift register module has the technical characterictic as shift register module 1.In addition, wherein one of one-level shift register module preceding secondary moves one of temporary module and draws high the voltage of gate node X as the reset signal RST of this grade shift register module.In this, the voltage of drawing high gate node X of first order shift register module is as the voltage of drawing high gate node X of the reset signal RST of third level shift register module, the second level shift register module reset signal RST as fourth stage shift register module, and all the other by that analogy.In addition, first order shift register module connects a reset signal RST-1 with as its reset signal RST, and second level shift register module connects a reset signal RST-2 with as its reset signal RST.In addition, the signal of the output node of first order shift register module is as the coupled signal of second level shift register module, and all the other by that analogy.First order shift register module connects one scan and initiates signal VST as its coupled signal.
The shift registor of present embodiment can have multiple variation aspect, below illustrates it.
Another changes the configuration diagram of the shift registor SR2 of aspect to Figure 11 for the present invention, and Figure 12 is the signal schematic representation of shift registor SR2.In this, the first order is connected same reset signal RST with second level shift register module.
Another changes the configuration diagram of the shift registor SR3 of aspect to Figure 13 for the present invention, and Figure 14 is the signal schematic representation of shift registor SR3.In this, all shift register modules connect same reset signal RST.
Figure 15 A is the circuit diagram that one of this shift register module 1a implements aspect for the block schematic diagram of the wherein one-level shift register module 1a of a shift registor of another variation aspect of the present invention, Figure 15 B.Be that with shift register module 1 main difference shown in Fig. 3 A and Fig. 3 B control module 13 that drags down of shift register module 1a does not have the second limit voltage compensating unit, has the first limit voltage compensating unit 121 and only draw high control module 12.The signal of shift register module 1a can repeat no more in this with reference to Fig. 4.
The shift registor of aforesaid arbitrary aspect can be applicable to a display device, and this display device comprises a display panel, data scanning driving circuit and a scan driving circuit.Wherein, scan drive circuit has above-mentioned shift registor.
In sum, in shift registor of the present invention, the control module of drawing high of one of them grade shift register module comprises one first limit voltage compensating unit, it can be at doing the compensation of a limit voltage with drawing high transistor that the unit is connected, makes it transmit one during a certain specific operation and be not subjected to high levle (VGH) voltage that limit voltage influences to drawing high the unit.By this, the present invention can avoid long-time operation to cause the transistor critical voltage value to raise so that transistor switch remarkable action and circuit malfunction, and then lifting and overall efficiency.
The above only is illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and to its equivalent modifications of carrying out or change, all should be contained in the claim.
Claims (20)
1. a shift registor has multistage shift register module and is connected in series, and it is characterized in that, the described shift register module of one of them grade comprises:
One draws high the unit, draws high gate node with one and an output node is electrically connected, and the start according to one first clock signal and the described voltage of drawing high gate node;
One draws high control module, be electrically connected with described output node with the described gate node of drawing high, and the start according to a reset signal and a coupled signal, the described control module of drawing high has one first limit voltage compensating unit, the described first limit voltage compensating unit connects described reset signal and described coupled signal, and is electrically connected with the described gate node of drawing high;
One drags down control module, be electrically connected with the described control module of drawing high, and the start according to described reset signal, described coupled signal and a second clock signal; And
One drags down the unit, is electrically connected with the described unit of drawing high, and drags down gate node via one and be electrically connected with the described control module that drags down.
2. shift registor as claimed in claim 1, it is characterized in that, the described first limit voltage compensating unit comprises one first compensation transistor, one the first transistor and one first building-out capacitor, one first end of described first compensation transistor, one first end of described first building-out capacitor and one first end of described the first transistor and a gate terminal are electrically connected via one first common node, one gate terminal of described first compensation transistor connects described reset signal, one second end of described first building-out capacitor connects described coupled signal, and one second end of described the first transistor is electrically connected with the described gate node of drawing high.
3. shift registor as claimed in claim 2, it is characterized in that, described second end of described the first transistor is electrically connected with one the 4th transistor via the described gate node of drawing high, the described the 4th a transistorized gate terminal is electrically connected with the described gate node that drags down, and the described the 4th transistorized one first end is electrically connected with the described gate node of drawing high.
4. shift registor as claimed in claim 3, it is characterized in that, the described control module of drawing high more comprises bias voltage reduction unit, and it is electrically connected with described output node and the described first common node, and is electrically connected with the described the 4th transistorized one second end via a node.
5. shift registor as claimed in claim 1, it is characterized in that, the described unit of drawing high comprises one the 5th transistor, the described the 5th a transistorized gate terminal is electrically connected with the described gate node of drawing high, the described the 5th transistorized one first end connects described first clock signal, and the described the 5th transistorized one second end is electrically connected with described output node.
6. shift registor as claimed in claim 1, it is characterized in that, the described control module that drags down has one second limit voltage compensating unit, the described second limit voltage compensating unit connects described reset signal and described second clock signal, and is electrically connected with the described unit that drags down via the described gate node that drags down.
7. shift registor as claimed in claim 6, it is characterized in that, the described second limit voltage compensating unit comprises one second compensation transistor, one the 3rd transistor and one second building-out capacitor, one first end of described second compensation transistor, one first end of described second building-out capacitor and the described the 3rd transistorized one first end and a gate terminal are electrically connected via one second common node, one gate terminal of described second compensation transistor connects described reset signal, one second end of described second building-out capacitor connects described second clock signal, and the described the 3rd transistorized one second end is electrically connected with the described gate node that drags down.
8. shift registor as claimed in claim 1, it is characterized in that, the described unit that drags down comprises one the 6th transistor, and the described the 6th a transistorized gate terminal is electrically connected with the described gate node that drags down, and the described the 6th transistorized one first end is electrically connected with described output node.
9. shift registor as claimed in claim 1 is characterized in that, the high levle of described reset signal shifts to an earlier date high levle one phase differential of described coupled signal.
10. shift registor as claimed in claim 1 is characterized in that, a preceding secondary of described shift register module moves one of temporary module and draws high the voltage of gate node as described reset signal.
11. shift registor as claimed in claim 1 is characterized in that, described coupled signal is from an output node of the temporary module of the described movement of previous stage.
12. a display device is characterized in that, described display device comprises:
One display panel;
One data scanning driving circuit; And
Scan driving circuit has at least one shift registor, and wherein said shift registor has multistage shift register module and is connected in series, and one of them grade shift register module comprises:
One draws high the unit, draws high gate node with one and an output node is electrically connected, and the start according to one first clock signal and the described voltage of drawing high gate node;
One draws high control module, be electrically connected with described output node with the described gate node of drawing high, and the start according to a reset signal and a coupled signal, the described control module of drawing high has one first limit voltage compensating unit, the described first limit voltage compensating unit connects described reset signal and described coupled signal, and is electrically connected with the described gate node of drawing high;
One drags down control module, be electrically connected with the described control module of drawing high, and the start according to described reset signal, described coupled signal and a second clock signal; And
One drags down the unit, is electrically connected with the described unit of drawing high, and drags down gate node via one and be electrically connected with the described control module that drags down.
13. display device as claimed in claim 12, it is characterized in that, the described first limit voltage compensating unit of described shift registor comprises one first compensation transistor, one the first transistor and one first building-out capacitor, one first end of described first compensation transistor, one first end of described first building-out capacitor and one first end of described the first transistor and a gate terminal are electrically connected via one first common node, one gate terminal of described first compensation transistor connects described reset signal, one second end of described first building-out capacitor connects described coupled signal, and one second end of described the first transistor is electrically connected with the described gate node of drawing high.
14. display device as claimed in claim 13, it is characterized in that, described second end of the described the first transistor of described shift registor is electrically connected with one the 4th transistor via the described gate node of drawing high, the described the 4th a transistorized gate terminal is electrically connected with the described gate node that drags down, and the described the 4th transistorized one first end is electrically connected with the described gate node of drawing high.
15. display device as claimed in claim 14, it is characterized in that, the described control module of drawing high of described shift registor more comprises bias voltage reduction unit, it is electrically connected with described output node and the described first common node, and is electrically connected with the described the 4th transistorized one second end via a node.
16. display device as claimed in claim 12, it is characterized in that, the described unit of drawing high of described shift registor comprises one the 5th transistor, the described the 5th a transistorized gate terminal is electrically connected with the described gate node of drawing high, the described the 5th transistorized one first end connects described first clock signal, and the described the 5th transistorized one second end is electrically connected with described output node.
17. display device as claimed in claim 12, it is characterized in that, the described control module that drags down of described shift registor has one second limit voltage compensating unit, the described second limit voltage compensating unit connects described reset signal and described second clock signal, and is electrically connected with the described unit that drags down via the described gate node that drags down.
18. display device as claimed in claim 17, it is characterized in that, the described second limit voltage compensating unit of described shift registor comprises one second compensation transistor, one the 3rd transistor and one second building-out capacitor, one first end of described second compensation transistor, one first end of described second building-out capacitor and the described the 3rd transistorized one first end and a gate terminal are electrically connected via one second common node, one gate terminal of described second compensation transistor connects described reset signal, one second end of described second building-out capacitor connects described second clock signal, and the described the 3rd transistorized one second end is electrically connected with the described gate node that drags down.
19. display device as claimed in claim 12, it is characterized in that, the described unit that drags down of described shift registor comprises one the 6th transistor, the described the 6th a transistorized gate terminal is electrically connected with the described gate node that drags down, and the described the 6th transistorized one first end is electrically connected with described output node.
20. display device as claimed in claim 12 is characterized in that, a preceding secondary of the described shift register module of described shift registor moves one of temporary module and draws high the voltage of gate node as described reset signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210043408.8A CN103295509B (en) | 2012-02-24 | 2012-02-24 | Shift registor and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210043408.8A CN103295509B (en) | 2012-02-24 | 2012-02-24 | Shift registor and display device |
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| CN103295509B (en) | 2016-04-06 |
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Address after: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant after: Qunkang Technology (Shenzhen) Co., Ltd. Applicant after: Innolux Display Group Address before: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant before: Qunkang Technology (Shenzhen) Co., Ltd. Applicant before: Chimei Optoelectronics Co., Ltd. |
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