CN103294089B - Electronic circuit - Google Patents
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- CN103294089B CN103294089B CN201210053972.8A CN201210053972A CN103294089B CN 103294089 B CN103294089 B CN 103294089B CN 201210053972 A CN201210053972 A CN 201210053972A CN 103294089 B CN103294089 B CN 103294089B
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Abstract
The invention relates to an electronic circuit which comprises a first part of a main circuit, a second part of a main circuit, a first operational amplifier, a first adjustment circuit, a second operational amplifier and a second adjustment circuit, wherein the first part of the main circuit receives an input voltage signal inputted to the electronic circuit; an input end of the first operational amplifier is connected with an upper limit reference level; and an input end of the second operational amplifier is connected with a lower limit reference level smaller than the upper limit reference level. During the periord that the input voltage signal of the electronic circuit is smaller than the upper limit reference level and larger than the lower limit reference level, an output voltage signal of the electronic circuit is changed along with the change of the input voltage signal of the electronic circuit; during the period that the input voltage signal of the electronic circuit is larger than the upper limit reference level, the upper limit reference level is output by the electronic circuit; and during the period that the input voltage of the electronic circuit is smaller than the lower limit reference level, the lower limit reference level is outputted by the electromic circuit.
Description
Technical field
The present invention relates to a kind of electronic circuit, relate more specifically to a kind of electronic circuit that can limit its output voltage amplitude scope.
Background technology
The electronic circuit that output voltage signal changes along with the change of input voltage signal has to be applied widely.In the prior art, such circuit has various structures, only illustrates for wherein a kind of structure below.
Fig. 1 is the structured flowchart of the electronic circuit of prior art.Fig. 2 is the circuit legend of the electronic circuit of prior art.Wherein, Vdd represents the power supply of the some electronic devices of electronic circuit 1, and Vout1 represents the voltage signal that the output terminal OUT1 of electronic circuit 1 exports.Below, composition graphs 1 and Fig. 2 illustrate the principle of work of this electronic circuit 1 output voltage signal Vout1:
As shown in Figure 1, the Part I 11 of main body circuit has power end, the input end P11 inputting the input voltage signal Vin1 of electronic circuit 1 and output terminal P12 of connection power supply Vdd, one end ground connection GND of the Part II 12 of main body circuit, the output terminal P12 of the Part I of other end P13 and main body circuit is electrically connected, and is electrically connected with the output terminal of electronic circuit 1 simultaneously.
As shown in Figure 2, the Part I 11 of main body circuit comprises the input end P11 of grid as electronic circuit 1 of NMOS tube T1, a T1, and the drain electrode of T1 connects power supply Vdd, and the source electrode of T1 is as the output terminal P12 of electronic circuit 1.The Part II 12 of main body circuit comprises a constant current source Isource1, and one end ground connection GND, its other end P3 are electrically connected the source electrode of T1.So, NMOS tube T1 and constant current source Isource1 forms a source and follows structure, the source voltage of T1 is followed the change of the change of the grid voltage of T1 and the electric current of constant current source Isource1 and changes, namely the voltage that the output terminal P12 of the Part I 11 of main body circuit exports can be followed the change of the input voltage signal Vin1 of electronic circuit 1 and change, because the output terminal P12 of the output terminal of electronic circuit 1 and the Part I of main body circuit is electrically connected, so the output voltage signal Vout1 of electronic circuit 1 follows the change of its input voltage signal Vin1 and changes.
But as the amplitude of the output voltage signal of an electronic circuit, usually can be limited in certain limit, namely there is higher limit and lower limit in output voltage signal.The output voltage signal Vout1 of electronic circuit 1 of the prior art follows the change of its input voltage signal Vin1 and the change of constant current source Isource1 and changes, when Vin1 occurs excessive or too small, Vout1 will follow excessive or too small, cannot effectively be limited, thus when the situation such as input of Vout1 as next stage electronic circuit, the normal work of next stage electronic circuit can be affected.
Summary of the invention
Proposing the present invention to overcome the above-mentioned problems in the prior art, the object of this invention is to provide a kind of electronic circuit that can limit its output voltage amplitude scope.
The electronic circuit of one aspect of the present invention comprises: the Part I comprising the main body circuit of input end, output terminal and feeder ear, the feeder ear of the Part I of described main body circuit connects the power supply of the Part I operation of provider's circuit, and the input end of the Part I of described main body circuit accepts the input voltage signal inputing to described electronic circuit, comprise the Part II of the main body circuit at two ends, one end ground connection, comprise the Circuit tuning of three ends, its one end is control end, and its another two ends are electrically connected the other end of the output terminal of the Part I of described main body circuit and the Part II of described main body circuit respectively, operational amplifier, one input end access reference level, its output terminal is electrically connected the control end of described Circuit tuning, wherein, when reference level is set as boundary level, another input end described of described operational amplifier be electrically connected the Part II of described main body circuit the other end and as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is greater than described boundary level, the output terminal of described electronic circuit exports described boundary level, during the input voltage signal of described electronic circuit is less than described boundary level, the voltage signal that the output terminal of described electronic circuit exports changes with the change of described electronic circuit input voltage signal, when reference level is set smaller than the lower level of described boundary level, another input end described of described operational amplifier be electrically connected the Part I of described main body circuit output terminal and as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is less than described lower level, the output terminal of described electronic circuit exports described lower level, during the input voltage signal of described electronic circuit is greater than described lower level, the voltage signal that the output terminal of described electronic circuit exports changes with the change of described electronic circuit input voltage signal.
Further, the Part I of described main body circuit is NMOS tube, and its grid is the input end of the Part I of described main body circuit, and its drain electrode is the feeder ear of the Part I of described main body circuit, and its source electrode is the output terminal of the Part I of described main body circuit.The Part II of described main body circuit is constant current source.
Further, when described reference level is set as described boundary level, described Circuit tuning is NMOS tube, and its grid is described control end, the output terminal of the Part I of the described main body circuit of its drain electrode electrical connection, its source electrode exports the output voltage signal of described electronic circuit.
Further, when described reference level is set as described boundary level, described Circuit tuning is NPN triple-pole type transistor, and its base stage is described control end, its collector is electrically connected the output terminal of the Part I of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
Further, when described reference level is set as described lower level, described Circuit tuning is PMOS, and its grid is described control end, its drain electrode connects the other end of the Part II of described main body circuit, and its source electrode exports the output voltage signal of described electronic circuit.
Further, when described reference level is set as described lower level, described Circuit tuning is PNP triple-pole type transistor, and its base stage is described control end, its collector is electrically connected the other end of the Part II of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
The present invention's electronic circuit on the other hand comprises: the Part I comprising the main body circuit of input end, output terminal and feeder ear, the feeder ear of the Part I of described main body circuit connects the power supply of the Part I operation of provider's circuit, and the input end of the Part I of described main body circuit accepts the input voltage signal inputing to described electronic circuit, comprise the Part II of the main body circuit at two ends, one end ground connection, comprise the first operational amplifier of two input ends and an output terminal, one input end access upper limit reference level, comprise the first Circuit tuning of three ends, its one end is control end, and the output terminal of described first operational amplifier of the control end of described first Circuit tuning electrical connection, its another two ends are electrically connected the output terminal of the Part I of described main body circuit and another input end of described first operational amplifier respectively, comprise the second operational amplifier of two input ends and an output terminal, one input end access is less than the lower limit reference level of described upper limit reference level, comprise the second Circuit tuning of three ends, its one end is control end, and the output terminal of described second operational amplifier of the control end of described second Circuit tuning electrical connection, its another two ends are electrically connected the other end of the Part II of described main body circuit and another input end of described second operational amplifier respectively, wherein, another input end electrical connection of another input end of described first operational amplifier and described second operational amplifier as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is less than described upper limit reference level and is greater than described lower limit reference level, the voltage signal that the output terminal of described electronic circuit exports changes with the input voltage signal change of described electronic circuit, during the input voltage signal of described electronic circuit is greater than described upper limit reference level, the output terminal of described electronic circuit exports described upper limit reference level, during the input voltage of described electronic circuit is less than described lower limit reference level, the output terminal of described electronic circuit exports described lower limit reference level.
Further, the Part I of described main body circuit is NMOS tube, and its grid is the input end of the Part I of described main body circuit, and its drain electrode is the feeder ear of the Part I of described main body circuit, and its source electrode is the output terminal of the Part I of described main body circuit.The Part II of described main body circuit is constant current source.
Further, described first Circuit tuning is NMOS tube, and its grid is described control end, and the output terminal of the Part I of the described main body circuit of its drain electrode electrical connection, its source electrode exports the output voltage signal of described electronic circuit.
Further, described first Circuit tuning is NPN triple-pole type transistor, and its base stage is described control end, and its collector is electrically connected the output terminal of the Part I of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
Further, described second Circuit tuning is PMOS, and its grid is described control end, and its drain electrode connects the other end of the Part II of described main body circuit, and its source electrode exports the output voltage signal of described electronic circuit.
Further, described second Circuit tuning is PNP triple-pole type transistor, and its base stage is described control end, and its collector is electrically connected the other end of the Part II of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
Accompanying drawing explanation
The general structure realizing each feature of the present invention is hereafter described with reference to the accompanying drawings.The accompanying drawing provided and associated description for illustration of embodiments of the invention, but are not limited to the present invention.
Fig. 1 is the structured flowchart of the electronic circuit of prior art.
Fig. 2 is the circuit legend of the electronic circuit of prior art.
Fig. 3 is the structured flowchart of the electronic circuit of the first embodiment of the present invention.
Fig. 4 is the circuit legend of the boundary level pattern of the electronic circuit of the first embodiment of the present invention.
Fig. 5 is the circuit legend of the lower level pattern of the electronic circuit of the first embodiment of the present invention.
Fig. 6 is the structured flowchart of the electronic circuit of the second embodiment of the present invention.
Fig. 7 is the circuit legend of the electronic circuit of the second embodiment of the present invention.
Embodiment
Below, description is used for realizing preference pattern of the present invention (hereinafter referred to as embodiment).In addition, the embodiment below described is the preferred embodiments of the present invention, therefore addition of technically desirable various restrictions, as long as but scope of the present invention is not particularly limited the record of the meaning of the present invention in the following description, be just not limited to these modes.
Fig. 3 is the structured flowchart of the electronic circuit of the first embodiment of the present invention.As shown in Figure 3, the electronic circuit 2 of the first embodiment of the present invention comprises: the Part I 21 comprising the main body circuit of input end P21, output terminal P22 and feeder ear, the feeder ear of the Part I 21 of main body circuit connects the power supply Vdd of Part I 21 operation of provider's circuit, and the input end P21 of the Part I 21 of main body circuit accepts the input voltage signal Vin2 inputing to electronic circuit 2, comprise the Part II 22 of the main body circuit at two ends, one end ground connection GND, comprise the Circuit tuning 23 of three ends, its one end is control end C21, and its another two ends are electrically connected the other end P23 of the output terminal P21 of the Part I 21 of main body circuit and the Part II 22 of main body circuit respectively, operational amplifier A 21, one input end P24 accesses reference level VREF, and its output terminal P26 is electrically connected the control end C21 of Circuit tuning 23, when reference level VREF is set as boundary level VREF21, another input end P25 of operational amplifier A 21 be electrically connected the Part II 22 of main body circuit other end P23 and as the output terminal OUT2 of electronic circuit 2, during the input voltage signal Vin2 of electronic circuit 2 is greater than boundary level VREF21, the output terminal OUT2 of electronic circuit 2 exports boundary level VREF21, during the input voltage signal Vin2 of electronic circuit 2 is less than boundary level VREF21, the voltage signal Vout2 that the output terminal OUT2 of electronic circuit 2 exports changes along with the change of electronic circuit 2 input voltage signal Vin2.When reference level VREF is set smaller than the lower level VREF22 of boundary level VREF21, another input end P25 of operational amplifier 21 be electrically connected the Part I 21 of main body circuit output terminal P22 and as the output terminal OUT2 of electronic circuit 2, during the input voltage signal Vin2 of electronic circuit 2 is less than lower level VREF22, the output terminal P22 bottoming level VREF22 of electronic circuit 2, during the input voltage signal Vin2 of electronic circuit 2 is greater than lower level VREF22, the voltage signal Vout2 that the output terminal P22 of electronic circuit 2 exports changes along with the change of electronic circuit 2 input voltage signal Vin2.
Fig. 4 is the circuit legend of the boundary level pattern of the electronic circuit of the first embodiment of the present invention.Here, the boundary level pattern of electronic circuit 2 refers to that reference level VREF is set as the pattern of boundary level VREF21.As shown in Figure 4, the Part I 21 of main body circuit is NMOS tube T2, its grid is the input end P21 of the Part I 21 of main body circuit, and its drain electrode is the feeder ear Vdd of the Part I 21 of main body circuit, and its source electrode is the output terminal P22 of the Part I 21 of main body circuit.The Part II 22 of main body circuit is constant current source Isource2.When reference level VREF is set as boundary level VREF21, Circuit tuning 23 is NMOS tube T3, its grid is described control end C21, and the output terminal P22 of the Part I 21 of its drain electrode electrical connection main body circuit, its source electrode exports the output voltage signal Vout2 of electronic circuit 2.
Again, when reference level VREF is set as boundary level VREF21, as the alternative that Circuit tuning 23 is NMOS tube T3, Circuit tuning 23 can also be triple-pole type transistor NPN (not shown), its base stage is control end C21, the output terminal P22 of the Part I 21 of its collector electrical connection main body circuit, its emitter exports the output voltage signal Vout2 of electronic circuit 2.
Below, with reference to Fig. 4, the electronic circuit 2 illustrating the first embodiment of the present invention suppresses output voltage signal Vout2 to be greater than principle and the process of boundary level VREF21.
During the voltage of the output terminal P22 of the Part I 21 of main body circuit is less than boundary level VREF21, NMOS tube T3 conducting, structure is followed, so the output voltage signal Vout2 of electronic circuit 2 changes along with the change of its input voltage signal Vin2 because NMOS tube T2 and constant current source Isource2 forms source.When the voltage rise of the output terminal P22 of the Part I 21 of main body circuit, the voltage of another input end P25 of operational amplifier A 21 also rises until close to the voltage of its another input end and boundary level VREF21 thereupon, the voltage that the output terminal P26 of operational amplifier A 21 exports declines along with the rising of the voltage of its input end P25, the output terminal P26 of operational amplifier A 21 is connected with the control gate C21 of NMOS tube T3 again, NMOS tube T3 is caused to enter saturation region, now, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 no longer follows the change of its input voltage vin 2 and changes, operational amplifier A 21 and NMOS tube T3 form negative feedback loop, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 is maintained at VREF21 and no longer rises.When the voltage of the output terminal P22 of the Part I 21 of main body circuit equals boundary level VREF21, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 is VREF21.
Fig. 5 is the circuit legend of the lower level pattern of the electronic circuit of the first embodiment of the present invention.Here, the lower level pattern of electronic circuit 2 refers to that reference level VREF is set as the pattern of lower level VREF22.As shown in Figure 5, the Part I 21 of main body circuit is NMOS tube T2, its grid is the input end P21 of the Part I 21 of main body circuit, and its drain electrode is the feeder ear Vdd of the Part I 21 of main body circuit, and its source electrode is the output terminal P22 of the Part I 21 of main body circuit.The Part II 22 of main body circuit is constant current source Isource2.When reference level VREF is set as lower level VREF22, Circuit tuning 23 is PMOS T4, and its grid is control end C21, and its drain electrode connects the other end P23 of the Part II 22 of main body circuit, and its source electrode exports the output voltage signal Vout2 of electronic circuit 2.
Again, when described reference level is set as described lower level, as the alternative that Circuit tuning 23 is PMOS T4, Circuit tuning 23 is triple-pole type transistor PNP (not shown), its base stage is control end C21, the other end P23 of the Part II 22 of its collector electrical connection main body circuit, its emitter exports the output voltage signal Vout2 of electronic circuit 2.
Below, with reference to Fig. 5, the electronic circuit 2 illustrating the first embodiment of the present invention suppresses output voltage signal Vout2 to be less than principle and the process of lower level VREF22.
During the voltage of the output terminal P22 of the Part I 21 of main body circuit is greater than lower level VREF22, PMOS T4 conducting, structure is followed, so the output voltage signal Vout2 of electronic circuit 2 changes along with the change of its input voltage signal Vin2 because NMOS tube T2 and constant current source Isource2 forms source.When the voltage drop of the output terminal P22 of the Part I 21 of main body circuit, the voltage of another input end P25 of operational amplifier A 21 also declines until close to the voltage of one input end P24 and lower level VREF22 thereupon, the voltage rise of the output terminal P26 output of operational amplifier A 21, the output terminal P26 of operational amplifier A 21 is connected with the control gate C21 of PMOS T4 again, PMOS T4 is made to enter saturation region, now, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 no longer follows the change of its input voltage vin 2 and changes, and operational amplifier A 21 and PMOS T4 form negative feedback loop, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 is maintained at VREF22 and no longer declines.When the voltage of the output terminal P22 of the Part I 21 of main body circuit equals lower level VREF22, the voltage Vout2 of the output terminal OUT2 of electronic circuit 2 is VREF22.
So, electronic circuit 2 according to a first embodiment of the present invention, its output voltage signal Vout2 can not be excessive, also can not be too small, only can change between boundary level VREF21 and lower level VREF22.
Fig. 6 is the structured flowchart of the electronic circuit of the second embodiment of the present invention.As shown in Figure 6, electronic circuit 3 comprises: the Part I 31 comprising the main body circuit of input end P31, output terminal P32 and feeder ear, the feeder ear of the Part I 31 of main body circuit connects the power supply Vdd of Part I 31 operation of provider's circuit, and the input end P31 of the Part I 31 of main body circuit accepts the input voltage signal Vin3 inputing to electronic circuit 3, comprise the Part II 32 of the main body circuit at two ends, one end ground connection GND, the first operational amplifier A 31, one input end P34 comprising two input ends P34, P35 and an output terminal P36 accesses upper limit reference level VREF31, comprise the first Circuit tuning 33 of three ends, its one end is control end C31, and the control end C31 of the first Circuit tuning 33 is electrically connected the output terminal P36 of the first operational amplifier A 31, its another two ends are electrically connected the output terminal OUT3 of the Part I 31 of main body circuit and another input end P35 of the first operational amplifier A 31 respectively, the second operational amplifier A 32, the one input end P37 access comprising two input ends P37, P38 and an output terminal P39 is less than the lower limit reference level VREF32 of upper limit reference level VREF31, comprise the second Circuit tuning 34 of three ends, its one end is control end C32, and the control end C32 of the second Circuit tuning 34 is electrically connected the output terminal P39 of the second operational amplifier A 32, its another two ends are electrically connected the other end P33 of the Part II 32 of main body circuit and another input end P38 of the second operational amplifier A 32 respectively, wherein, another input end P38 of another input end P35 of the first operational amplifier A 31 and the second operational amplifier A 32 is electrically connected and as the output terminal OUT3 of electronic circuit 3, during the input voltage signal Vin3 of electronic circuit 3 is less than upper limit reference level VREF31 and is greater than lower limit reference level VREF32, the voltage signal Vout3 that the output terminal OUT3 of electronic circuit 3 exports changes along with the input voltage signal Vin3 change of electronic circuit 3, during 3 input voltage signal Vin3 of electronic circuit are greater than upper limit reference level VREF31, the output terminal OUT3 of electronic circuit 3 exports upper limit reference level VREF31, during the input voltage vin 3 of electronic circuit 3 is less than lower limit reference level VREF32, the output terminal OUT3 bottoming reference level VREF32 of electronic circuit 3.
Fig. 7 is the circuit legend of the electronic circuit of the second embodiment of the present invention.As shown in Figure 7, the Part I 31 of main body circuit is NMOS tube T5, and its grid is the input end P31 of the Part I 31 of main body circuit, and its drain electrode is the feeder ear of the Part I 31 of main body circuit, and its source electrode is the output terminal P32 of the Part I 31 of main body circuit.The Part II 32 of main body circuit is constant current source Isource3.First Circuit tuning 33 is NMOS tube T6, and its grid is control end C31, and the output terminal P32 of the Part I 31 of its drain electrode electrical connection main body circuit, its source electrode exports the output voltage signal Vout3 of electronic circuit 3.Second Circuit tuning 34 is PMOS T7, and its grid is described control end C32, and its drain electrode connects the other end P33 of the Part II 32 of main body circuit, and its source electrode exports the output voltage signal Vout3 of electronic circuit 3.
Again, as the conversion example that the first Circuit tuning 33 is NMOS tube T6, first Circuit tuning 33 can also be triple-pole type transistor NPN (not shown), its base stage is control end C31, the output terminal P32 of the Part I 31 of its collector electrical connection main body circuit, its emitter exports the output voltage signal Vout3 of electronic circuit 3.
Again, as the alternative that the second Circuit tuning 34 is PMOS T7, second Circuit tuning 34 is triple-pole type transistor PNP (not shown), its base stage is control end C32, the other end P33 of the Part II 32 of its collector electrical connection main body circuit, its emitter exports the output voltage signal Vout3 of electronic circuit 3.
Below, composition graphs 7, illustrates the principle that the electronic circuit 3 of the second embodiment of the present invention suppresses its output voltage signal Vout3 excessive or too small and process.
During the voltage of the output terminal P32 of the Part I 31 of main body circuit is less than boundary level VREF31 and is greater than lower level VREF32, the equal conducting of NMOS tube T6 and PMOS T7, structure is followed, so the output voltage signal Vout3 of electronic circuit 3 changes along with the change of its input voltage signal Vin3 because NMOS tube T5 and constant current source Isource3 forms source.When the voltage rise of the output terminal P32 of the Part I 31 of main body circuit, the voltage of another input end P35 of operational amplifier A 31 also rises until close to the voltage of one input end P34 and boundary level VREF31 thereupon, the voltage drop of the output terminal P36 output of operational amplifier A 31, the output terminal P36 of operational amplifier A 31 is connected with the control gate C31 of NMOS tube T6 again, NMOS tube T6 is caused to enter saturation region, now, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 no longer follows the change of its input voltage vin 3 and changes, and operational amplifier A 31 and NMOS tube T6 form negative feedback loop, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 is maintained at VREF31 and no longer rises.During this period, the output terminal P39 of operational amplifier A 32 exports the control gate C32 of a low level to PMOS T7, to make PMOS T7 conducting.When the voltage of the output terminal P32 of the Part I 31 of main body circuit equals boundary level VREF31, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 is VREF31.When the voltage drop of the output terminal P32 of the Part I 31 of main body circuit, the voltage of another input end P38 of operational amplifier A 32 also declines until close to the voltage of one input end P37 and lower level VREF32 thereupon, the voltage rise of the output terminal P39 output of operational amplifier A 32, the output terminal P39 of operational amplifier A 32 is connected with the control gate C32 of PMOS T7 again, PMOS T7 is made to enter saturation region, now, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 no longer follows the change of its input voltage vin 3 and changes, and operational amplifier A 32 and PMOS T7 form negative feedback loop, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 is maintained at VREF32 and no longer declines.During this period, the output terminal P36 of operational amplifier A 31 exports the control gate C31 of a high level to NMOS tube T6, to make NMOS tube T6 conducting.When the voltage of the output terminal P32 of the Part I 31 of main body circuit equals lower level VREF32, the voltage Vout3 of the output terminal OUT3 of electronic circuit 3 is VREF32.
In addition, the Part I of main body circuit is here not limited to NMOS tube, can be replaced by other electron device or electronic circuit; The Part II of main body circuit is not limited to constant current source, can be replaced by other electron device or electronic circuit.
In addition, boundary level here refers to the pressure reduction at boundary level or boundary level plus-minus metal-oxide-semiconductor two ends.Here lower level refers to the pressure reduction at lower level or lower level plus-minus metal-oxide-semiconductor two ends.
In addition; for each device selected in embodiments of the present invention; those skilled in the art are based on the common practise of this area; NMOS tube can be replaced with by corresponding for PMOS; PMOS is replaced with by corresponding for NMOS tube; also other devices that can realize identical function can be selected to substitute each selected in the above-described embodiments device, or the connected mode between each device of corresponding change, these do not depart from protection scope of the present invention.
Although particular implementation of the present invention is described, this embodiment is just stated by the mode of example, is not intended to limit scope of the present invention.In fact, reference voltage generating circuit described herein can be implemented by other forms various; In addition, also can carry out the various omissions to reference voltage generating circuit described herein, substitute and change and do not deviate from spirit of the present invention.Attached claim and the object of equivalents thereof contain to fall into such various forms in scope and spirit of the present invention or amendment.
Claims (12)
1. an electronic circuit, is characterized in that, comprises:
Comprise the Part I of the main body circuit of input end, output terminal and feeder ear, the feeder ear of the Part I of described main body circuit connects the power supply of the Part I operation of provider's circuit, and the input end of the Part I of described main body circuit accepts the input voltage signal inputing to described electronic circuit;
Comprise the Part II of the main body circuit at two ends, one end ground connection;
Comprise the Circuit tuning of three ends, its one end is control end, and its another two ends are electrically connected the other end of the output terminal of the Part I of described main body circuit and the Part II of described main body circuit respectively;
Operational amplifier, one input end access reference level, its output terminal is electrically connected the control end of described Circuit tuning,
Wherein, when reference level is set as boundary level, another input end described of described operational amplifier be electrically connected the Part II of described main body circuit the other end and as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is greater than described boundary level, the output terminal of described electronic circuit exports described boundary level, during the input voltage signal of described electronic circuit is less than described boundary level, the voltage signal that the output terminal of described electronic circuit exports changes with the change of described electronic circuit input voltage signal
When reference level is set smaller than the lower level of described boundary level, another input end described of described operational amplifier be electrically connected the Part I of described main body circuit output terminal and as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is less than described lower level, the output terminal of described electronic circuit exports described lower level, during the input voltage signal of described electronic circuit is greater than described lower level, the voltage signal that the output terminal of described electronic circuit exports changes with the change of described electronic circuit input voltage signal.
2. electronic circuit as claimed in claim 1, it is characterized in that, the Part I of described main body circuit is NMOS tube, its grid is the input end of the Part I of described main body circuit, its drain electrode is the feeder ear of the Part I of described main body circuit, and its source electrode is the output terminal of the Part I of described main body circuit.
3. electronic circuit as claimed in claim 2, it is characterized in that, the Part II of described main body circuit is constant current source.
4. electronic circuit as claimed in claim 3, is characterized in that,
When described reference level is set as described boundary level, described Circuit tuning is NMOS tube, and its grid is described control end, the output terminal of the Part I of the described main body circuit of its drain electrode electrical connection, and its source electrode exports the output voltage signal of described electronic circuit; Or
When described reference level is set as described lower level, described Circuit tuning is PMOS, and its grid is described control end, and the other end of the Part II of the described main body circuit of its drain electrode electrical connection, its source electrode exports the output voltage signal of described electronic circuit.
5. electronic circuit as claimed in claim 3, is characterized in that,
When described reference level is set as described boundary level, described Circuit tuning is NPN triple-pole type transistor, its base stage is described control end, and its collector is electrically connected the output terminal of the Part I of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit; Or
When described reference level is set as described lower level, described Circuit tuning is PNP triple-pole type transistor, its base stage is described control end, and its collector is electrically connected the other end of the Part II of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
6. an electronic circuit, is characterized in that, comprises:
Comprise the Part I of the main body circuit of input end, output terminal and feeder ear, the feeder ear of the Part I of described main body circuit connects the power supply of the Part I operation of provider's circuit, and the input end of the Part I of described main body circuit accepts the input voltage signal inputing to described electronic circuit;
Comprise the Part II of the main body circuit at two ends, one end ground connection;
Comprise the first operational amplifier of two input ends and an output terminal, one input end access upper limit reference level;
Comprise the first Circuit tuning of three ends, its one end is control end, and the output terminal of described first operational amplifier of the control end of described first Circuit tuning electrical connection, its another two ends are electrically connected the output terminal of the Part I of described main body circuit and another input end of described first operational amplifier respectively;
Comprise the second operational amplifier of two input ends and an output terminal, one input end access is less than the lower limit reference level of described upper limit reference level;
Comprise the second Circuit tuning of three ends, its one end is control end, and the output terminal of described second operational amplifier of the control end of described second Circuit tuning electrical connection, its another two ends are electrically connected the other end of the Part II of described main body circuit and another input end of described second operational amplifier respectively;
Wherein, another input end electrical connection of another input end of described first operational amplifier and described second operational amplifier as the output terminal of described electronic circuit, during the input voltage signal of described electronic circuit is less than described upper limit reference level and is greater than described lower limit reference level, the voltage signal that the output terminal of described electronic circuit exports changes with the input voltage signal change of described electronic circuit, during the input voltage signal of described electronic circuit is greater than described upper limit reference level, the output terminal of described electronic circuit exports described upper limit reference level, during the input voltage of described electronic circuit is less than described lower limit reference level, the output terminal of described electronic circuit exports described lower limit reference level.
7. electronic circuit as claimed in claim 6, is characterized in that,
The Part I of described main body circuit is NMOS tube, and its grid is the input end of the Part I of described main body circuit, and its drain electrode is the feeder ear of the Part I of described main body circuit, and its source electrode is the output terminal of the Part I of described main body circuit.
8. electronic circuit as claimed in claim 7, it is characterized in that, the Part II of described main body circuit is constant current source.
9. electronic circuit as claimed in claim 8, it is characterized in that, described first Circuit tuning is NMOS tube, and its grid is described control end, the output terminal of the Part I of the described main body circuit of its drain electrode electrical connection, its source electrode exports the output voltage signal of described electronic circuit.
10. electronic circuit as claimed in claim 8, it is characterized in that, described first Circuit tuning is NPN triple-pole type transistor, its base stage is described control end, its collector is electrically connected the output terminal of the Part I of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
11. electronic circuits as claimed in claim 8 or 9, it is characterized in that, described second Circuit tuning is PMOS, and its grid is described control end, its drain electrode connects the other end of the Part II of described main body circuit, and its source electrode exports the output voltage signal of described electronic circuit.
12. electronic circuits as claimed in claim 8 or 9, it is characterized in that, described second Circuit tuning is PNP triple-pole type transistor, its base stage is described control end, its collector is electrically connected the other end of the Part II of described main body circuit, and its emitter exports the output voltage signal of described electronic circuit.
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| CN201210053972.8A CN103294089B (en) | 2012-03-02 | 2012-03-02 | Electronic circuit |
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| CN201210053972.8A CN103294089B (en) | 2012-03-02 | 2012-03-02 | Electronic circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3151423A1 (en) * | 2015-09-30 | 2017-04-05 | MediaTek Inc. | Input stage of chip and method for controlling source driver of chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7304729B2 (en) * | 2019-04-12 | 2023-07-07 | ローム株式会社 | Power supply circuit, power supply device and vehicle |
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| TWI252967B (en) * | 2004-07-19 | 2006-04-11 | Richtek Techohnology Corp | Output voltage overload suppression circuit applied in voltage regulator |
| TWI266166B (en) * | 2004-12-16 | 2006-11-11 | Realtek Semiconductor Corp | Source follower and stabilizing current feedback circuit thereof |
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| CN1448819A (en) * | 2002-03-18 | 2003-10-15 | 英特塞尔美国公司 | DC-to-DC converter with fast override feedback control and associated methods |
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| CN103294089A (en) | 2013-09-11 |
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