CN103268758B - Display panel and driving circuit thereof and driving method - Google Patents
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- CN103268758B CN103268758B CN201210382312.4A CN201210382312A CN103268758B CN 103268758 B CN103268758 B CN 103268758B CN 201210382312 A CN201210382312 A CN 201210382312A CN 103268758 B CN103268758 B CN 103268758B
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000005669 field effect Effects 0.000 claims description 24
- 239000010409 thin film Substances 0.000 claims description 24
- 239000004973 liquid crystal related substance Substances 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims 1
- 238000004134 energy conservation Methods 0.000 abstract 6
- 238000010586 diagram Methods 0.000 description 13
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 11
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 11
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 7
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 7
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 6
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
The invention discloses a kind of display panel and driving circuit thereof and driving method, in order to save the drive circuit power consumption of display panel, avoid the wasting of resources.The driving circuit of a kind of display panel provided by the invention, comprise multiple shift register, this driving circuit also comprises at least one power saving unit, each power saving unit is provided with energy-conservation signal input part and two energy-conservation signal output parts, each energy-conservation signal output part is connected with the signal output terminal of a shift register, the energy-conservation signal that this power saving unit is received by energy-conservation signal input part, controls the signal output terminal short circuit of the shift register that signal output part energy-conservation with each is connected.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a display panel, and a driving circuit and a driving method thereof.
Background
Fig. 1 and fig. 2 are schematic diagrams of a single-side driving display panel and a double-side driving display panel in the prior art, respectively. Wherein AA is a display area, DEMUX is a multiplexer, and IC is an integrated circuit. The IC supplies signals to the DEMUX, which divides each of the received signals into a plurality of signals and supplies them to the display area AA.
Fig. 3 is a schematic diagram of a dual-side driving vertical shift register, in which each shift register of any side outputs a Gate (Gate) signal to a display panel for driving the display panel, and an output of a previous shift register of two adjacent shift registers of any side is simultaneously used as a chip select input signal of a next shift register. Specifically, the first shift register for outputting the gate signal G1 is respectively connected with a start chip select signal STV, a Reset signal Reset, a first clock signal CLK1 and a third clock signal CLK3, and the gate signal G1 output by the first shift register also serves as a chip select input signal of the third shift register. The third shift register is connected with a chip selection signal G1, a Reset signal Reset, a first clock signal CLK1 and a third clock signal CLK3, and outputs a gate signal G3 as a chip selection input signal of the next shift register, and so on; the circuit connection and the driving on the other side are the same. The timing relationship of the signals is shown in fig. 4, wherein POL is a polarity signal provided to the data lines of the display panel, and is toggled during each clock cycle to provide data signals of opposite polarity accordingly.
Therefore, when the display panel is in the power consumption measuring mode, or the checkerboard mode, or the full black or full white power saving mode, or the sleep mode, the display panel only needs to present the data signal transmission state of line inversion or dot inversion, but the driving circuit in the prior art still needs to provide signals of CLK1 and CLK3 at the same time, and the data lines provided to the display panel are switched back and forth between high and low levels, so the power consumption of the driving circuit in the prior art is very large.
Disclosure of Invention
The embodiment of the invention provides a display panel, a driving circuit and a driving method thereof, which are used for saving the power consumption of the driving circuit of the display panel and avoiding resource waste.
The driving circuit of the display panel provided by the embodiment of the invention comprises a plurality of shift registers and at least one energy-saving unit, wherein each energy-saving unit is provided with an energy-saving signal input end and two energy-saving signal output ends, each energy-saving signal output end is connected with a grid signal output end of one shift register, and the energy-saving unit controls the grid signal output end of the shift register connected with each energy-saving signal output end to be in short circuit through an energy-saving signal received by the energy-saving signal input end.
Preferably, the energy saving unit includes: a CMOS composed of a P-type thin film field effect transistor TFT and an N-type thin film field effect transistor TFT, and an inverter;
the drain electrode of the N-type thin film field effect transistor TFT is connected with the source electrode of the P-type thin film field effect transistor TFT and is used as a first energy-saving signal output end of the energy-saving unit; the source level of the N-type thin film field effect transistor TFT is connected with the drain electrode of the P-type thin film field effect transistor TFT and is used as a second energy-saving signal output end of the energy-saving unit;
the grid electrode of the P-type thin film field effect transistor TFT is connected with the output end of the phase inverter;
and the grid electrode of the N-type thin film field effect transistor TFT is connected with the input end of the phase inverter and is used as the energy-saving signal input end of the energy-saving unit.
Preferably, the driving circuit further includes:
and an integrated circuit IC providing a power saving signal to the power saving unit.
Preferably, the integrated circuit IC includes at least one energy-saving signal generating unit for generating energy-saving signals, each energy-saving unit corresponds to one energy-saving signal generating unit, and the energy-saving signal generating unit outputs the generated energy-saving signal to an energy-saving signal input terminal of the corresponding energy-saving unit.
Preferably, the driving circuit is a dual-side driving circuit.
Preferably, at least one energy-saving unit is disposed on the driving circuit of each side.
Preferably, the two energy-saving signal output ends of each energy-saving unit are respectively connected to the gate signal output ends of two adjacent shift registers.
The display panel provided by the embodiment of the invention comprises a liquid crystal panel and the driving circuit.
The driving method of the driving circuit provided by the embodiment of the invention comprises the following steps:
when the energy-saving condition is not met, the grid signal output ends of a plurality of shift registers connected with the energy-saving unit respectively output independent signals;
when the energy-saving condition is met, the driving circuit generates an energy-saving signal through at least one energy-saving signal generating unit and outputs the energy-saving signal to the energy-saving unit corresponding to the energy-saving signal generating unit, so that the grid signal output end of the shift register connected with the energy-saving signal output end of each energy-saving unit receiving the energy-saving signal is short-circuited.
Preferably, the driving circuit is a dual-side driving circuit.
Preferably, the driving circuit further includes an integrated circuit IC, and the driving circuit provides a power saving signal to the power saving unit through the integrated circuit IC.
Preferably, in the power saving mode, the IC outputs a power saving signal to an input terminal of a power saving unit on at least one side of the driving circuit.
Preferably, the method further comprises:
when the energy-saving signal is started, the first clock signal on the driving circuit of at least one side is controlled to be turned off or switched to a low potential through the IC; or,
when the energy-saving signal is turned on, the second clock signal on the driving circuit of at least one side is controlled by the IC to be turned off or switched to a low potential.
Preferably, the energy saving condition comprises one or a combination of the following conditions:
receiving an external signal, and entering a power saving mode;
and reaching the preset timing time for outputting the energy-saving signal.
Preferably, the driving circuit further comprises a data driving unit,
when the energy-saving condition is not met, the data signal sent to the display panel by the data driving unit is inverted for multiple times within one frame time;
when the energy-saving condition is satisfied, the data signal sent to the display panel by the data driving unit is only turned over once within one frame time.
The driving circuit of the display panel provided by the embodiment of the invention comprises a plurality of shift registers and at least one energy-saving unit, wherein each energy-saving unit is provided with an energy-saving signal input end and two energy-saving signal output ends, each energy-saving signal output end is connected with a grid signal output end of one shift register, and the energy-saving unit controls the grid signal output end of the shift register connected with each energy-saving signal output end to be in short circuit through an energy-saving signal received by the energy-saving signal input end. Therefore, power consumption of 1/2 vertical shift register and 1/2 data line power consumption can be saved in a measurement power consumption mode, a checkerboard mode, a full black or full white power saving mode, or a sleep mode without adding an additional space circuit.
Drawings
FIG. 1 is a schematic diagram of a conventional single-side-driven display panel;
FIG. 2 is a schematic diagram of a conventional dual-edge-driven display panel;
FIG. 3 is a circuit diagram of a conventional dual-side driving vertical shift register;
FIG. 4 is a timing diagram of a conventional dual-side driving vertical shift register;
FIG. 5 is a schematic diagram of a dual-side driving vertical shift register according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a dual-side driving vertical shift register according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a connection of a dual-side driving vertical shift register display panel according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a signal control flow according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a signal control flow according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a display panel, a driving circuit and a driving method thereof, which are used for saving the power consumption of the driving circuit of the display panel and avoiding resource waste.
The technical scheme provided by the embodiment of the invention can achieve the effect of saving electricity in black and white pictures, pictures for measuring power consumption and the like. Referring to fig. 5, in the embodiment of the present invention, a Complementary Metal Oxide Semiconductor (CMOS) is added to a driving circuit of a display panel, and a Power Saving (PS) signal is added, so that gate signals of G1 and G3 … … are connected when the PS signal is present, and gate signals of G2 and G G4. are connected, so as to achieve an effect of Saving Power consumption.
Fig. 6 shows a timing relationship of signals of a driving circuit of a display panel according to an embodiment of the present invention.
The power of the whole display panel is:
P=1/2fCV2
where f is a high/low signal switching Frequency (Frequency) when the panel operates, C is a Capacitance (Capacitance) inside the panel, and V is a high/low Voltage difference (application Voltage) of a control signal applied to the panel. The values of C and V are preset according to the characteristics of each display panel, and when the frequency f becomes 1/2, the power consumption of the whole panel is reduced to 1/2.
Specifically, referring to fig. 5, the driving circuit of a display panel according to an embodiment of the present invention, taking a dual-side driving display panel as an example, includes a plurality of shift registers, and at least one energy saving unit (i.e., a portion shown in a dashed line frame in fig. 5), where each energy saving unit is provided with an energy saving signal input end (i.e., an end for inputting a PS signal) and two energy saving signal output ends, each energy saving signal output end is connected to a gate signal output end of one shift register, and the energy saving unit controls, through an energy saving signal received by the energy saving signal input end, a gate signal output end of the shift register connected to each energy saving signal output end to be short-circuited (i.e., connected).
Preferably, the energy saving unit includes: a CMOS composed of a P-type thin film field effect transistor TFT and an N-type thin film field effect transistor TFT, and an inverter;
the drain electrode of the N-type thin film field effect transistor TFT is connected with the source electrode of the P-type thin film field effect transistor TFT and is used as a first energy-saving signal output end of the energy-saving unit; the source level of the N-type thin film field effect transistor TFT is connected with the drain electrode of the P-type thin film field effect transistor TFT and is used as a second energy-saving signal output end of the energy-saving unit; the grid electrode of the P-type thin film field effect transistor TFT is connected with the output end of the phase inverter; and the grid electrode of the N-type thin film field effect transistor TFT is connected with the input end of the phase inverter and is used as the energy-saving signal input end of the energy-saving unit.
In this embodiment, when the power saving signal is turned on, the gate signal output terminal of the shift register connected to the power saving signal output terminal of each power saving unit receiving the power saving signal (PS signal) can be short-circuited through at least one of the power saving units, that is, when the driving circuit includes one power saving unit, for example, the output terminal outputting the G1 signal and the output terminal outputting the G3 signal are short-circuited; or when the driving circuit comprises two power saving units, the output terminal outputting the G2 signal and the output terminal outputting the G4 signal are preferably also short-circuited at the same time. Under the condition of omitting any one clock signal of CLK1 or CLK3 (when the driving circuit only comprises one energy-saving unit) or further simultaneously omitting any one clock signal of CLK2 or CLK4 (when the driving circuit comprises two energy-saving units), the gate signal output ends of the short-circuited shift register (namely the output end for outputting the G1 signal and the output end for outputting the G3 signal, or further comprising the output end for outputting the G2 signal and the output end for outputting the G4 signal) can still normally output signals for detection, so that the working frequency f of the panel can be changed into 1/2 under the condition that the holding circuit normally works, the power P of the display panel is reduced to the original 1/2, and the energy-saving effect can be achieved.
In this embodiment, the bilateral driving circuit is only exemplified to include one or two energy-saving units, and actually, the driving circuit of the present invention includes at least one energy-saving unit, which should be understood to include one or more energy-saving units, such as two, three, or more energy-saving units.
As a variation of this embodiment, the driving circuit further includes: and an integrated circuit IC providing a power saving signal to the power saving unit.
As shown in fig. 7, the integrated circuit IC includes at least one energy-saving signal generating unit for generating energy-saving signals, each energy-saving unit corresponds to one energy-saving signal generating unit, and the energy-saving signal generating unit outputs the generated energy-saving signal to an energy-saving signal input terminal of the corresponding energy-saving unit.
It should be noted that the driving circuits described in the above embodiments are all exemplified by a dual-edge driving circuit. In a variation of this embodiment, the driving circuit may also be a single-sided driving circuit.
Preferably, for the dual-side driving circuit, at least one energy-saving unit is disposed on the driving circuit of each side.
Preferably, the two energy-saving signal output ends of each energy-saving unit are respectively connected to the gate signal output ends of two adjacent shift registers.
The display panel provided by the embodiment of the invention comprises a liquid crystal panel and the driving circuit in any one of the embodiments. The display panel can reduce the inversion frequency of the polarity signal POL on the data line of the driving circuit under the action of the energy-saving signal, and simultaneously, the use of a clock signal on any side is also saved, thereby reducing the power consumption of the driving circuit and the display panel.
Correspondingly, referring to fig. 8, an embodiment of the present invention further provides a driving method of the driving circuit, including:
s101, when the energy-saving condition is not met, grid signal output ends of a plurality of shift registers connected with the energy-saving unit respectively output independent signals;
and S102, when the energy-saving condition is met, the driving circuit generates an energy-saving signal through at least one energy-saving signal generating unit and outputs the energy-saving signal to an energy-saving unit corresponding to the energy-saving signal generating unit, so that a grid signal output end of a shift register connected with an energy-saving signal output end of each energy-saving unit receiving the energy-saving signal is short-circuited.
When the display panel works normally, the power of the whole display panel is as follows: p =1/2fCV2；
When the energy-saving signal is turned on, the gate signal output end of the shift register connected with the energy-saving signal output end of each energy-saving unit receiving the energy-saving signal is short-circuited through the energy-saving unit, and under the condition that any one clock signal of CLK1 or CLK3 is omitted, the gate signal output end of the short-circuited shift register can still normally output a signal for detection, so that the working frequency f of the panel can be changed into the original 1/2 under the condition that the circuit normally works, the power P of the display panel is reduced to the original 1/2, and therefore, when the energy-saving condition is met, the energy-saving effect can be achieved.
Preferably, the driving circuit is a bilateral driving circuit, and of course, when necessary, the driving circuit may also be a unilateral driving circuit, and the energy saving effect can be realized only by driving the driving circuit on any side.
In another embodiment, the driving circuit further includes an integrated circuit IC, and the driving circuit provides the power saving signal to the power saving unit through the integrated circuit IC.
Preferably, in the power saving mode, the IC outputs a power saving signal to an input terminal of a power saving unit on at least one side of the driving circuit. That is, the invention can save energy for one side or two sides, that is, the PS signals can be sent simultaneously, or the PS signals can be sent separately for the left and the right sides; the PS signals can be sent separately on one side independently, or can be sent to both sides simultaneously.
Preferably, the driving method further includes:
when the energy-saving signal is started, the first clock signal on the driving circuit of at least one side is controlled to be turned off or switched to a low potential through the IC; or,
when the energy-saving signal is turned on, the second clock signal on the driving circuit of at least one side is controlled by the IC to be turned off or switched to a low potential.
Referring to fig. 4 and 6, fig. 4 is a timing diagram of a dual-side driving vertical shift register in the prior art, and fig. 6 is a timing diagram of a dual-side driving vertical shift register according to an embodiment of the present invention. Comparing CLK3 and CLK4 in fig. 4 and 6, it can be seen that the present invention saves the use of clock signals, thereby reducing the power consumption of the driving circuit.
The energy-saving condition comprises one or a combination of the following conditions:
the first condition is as follows: and entering a power saving mode when receiving an external signal. The external signal may be an external key or may satisfy a specific preset condition. For example, when the set time point is reached or a key is generated, the driving circuit receives the energy-saving signal and enters the power-saving mode.
And a second condition: and reaching the preset timing time for outputting the energy-saving signal.
The timing duration is preferably 20 s-5 mins, and other durations may also be set according to specific needs, which is not limited herein.
In another embodiment of the present invention, the driving circuit further includes a data driving unit, and the driving method further includes:
when the energy-saving condition is not met, the data signal sent to the display panel by the data driving unit is inverted for multiple times within one frame time;
when the energy-saving condition is satisfied, the data signal sent to the display panel by the data driving unit is only turned over once within one frame time.
Specifically, referring to fig. 9 and 6, the step of the embodiment of the present invention, when the power saving condition is satisfied, the data signal sent by the data driving unit to the display panel is inverted only once within one frame time includes:
determining that the display device enters a power measurement mode, a checkerboard mode, a full black or full white power saving mode or a sleep mode;
turning on the PS signal;
turning off the third clock signal CLK3, preferably simultaneously with turning off the fourth clock signal CLK4, thereby saving 1/2 power consumption for the driving circuits of the display panel;
when the second clock signal is turned on, the polarity of the polarity signal POL on the data line is inverted, thereby further saving 1/2 power consumption for the display panel.
It should be noted that, in the embodiment, when clock signals are omitted, the third clock signal CLK3 is turned off for example, but those skilled in the art will understand that the method is not limited to the embodiment as long as one of the first clock signal CLK1 and the third clock signal CLK3 is turned off. Similarly, the fourth clock signal CLK4 is turned off in the present embodiment, but those skilled in the art will understand that the present embodiment is not limited to the method as long as one of the second clock signal CLK2 or the fourth clock signal CLK4 is turned off. In addition, in the present embodiment, it is preferable to turn off the third clock signal CLK3 and the fourth clock signal CLK4 at the same time, but those skilled in the art can also turn off only one side of the clock signals, that is, only the third clock signal CLK3 (or the first clock signal CLK 1) or only the fourth clock signal CLK4 (or the second clock signal CLK 2) according to different working requirements.
In summary, the technical solution provided in the embodiments of the present invention can save 1/2 the power consumption of the driving circuit including the vertical shift register and 1/2 the power consumption of the display panel including the data lines in the power consumption measuring mode, the checkerboard mode, the full black or full white power saving mode, or the sleep mode without adding extra space as a circuit. Also, the present invention may preferably be used in combination with a dynamic Backlight Control (CABC).
The above embodiments of the present invention are designed only for the driving circuit of the vertical shift register, do not affect other structures of the display panel, and can be applied to the driving control of various known existing display devices such as a low temperature polysilicon liquid crystal display, and should not be limited in the embodiments of the present invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A driving circuit of a display panel includes a plurality of shift registers, characterized in that: the driving circuit also comprises at least one energy-saving unit, each energy-saving unit is provided with an energy-saving signal input end and two energy-saving signal output ends, each energy-saving signal output end is connected with a grid signal output end of a shift register, and the energy-saving unit controls the grid signal output end of the shift register connected with each energy-saving signal output end to be short-circuited through an energy-saving signal received by the energy-saving signal input end;
the energy saving unit includes: a CMOS composed of a P-type thin film field effect transistor TFT and an N-type thin film field effect transistor TFT, and an inverter; the drain electrode of the N-type thin film field effect transistor TFT is connected with the source electrode of the P-type thin film field effect transistor TFT and is used as a first energy-saving signal output end of the energy-saving unit; the source level of the N-type thin film field effect transistor TFT is connected with the drain electrode of the P-type thin film field effect transistor TFT and is used as a second energy-saving signal output end of the energy-saving unit; the grid electrode of the P-type thin film field effect transistor TFT is connected with the output end of the phase inverter; and the grid electrode of the N-type thin film field effect transistor TFT is connected with the input end of the phase inverter and is used as the energy-saving signal input end of the energy-saving unit.
2. The driving circuit according to claim 1, further comprising:
and an integrated circuit IC providing a power saving signal to the power saving unit.
3. The driving circuit according to claim 2, wherein the integrated circuit IC comprises at least one energy-saving signal generating unit for generating energy-saving signals, each energy-saving unit corresponds to one energy-saving signal generating unit, and the energy-saving signal generating unit outputs the generated energy-saving signal to an energy-saving signal input terminal of the corresponding energy-saving unit.
4. The driver circuit of claim 3, wherein the driver circuit is a dual edge driver circuit.
5. The driving circuit according to claim 4, wherein at least one of the power saving units is provided on the driving circuit of each side.
6. The driving circuit according to claim 1, wherein the two power saving signal output terminals of each power saving unit are respectively connected to the gate signal output terminals of two adjacent shift registers.
7. A display panel comprising a liquid crystal panel and the driver circuit of any one of claims 1 to 6.
8. A method of driving a driver circuit according to claim 1, the method comprising:
when the energy-saving condition is not met, the grid signal output ends of a plurality of shift registers connected with the energy-saving unit respectively output independent signals;
when the energy-saving condition is met, the driving circuit generates an energy-saving signal through at least one energy-saving signal generating unit and outputs the energy-saving signal to the energy-saving unit corresponding to the energy-saving signal generating unit, so that the grid signal output end of the shift register connected with the energy-saving signal output end of each energy-saving unit receiving the energy-saving signal is short-circuited;
wherein the energy-saving condition comprises one or a combination of the following conditions: receiving an external signal, and entering a power saving mode; and reaching the preset timing time for outputting the energy-saving signal.
9. The driving method according to claim 8, wherein the driving circuit is a dual-edge driving circuit.
10. The driving method according to claim 9, wherein the driving circuit further includes an integrated circuit IC, and the driving circuit supplies a power saving signal to the power saving unit through the integrated circuit IC.
11. The driving method according to claim 10, wherein in the power saving mode, the IC outputs a power saving signal to a power saving unit input terminal on at least one side of the driving circuit.
12. The driving method according to claim 10, characterized by further comprising:
when the energy-saving signal is started, the first clock signal on the driving circuit of at least one side is controlled to be turned off or switched to a low potential through the IC; or,
when the energy-saving signal is turned on, the second clock signal on the driving circuit of at least one side is controlled by the IC to be turned off or switched to a low potential.
13. The driving method according to claim 8, wherein the driving circuit further includes a data driving unit,
when the energy-saving condition is not met, the data signal sent to the display panel by the data driving unit is inverted for multiple times within one frame time;
when the energy-saving condition is satisfied, the data signal sent to the display panel by the data driving unit is only turned over once within one frame time.
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| CN101847377A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Gate drive device of liquid crystal display |
| CN102087827A (en) * | 2010-05-11 | 2011-06-08 | 友达光电股份有限公司 | Shift register |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103268758A (en) | 2013-08-28 |
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