CN103268293A - Management method of multichannel multi-speed data collection system memory - Google Patents

Management method of multichannel multi-speed data collection system memory Download PDF

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CN103268293A
CN103268293A CN2013102348518A CN201310234851A CN103268293A CN 103268293 A CN103268293 A CN 103268293A CN 2013102348518 A CN2013102348518 A CN 2013102348518A CN 201310234851 A CN201310234851 A CN 201310234851A CN 103268293 A CN103268293 A CN 103268293A
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speed group
traversal
speed
data
group
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CN103268293B (en
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梁燕
段文亮
何林
舒明华
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CHONGQING CHONGYOU HUICE ELECTRONIC TECHNOLOGY RESEARCH INSTITUTE Co.,Ltd.
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Chongqing Zhongyou Huice Communication Technology Co Ltd
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Abstract

In order to solve the problems of large necessary high speed cache region and waste or complicated distribution process and dispatch management of the high speed cache region of the management method of multichannel multi-speed data collection system memory in the prior art, the invention provides a management method of a multichannel multi-speed data collection system memory. A speed group is divided in a data speed multiplication manner, each data channel is uniformly distributed with a high speed cache region of which volume is bit number written by one abrupt writing of a main storage region, the traversal frequency of a high speed group is higher than that of a low speed group, the relation between the high speed cache space dimension and the data reading frequency is considered, and the core concept is to exchange time with space. The management method of the multichannel multi-speed data collection system memory disclosed by the invention has the beneficial effects of greatly reducing the volume of the storage space of the high speed cache region, and meanwhile, improving the writing efficiency from the high speed cache region to the main storage region.

Description

Hyperchannel multi-rate data acquisition system storage management method
Technical field
The present invention relates to the administrative skill of multichannel data acquisition system storer, specially refer to hyperchannel multi-rate data acquisition system storage management method.
Background technology
Usually, in data acquisition system (DAS), usually can relate to the data acquisition of a plurality of data channel, and the data rate of each data channel is inconsistent even differ greatly.For example, channelizing optical transport network CPOS(Channelized Packet over SONET/SDH) A and Abis optical interface being carried out signaling data when gathering, each high-level data link control procedure HDLC(High-Level Data Link Control in the acquisition system) data rate of passage just changes in the 8Kbps scope at 2.048Mbps.Demand for the data acquisition that adapts to the data with different rate passage, usually adopt the memory management pattern in cache memory section+main storage area, the physical medium that is the main storage area is double data rate random access memory DDR SDRAM, be characterized in being fit to read and write with long burst-length, namely a plurality of bytes of write-once are more efficient.And the purpose of cache memory section is set, and run up to a suitable length for the sporadic data fragment with each data channel exactly, dump to again among the DDR SDRAM in main storage area.Obviously, the distribution of cache memory section or management directly have influence on operational efficiency and the speed of data acquisition system (DAS).Prior art hyperchannel multi-rate data acquisition system storage management method adopts two kinds of way to manages to distribute or the management of cache district, a kind of mode is the equal-sized cache memory section of different rates passage mean allocation, do not consider the difference on each data channel speed, unified with flank speed passage buffer storage demand assignment cache memory space.Though this mode realizes that simply the cache memory space that needs is too big, the cost of realization is higher, and is low rate channel allocation and the onesize buffer area of two-forty passage, can cause unnecessary waste.Another kind of mode is according to the difference of each HDLC channel rate, the cache memory section of fixing that does not wait for its allocated size.The spatial cache that speed channel allocation faster is bigger, the less spatial cache of channel allocation that speed is less.Though this mode has been avoided the waste in cache memory section space, too complicated in assigning process and the management and running of cache memory section, and still need bigger cache memory section with the buffer memory demand of adaptive various speed.Obviously, it is big and have a waste that prior art hyperchannel multi-rate data acquisition system storage management method exists required cache memory section space, perhaps the assigning process of cache memory section and management and running problem such as complexity too.
Summary of the invention
In order to solve the big and existence waste in required cache memory section space that prior art hyperchannel multi-rate data acquisition system storage management method exists, the perhaps assigning process of cache memory section and management and running problem such as complexity too, the present invention proposes a kind of hyperchannel multi-rate data acquisition system storage management method.Hyperchannel multi-rate data acquisition system storage management method of the present invention may further comprise the steps:
S1, according to data rate order from low to high, in the mode of data rate multiplication all data channel that system receives are divided into the speed group, 1/8 the data channel that comprises in the minimum speed limit group that system receives; Wherein, speed group quantity kWith coefficient hThere is following relation:
Figure 2013102348518100002DEST_PATH_IMAGE002
（1）
In the formula, hBe coefficient, its value is 2 integral number power; kBe speed group quantity;
S2, set being numbered of speed group from low to high according to data rate , the data channel quantity in the corresponding speed group is respectively
S3, for each data channel partition capacity be
Figure 2013102348518100002DEST_PATH_IMAGE008
Cache memory section,
Figure 2013102348518100002DEST_PATH_IMAGE010
Value be the bit number that the secondary burst in main storage area writes, and each data channel Be worth all identical;
S4, setting-up time cycle, set the service time slot , wherein, the service time slot
Figure 2013102348518100002DEST_PATH_IMAGE014
Duration for being that data in the high-speed buffer of C are written to the time required in the main storage area with capacity; Time cycle
Figure 2013102348518100002DEST_PATH_IMAGE016
With the service time slot
Figure 785591DEST_PATH_IMAGE012
Between have a following relation:
Figure 2013102348518100002DEST_PATH_IMAGE018
（2）
In the formula, NBe systematic parameter, its value is
Figure 2013102348518100002DEST_PATH_IMAGE020
(3)
Wherein,
Figure 939229DEST_PATH_IMAGE006
Be respectively and be numbered
Figure 334439DEST_PATH_IMAGE004
Data channel quantity in the speed group;
Simultaneously, also satisfy following formula:
（4）
In the formula,
Figure 24177DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 2013102348518100002DEST_PATH_IMAGE024
Figure 2013102348518100002DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power;
Figure 2013102348518100002DEST_PATH_IMAGE028
For being numbered
Figure 2013102348518100002DEST_PATH_IMAGE030
The maximum rate of speed group, unit is
Figure 2013102348518100002DEST_PATH_IMAGE032
Be systematic parameter, its value is
Figure 116415DEST_PATH_IMAGE020
Figure 695033DEST_PATH_IMAGE014
Be the service time slot, unit is
Figure 2013102348518100002DEST_PATH_IMAGE036
Transform (4):
Figure 2013102348518100002DEST_PATH_IMAGE038
（5）
Convolution (3) and formula (5):
Figure 2013102348518100002DEST_PATH_IMAGE040
In the formula,
Figure 831616DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 815009DEST_PATH_IMAGE024
Figure 808373DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power,
Figure 625019DEST_PATH_IMAGE002
, kBe speed group quantity;
For being numbered
Figure 175080DEST_PATH_IMAGE030
The maximum rate of speed group, unit is
Figure 698465DEST_PATH_IMAGE032
Figure 190627DEST_PATH_IMAGE034
Be systematic parameter, its value is
Figure 18960DEST_PATH_IMAGE014
Be the service time slot, unit is
Figure 724748DEST_PATH_IMAGE036
Figure 872964DEST_PATH_IMAGE006
Be respectively and be numbered
Figure 601885DEST_PATH_IMAGE004
The quantity of data channel in the speed group;
S5, according to the data channel that begins with the following frequency to travel through in each speed group, described traversal refers to the data in this data channel cache memory section are written in the main storage area:
The speed group
Figure 743016DEST_PATH_IMAGE030
, every
Figure 2013102348518100002DEST_PATH_IMAGE042
Individual time cycle traversal once;
The speed group
Figure 2013102348518100002DEST_PATH_IMAGE044
, every
Figure 2013102348518100002DEST_PATH_IMAGE046
Individual time cycle traversal once;
The speed group
Figure 2013102348518100002DEST_PATH_IMAGE048
, every Individual time cycle traversal once;
……
The speed group , every
Figure 2013102348518100002DEST_PATH_IMAGE054
Individual time cycle traversal once;
The speed group
Figure 2013102348518100002DEST_PATH_IMAGE056
, every
Figure 2013102348518100002DEST_PATH_IMAGE058
Individual time cycle traversal once;
In the formula,
Figure 674282DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power,
Figure 445929DEST_PATH_IMAGE002
, kBe speed group quantity,
Figure 2013102348518100002DEST_PATH_IMAGE060
Be the time cycle;
Wherein, the higher speed group of data rate has higher priority, and the speed group that data rate is lower has lower priority; The traversal cycle that each speed group begins according to the above-mentioned setting frequency is called this speed group intrinsic traversal cycle;
S6, each speed group begin to repeat traversal according to its intrinsic traversal cycle from higher prior stage speed group; In the ergodic process of lower priority speed group, if begun the intrinsic traversal cycle of a higher prior stage speed group, at this moment, lower priority speed group ergodic process will be interrupted, then begin to travel through higher prior stage speed group, after higher prior stage speed group traversal finishes, continue the ergodic process of interrupted lower priority speed group again;
S7, when end data is gathered, according to speed group priority orders, travel through all speed groups.
The useful technique effect of hyperchannel multi-rate data acquisition system storage management method of the present invention is the capacity that has significantly reduced the high-speed buffer storage space, simultaneously, improved data and write efficient from the high-speed buffer to the main storage area.
Description of drawings
Accompanying drawing 1 is hyperchannel multi-rate data acquisition system storage management method process flow diagram of the present invention.
Following the drawings and specific embodiments are described further hyperchannel multi-rate data acquisition system storage management method of the present invention.
Embodiment
Accompanying drawing 1 is hyperchannel multi-rate data acquisition system storage management method process flow diagram of the present invention.As seen from the figure, hyperchannel multi-rate data acquisition system storage management method of the present invention may further comprise the steps:
S1, according to data rate order from low to high, in the mode of data rate multiplication all data channel that system receives are divided into the speed group, 1/8 the data channel that comprises in the minimum speed limit group that system receives; Wherein, speed group quantity kWith coefficient hThere is following relation:
Figure 773399DEST_PATH_IMAGE002
（1）
In the formula, hBe coefficient, its value is 2 integral number power; kBe speed group quantity;
S2, set being numbered of speed group from low to high according to data rate
Figure 655904DEST_PATH_IMAGE004
, the data channel quantity in the corresponding speed group is respectively
S3, for each data channel partition capacity be
Figure 826303DEST_PATH_IMAGE008
Cache memory section,
Figure 264237DEST_PATH_IMAGE010
Value be the bit number that the secondary burst in main storage area writes, and each data channel
Figure 747171DEST_PATH_IMAGE008
Be worth all identical;
S4, setting-up time cycle , set the service time slot , wherein, the service time slot
Figure 632322DEST_PATH_IMAGE014
Duration for being that data in the high-speed buffer of C are written to the time required in the main storage area with capacity; Time cycle
Figure 669680DEST_PATH_IMAGE016
With the service time slot
Figure 793493DEST_PATH_IMAGE012
Between have a following relation:
Figure 77844DEST_PATH_IMAGE018
（2）
In the formula, NBe systematic parameter, its value is
Figure 799026DEST_PATH_IMAGE020
(3)
Wherein,
Figure 889342DEST_PATH_IMAGE006
Be respectively and be numbered
Figure 70924DEST_PATH_IMAGE004
Data channel quantity in the speed group;
Simultaneously, also satisfy following formula:
Figure 73646DEST_PATH_IMAGE022
（4）
In the formula,
Figure 35786DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 601897DEST_PATH_IMAGE024
Figure 215150DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power;
Figure 638041DEST_PATH_IMAGE028
For being numbered The maximum rate of speed group, unit is
Figure 208010DEST_PATH_IMAGE032
Be systematic parameter, its value is
Figure 957978DEST_PATH_IMAGE020
Figure 881328DEST_PATH_IMAGE014
Be the service time slot, unit is
Figure 117137DEST_PATH_IMAGE036
Transform (4):
（5）
Convolution (3) and formula (5):
Figure 908824DEST_PATH_IMAGE040
In the formula,
Figure 67272DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 90461DEST_PATH_IMAGE024
Figure 955649DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power,
Figure 156823DEST_PATH_IMAGE002
, kBe speed group quantity;
Figure 553300DEST_PATH_IMAGE028
For being numbered The maximum rate of speed group, unit is
Figure 850607DEST_PATH_IMAGE032
Be systematic parameter, its value is
Figure 655468DEST_PATH_IMAGE014
Be the service time slot, unit is
Figure 308297DEST_PATH_IMAGE036
Figure 788957DEST_PATH_IMAGE006
Be respectively and be numbered
Figure 143715DEST_PATH_IMAGE004
The quantity of data channel in the speed group;
S5, according to the data channel that begins with the following frequency to travel through in each speed group, described traversal refers to the data in this data channel cache memory section are written in the main storage area:
The speed group
Figure 312397DEST_PATH_IMAGE030
, every
Figure 69000DEST_PATH_IMAGE042
Individual time cycle traversal once;
The speed group , every
Figure 578927DEST_PATH_IMAGE046
Individual time cycle traversal once;
The speed group , every Individual time cycle traversal once;
……
The speed group
Figure 987802DEST_PATH_IMAGE052
, every
Figure 317153DEST_PATH_IMAGE054
Individual time cycle traversal once;
The speed group
Figure 516053DEST_PATH_IMAGE056
, every
Figure 732402DEST_PATH_IMAGE058
Individual time cycle traversal once;
In the formula,
Figure 53661DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power,
Figure 807991DEST_PATH_IMAGE002
, kBe speed group quantity, Be the time cycle;
Wherein, the higher speed group of data rate has higher priority, and the speed group that data rate is lower has lower priority; The traversal cycle that each speed group begins according to the above-mentioned setting frequency is referred to as this speed group intrinsic traversal cycle;
S6, each speed group begin to repeat traversal according to its intrinsic traversal cycle from higher prior stage speed group; In the ergodic process of lower priority speed group, if begun the intrinsic traversal cycle of a higher prior stage speed group, at this moment, lower priority speed group ergodic process will be interrupted, then begin to travel through higher prior stage speed group, after higher prior stage speed group traversal finishes, continue the ergodic process of interrupted lower priority speed group again;
S7, when end data is gathered, according to speed group priority orders, travel through all speed groups.
Because hyperchannel multi-rate data acquisition system storage management method of the present invention is divided equally the complexion amount for each data channel and is
Figure 442289DEST_PATH_IMAGE008
Cache memory section,
Figure 685183DEST_PATH_IMAGE010
Value be the bit number that the secondary burst in main storage area writes, and each data channel
Figure 661229DEST_PATH_IMAGE008
Be worth all identical.Therefore, significantly reduced the capacity of high-speed buffer storage space.Again because hyperchannel multi-rate data acquisition system storage management method of the present invention adopts the mode of data rate multiplication to divide the speed group, make the higher speed group of data rate can access more traversal chance, the speed group that data rate is lower obtains less traversal chance.Because it is higher that the higher passage of data rate writes the speed of data, otherwise, then lower; Make writing with reading speed of data mate mutually, guaranteeing under the situation that cache memory section does not overflow, the adjustment of science the relation between the reading speed of the writing speed of cache memory section size, data and data.And, also effectively improved data and from the high-speed buffer to the main storage area, write efficient.
Specific embodiment
With a specific embodiment hyperchannel multi-rate data acquisition system storage management method of the present invention is further described below.
Set the number of packet of speed group kBe 5, and the data channel quantity of each speed group is n, then the speed group # is V 1, V 2, V 3.V 4, V 5, the data rate of speed group is from V 1To V 5Increase successively, namely priority increases successively:
The capacity of setting the cache memory section of each data channel distribution is C, Value be the bit number that the secondary burst in main storage area writes;
Set the service time slot ServiceBe t, the time that namely travels through each data channel is t;
Coefficient h=2 k-1 =2 4=16,
Systematic parameter
Figure 52312DEST_PATH_IMAGE020
=n+
Figure 2013102348518100002DEST_PATH_IMAGE062
N+
Figure 2013102348518100002DEST_PATH_IMAGE064
N+
Figure 2013102348518100002DEST_PATH_IMAGE066
N+
Figure 2013102348518100002DEST_PATH_IMAGE068
N=
Figure 2013102348518100002DEST_PATH_IMAGE070
n
Time cycle
Figure 636746DEST_PATH_IMAGE018
=
Figure 365668DEST_PATH_IMAGE070
N * t=
Figure 506799DEST_PATH_IMAGE070
Nt;
First FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 2013102348518100002DEST_PATH_IMAGE072
The nt time;
Second FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 2013102348518100002DEST_PATH_IMAGE074
The nt time, traversal V 3Spend
Figure 2013102348518100002DEST_PATH_IMAGE076
The nt time;
The 3rd FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 194657DEST_PATH_IMAGE072
The nt time;
The 4th FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 700724DEST_PATH_IMAGE074
The nt time, traversal V 3Spend
Figure 2013102348518100002DEST_PATH_IMAGE078
The nt time, traversal V 2Spend
Figure 2013102348518100002DEST_PATH_IMAGE080
The nt time;
The 5th FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 792308DEST_PATH_IMAGE072
The nt time;
The 6th FrameIn, traversal V 5Spend the nt time, traversal V 4Spend The nt time, traversal V 3Spend
Figure 2013102348518100002DEST_PATH_IMAGE082
The nt time;
The 7th FrameIn, traversal V 5Spend the nt time, traversal V 4Spend
Figure 401199DEST_PATH_IMAGE072
The nt time;
The 8th FrameIn, traversal V 5Spend the nt time, traversal V 4Spend The nt time, traversal V 3Spend The nt time, traversal V 2Spend
Figure 2013102348518100002DEST_PATH_IMAGE084
The nt time, traversal V 1Spend
Figure 2013102348518100002DEST_PATH_IMAGE086
The nt time;
The the 9th to 15 FrameProcess and first to seven FrameIdentical;
The 16 FrameIn, traversal V 5Spend the nt time, traversal V 4Spend The nt time, traversal V 3Spend
Figure 983523DEST_PATH_IMAGE078
The nt time, traversal V 2Spend The nt time, traversal V 1Spend
Figure 631990DEST_PATH_IMAGE086
The nt time.
By above-described embodiment as can be known, exist hIndividual FrameIn, all speed groups can travel through once at least.Because hyperchannel multi-rate data acquisition system storage management method of the present invention adopts the mode of data rate multiplication to divide the speed group, and, the traversal frequency of higher rate group is the height of low rate group relatively, taken into account the relation of speed buffering space size and the data read frequency, therefore, as long as traversal once in the time interval of setting, the data in the respective rate group cache memory section just can not overflowed, and its core concept is to change the space with the time.
In addition, when end data is gathered, need the data of all cache memory sections are write the main storage area, therefore, when receiving the data acquisition END instruction, hyperchannel multi-rate data acquisition system storage management method of the present invention travels through all speed groups according to speed group priority orders.
Obviously, the useful technique effect of hyperchannel multi-rate data acquisition system storage management method of the present invention is the capacity that has significantly reduced the high-speed buffer storage space, simultaneously, has improved data and write efficient from the high-speed buffer to the main storage area.

Claims (1)

1. hyperchannel multi-rate data acquisition system storage management method, it is characterized in that: this method may further comprise the steps:
S1, according to data rate order from low to high, in the mode of data rate multiplication all data channel that system receives are divided into the speed group, 1/8 the data channel that comprises in the minimum speed limit group that system receives; Wherein, speed group quantity kWith coefficient hThere is following relation:
Figure 2013102348518100001DEST_PATH_IMAGE002
（1）
In the formula, hBe coefficient, its value is 2 integral number power; kBe speed group quantity;
S2, set being numbered of speed group from low to high according to data rate
Figure 2013102348518100001DEST_PATH_IMAGE004
, the data channel quantity in the corresponding speed group is respectively
Figure 2013102348518100001DEST_PATH_IMAGE006
S3, for each data channel partition capacity be
Figure 2013102348518100001DEST_PATH_IMAGE008
Cache memory section, Value be the bit number that the secondary burst in main storage area writes, and each data channel
Figure 198339DEST_PATH_IMAGE008
Be worth all identical;
S4, setting-up time cycle
Figure 2013102348518100001DEST_PATH_IMAGE012
, set the service time slot
Figure 2013102348518100001DEST_PATH_IMAGE014
, wherein, the service time slot
Figure 2013102348518100001DEST_PATH_IMAGE016
Duration for being that data in the high-speed buffer of C are written to the time required in the main storage area with capacity; Time cycle
Figure 2013102348518100001DEST_PATH_IMAGE018
With the service time slot
Figure 715296DEST_PATH_IMAGE014
Between have a following relation:
Figure 2013102348518100001DEST_PATH_IMAGE020
（2）
In the formula, NBe systematic parameter, its value is
Figure 2013102348518100001DEST_PATH_IMAGE022
(3)
Wherein,
Figure 373548DEST_PATH_IMAGE006
Be respectively and be numbered Data channel quantity in the speed group;
Simultaneously, also satisfy following formula:
（4）
In the formula,
Figure 423861DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 2013102348518100001DEST_PATH_IMAGE028
Be coefficient, its value is 2 integral number power;
Figure 2013102348518100001DEST_PATH_IMAGE030
For being numbered
Figure 2013102348518100001DEST_PATH_IMAGE032
The maximum rate of speed group, unit is
Figure 2013102348518100001DEST_PATH_IMAGE034
Figure 2013102348518100001DEST_PATH_IMAGE036
Be systematic parameter, its value is
Figure 914098DEST_PATH_IMAGE022
Figure 680935DEST_PATH_IMAGE016
Be the service time slot, unit is
Figure 2013102348518100001DEST_PATH_IMAGE038
Transform (4):
Figure 2013102348518100001DEST_PATH_IMAGE040
（5）
Convolution (3) and formula (5):
In the formula,
Figure 518441DEST_PATH_IMAGE008
Be the data channel capacity, its value is the bit number that a secondary burst in main storage area writes, and unit is
Figure 84551DEST_PATH_IMAGE026
Be coefficient, its value is 2 integral number power,
Figure 123625DEST_PATH_IMAGE002
, kBe speed group quantity;
For being numbered
Figure 428015DEST_PATH_IMAGE032
The maximum rate of speed group, unit is
Figure 646507DEST_PATH_IMAGE034
Figure 755146DEST_PATH_IMAGE036
Be systematic parameter, its value is
Figure 363982DEST_PATH_IMAGE022
Figure 599792DEST_PATH_IMAGE016
Be the service time slot, unit is
Figure 423522DEST_PATH_IMAGE038
Be respectively and be numbered
Figure 549927DEST_PATH_IMAGE004
The quantity of data channel in the speed group;
S5, according to the data channel that begins with the following frequency to travel through in each speed group, described traversal refers to the data in this data channel cache memory section are written in the main storage area:
The speed group
Figure 304607DEST_PATH_IMAGE032
, every
Figure 2013102348518100001DEST_PATH_IMAGE044
Individual time cycle traversal once;
The speed group , every
Figure 2013102348518100001DEST_PATH_IMAGE048
Individual time cycle traversal once;
The speed group
Figure 2013102348518100001DEST_PATH_IMAGE050
, every
Figure 2013102348518100001DEST_PATH_IMAGE052
Individual time cycle traversal once;
……
The speed group , every
Figure 2013102348518100001DEST_PATH_IMAGE056
Individual time cycle traversal once;
The speed group
Figure 2013102348518100001DEST_PATH_IMAGE058
, every
Figure 2013102348518100001DEST_PATH_IMAGE060
Individual time cycle traversal once;
In the formula,
Figure 622324DEST_PATH_IMAGE028
Be coefficient, its value is 2 integral number power,
Figure 75696DEST_PATH_IMAGE002
, kBe speed group quantity,
Figure 659124DEST_PATH_IMAGE012
Be the time cycle;
Wherein, the higher speed group of data rate has higher priority, and the speed group that data rate is lower has lower priority; The traversal cycle that each speed group begins according to the above-mentioned setting frequency is referred to as this speed group intrinsic traversal cycle;
S6, each speed group begin to repeat traversal according to its intrinsic traversal cycle from higher prior stage speed group; In the ergodic process of lower priority speed group, if begun the intrinsic traversal cycle of a higher prior stage speed group, at this moment, lower priority speed group ergodic process will be interrupted, then begin to travel through higher prior stage speed group, after higher prior stage speed group traversal finishes, continue the ergodic process of interrupted lower priority speed group again.
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CN104637483A (en) * 2015-02-03 2015-05-20 中国电子科技集团公司第五十八研究所 Multichannel-based low-speed voice coding/decoding system
CN108009008A (en) * 2016-10-28 2018-05-08 北京市商汤科技开发有限公司 Data processing method and system, electronic equipment
CN113114684A (en) * 2021-04-14 2021-07-13 浙江中拓合控科技有限公司 Information transmission system, method and device for field device

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