CN103262228B - 具有抗电迁移馈线结构的ic器件 - Google Patents
具有抗电迁移馈线结构的ic器件 Download PDFInfo
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- CN103262228B CN103262228B CN201180060401.0A CN201180060401A CN103262228B CN 103262228 B CN103262228 B CN 103262228B CN 201180060401 A CN201180060401 A CN 201180060401A CN 103262228 B CN103262228 B CN 103262228B
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- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/970,464 | 2010-12-16 | ||
| US12/970,464 US8531030B2 (en) | 2010-12-16 | 2010-12-16 | IC device having electromigration resistant feed line structures |
| PCT/US2011/065355 WO2012083110A2 (en) | 2010-12-16 | 2011-12-16 | Ic device having electromigration resistant feed line structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103262228A CN103262228A (zh) | 2013-08-21 |
| CN103262228B true CN103262228B (zh) | 2016-04-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180060401.0A Active CN103262228B (zh) | 2010-12-16 | 2011-12-16 | 具有抗电迁移馈线结构的ic器件 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8531030B2 (enExample) |
| JP (1) | JP6053690B2 (enExample) |
| CN (1) | CN103262228B (enExample) |
| WO (1) | WO2012083110A2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8575007B2 (en) * | 2011-03-28 | 2013-11-05 | International Business Machines Corporation | Selective electromigration improvement for high current C4s |
| US9318413B2 (en) | 2013-10-29 | 2016-04-19 | Globalfoundries Inc. | Integrated circuit structure with metal cap and methods of fabrication |
| US9318414B2 (en) | 2013-10-29 | 2016-04-19 | Globalfoundries Inc. | Integrated circuit structure with through-semiconductor via |
| US9515035B2 (en) | 2014-12-19 | 2016-12-06 | International Business Machines Corporation | Three-dimensional integrated circuit integration |
| US10068181B1 (en) * | 2015-04-27 | 2018-09-04 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafer and methods for making the same |
| US10289794B2 (en) | 2016-12-14 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Layout for semiconductor device including via pillar structure |
| US10833036B2 (en) | 2018-12-27 | 2020-11-10 | Texas Instruments Incorporated | Interconnect for electronic device |
| US11362047B2 (en) * | 2020-04-16 | 2022-06-14 | Texas Instruments Incorporated | Integrated system-in-package with radiation shielding |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030216023A1 (en) * | 1997-03-26 | 2003-11-20 | Wark James M. | Projected contact structures for engaging bumped semiconductor devices and methods of making the same |
| US20050028123A1 (en) * | 2003-07-28 | 2005-02-03 | Senol Pekin | Optimized bond out method for flip chip wafers |
| US20080026560A1 (en) * | 2002-06-25 | 2008-01-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
| US20080042271A1 (en) * | 2005-02-01 | 2008-02-21 | Dauksher Walter J | Trace Design to Minimize Electromigration Damage to Solder Bumps |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4452217B2 (ja) * | 2005-07-04 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| US8212357B2 (en) | 2008-08-08 | 2012-07-03 | International Business Machines Corporation | Combination via and pad structure for improved solder bump electromigration characteristics |
| WO2010059724A2 (en) * | 2008-11-20 | 2010-05-27 | Qualcomm Incorporated | Capacitor die design for small form factors |
| US8084858B2 (en) * | 2009-04-15 | 2011-12-27 | International Business Machines Corporation | Metal wiring structures for uniform current density in C4 balls |
-
2010
- 2010-12-16 US US12/970,464 patent/US8531030B2/en active Active
-
2011
- 2011-12-16 WO PCT/US2011/065355 patent/WO2012083110A2/en not_active Ceased
- 2011-12-16 CN CN201180060401.0A patent/CN103262228B/zh active Active
- 2011-12-16 JP JP2013544804A patent/JP6053690B2/ja active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030216023A1 (en) * | 1997-03-26 | 2003-11-20 | Wark James M. | Projected contact structures for engaging bumped semiconductor devices and methods of making the same |
| US20080026560A1 (en) * | 2002-06-25 | 2008-01-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
| US20050028123A1 (en) * | 2003-07-28 | 2005-02-03 | Senol Pekin | Optimized bond out method for flip chip wafers |
| US20080042271A1 (en) * | 2005-02-01 | 2008-02-21 | Dauksher Walter J | Trace Design to Minimize Electromigration Damage to Solder Bumps |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103262228A (zh) | 2013-08-21 |
| JP6053690B2 (ja) | 2016-12-27 |
| WO2012083110A3 (en) | 2012-09-07 |
| US8531030B2 (en) | 2013-09-10 |
| US20120153458A1 (en) | 2012-06-21 |
| WO2012083110A2 (en) | 2012-06-21 |
| JP2014501446A (ja) | 2014-01-20 |
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