CN103259536B - Eliminate the device of charge pump phase lock loop road loop filter resistor noise - Google Patents
Eliminate the device of charge pump phase lock loop road loop filter resistor noise Download PDFInfo
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Abstract
The present invention provides a kind of improved phase-locked loop based on charge pump, and loop filter resistance noise is reduced about one magnitude.Voltage controlled oscillator generates clock signal, and it is input into phase detectors, phase detectors comparison oscillator clock and reference clock, and generates the electric current proportional to phase difference using charge pump and export.The proportional electric current is converted to voltage by loop filter, and is connected to oscillator input.The loop filter is made of the device of capacitor, resistor and the most of resistance noise of bypass.
Description
Priority
It was submitted this application claims on 2 20th, 2012, it is entitled " to eliminate charge pump phase lock loop road loop filter resistance
Technology (the A NOVEL TECHNIQUE TO REMOVE THE LOOP FILTER RESISTOR NOISE IN of device noise
CHARGE-PUMP PLL) " U.S. Provisional Application NO.61/600,745 priority, entire contents are incorporated herein as joining
It examines.
Technical field
Present application relates generally to a kind of phase-locked loop (PLL), and relate more specifically to eliminate PLL loop filter resistance
Device thermal noise.
Background technique
With reference to Fig. 1, it illustrates traditional PLL 100.Resistor Rcp 155 is used for PLL 100 for stability mesh
, to generate " zero " in loop switch function and to ensure the stability near entire gain frequency.However, PLL's is entire
Phase noise (shake) can be problematic.
Itd is proposed to solve the problems, such as that PLL loop is various, such as phase noise characteristic, other methods, such as Klemmer
United States Patent (USP) No.6,420,917B1, the entitled " circuit PLL (the PLL Loop Filter with switched-capacitor resistor
With Switched-Capacitor Resistor)".However, this structure seems that there are three disadvantages: 1) there are additional electrics
The demand of container and the 15% of entire loop filter area, 2 may be will increase) need non-overlapping clock generator to generate
For the control signal of switched capacitor, 3) need two big switches to be used for the switched capacitor network (figure of Klemmer patent
Q1 and Q2 in 4), due to being coupled by capacitor parasitics, this can increase some switching noises in ' VCTRL ' node.
Therefore, there are a kind of demands to handle the relevant at least some problems of conventional PLL circuit for this field.
Summary of the invention
First aspect provides a kind of circuit, comprising: phase-frequency detector (PFD)；Upward current switch, is coupled to
The output of phase-frequency detector；Downward current switch is coupled to the output of PFD；Current source is opened by upward electric current
Pass is coupled to node, and downward current source is coupled to node by downward current switch, which is coupled to: a) pressing
It controls oscillator (VCO), the wherein output of VCO and the input connection of PFD and b) loop filter resistor bypass circuit,
Include: loop filter resistor, is coupled to the node；Capacitor is connected with loop filter resistor, the capacitor
Device is also grounded；And first by-pass switch, it is coupled to the node, the second by-pass switch, with the first by-pass switch string
Connection connection, which is also coupled to the anode of capacitor, wherein the first by-pass switch and the second by-pass switch that
This series connection and with loop filter resistor parallel connection, wherein when the first and second by-pass switches are not closed, the ring
Path filter resistor be used to generate zero point in the loop；And first control line, by CMOS inverter to powering on
Stream switch arrives the first shunt resistive element of connection；Second control line is joined by another CMOS inverter from upward current switch
It is connected to the second shunt resistive element, wherein the first and second by-pass switches are complementary cmos pair, wherein when the first and second bypasses
When switch is not closed, loop filter resistor is used to zero pole, and when loop filter resistor is bypassed, ring
The noise of path filter resistor is bypassed.
Second aspect provides a kind of circuit, comprising: PFD；Upward current switch, is coupled to phase-frequency detector
Output；Downward current switch is coupled to the output of PFD；Current source is coupled to node by upward current switch；
Downward current source is coupled to node by downward current switch, which is coupled to: a) VCO, wherein the output of VCO
The input for being coupled to PFD and b) loop filter resistor bypass circuit comprising: it is connected to the loop filter of the node
Wave device resistor；With the capacitor with loop filter resistor coupled in series, which is also grounded；And it is connected to the section
First by-pass switch of point, is coupled in series to the second by-pass switch of the first by-pass switch, the second by-pass switch also with capacitor
Anode connection, wherein the first by-pass switch and the second by-pass switch be coupled to one another in series and and with loop filter resistor simultaneously
Connection connection.
The third aspect provides a kind of circuit, comprising: a kind of circuit, comprising: PFD；One upward current switch, is coupled to
The output of phase-frequency detector；Downward current switch is coupled to the output of phase-frequency detector；Current source leads to
It crosses upward current switch and is coupled to node, downward current source is coupled to node by downward current supply switch, the node
It is coupled to: a) VCO, the input and b) loop filter resistor bypass circuit that wherein the output of VCO is connected to PFD,
It include: the loop filter resistor for being connected to the node；With the capacitor of the loop filter resistor coupled in series, the electricity
Container is also grounded；And first by-pass switch, it is coupled to the node, the second by-pass switch, with the first by-pass switch
Coupled in series, the second by-pass switch are also coupled to the anode of capacitor, wherein the first by-pass switch and the second by-pass switch that
This coupled in series and with loop filter resistor parallel connection, wherein when the first and second by-pass switches are not turned off
When, loop filter resistor be used to generate zero point in circuit；And first control line, couple from upward current switch
To the first shunt resistive element；And second control line, the second shunt resistive element is connected to from upward current switch.
Detailed description of the invention
Referring now to following description:
Fig. 1 shows conventional PLL circuit；
Fig. 2 shows the PLL circuits that circuit is removed with loop filter resistor；
Fig. 3 A is the graphical representation of exemplary of Fig. 2 signal when PLL is in stable state in Fig. 2；
Fig. 3 B is the graphical representation of exemplary for the reception signal that Fig. 2 loop filter resistor removes circuit；And
Fig. 4 is example modelled figure, compares the pectrum noise of the loop filter with and without noise shunt circuit
Density.
Specific embodiment
With reference to Fig. 2, it illustrates what is constructed according to the application principle to remove circuit 200 with loop filter resistor
The one aspect of PLL.Understood by the inventor that the application specifies, in typical charge-pump PLL, loop filter electricity
Hindering device is to cause one of the reason of always exporting PLL phase noise (shake).By using removal loop during the part PLL period
The method of filter resistors, it is possible to reduce the loop filter resistor noise of PLL.
It in general, PLL includes two poles and high DC gain in starting point, therefore is unstable.Resistor is connected in series to electricity
Container, as loop filter resistor to generate zero point in the feedback control loop of PLL, this helps to stablize PLL.As invention
Desired by people, loop filter resistor, according to the understanding of present inventor, the use of the resistor Rcp 155 in Fig. 1 exists
Further problems, such as thermal noise are introduced in PLL circuit, which increase shakes, that is, thermal noise is added to PLL and influences finally
PLL output clock phase noise.According to the understanding of inventor, in the high speed low jitter application in traditional PLL design, loop
Filter resistors, which become, causes one of principal element of phase noise
Generally about the more information of PLL, " the Design of Analog CMOS of Behzad Razavi is please referred to
Integrated Circuits ", chapters and sections 15.2.3, " Basic Charge-Pump PLL ", McGraw Hill
International is published, and date of printing 2001, the 556-562 pages, merges reference entire contents herein.It is elaborated
PLL loop dynamic, and more specifically, further describing needs for the zero of holding PLL stability refering to the discussion for the two poles of the earth
The discussion asked.
In circuit 200, phase-frequency detector (PFD) 210 receives REFCLK signal, i.e. reference clock signal, and
FDBKCLK signal, i.e. feedback clock signal.PFD 210 exports upward signal UP 211 and down signal DN 212, drives respectively
It trend upper switch 222 and is opened or closed to lower switch 227.It is coupled to the first charge pump 220 to upper switch 222, for electricity
Stream source.It is coupled to the second charge pump 225 to lower switch 227, is equally current source.To upper switch 222 and to lower switch 227
It is coupled together in node 229.
Be connected to node 229 is that loop filter resistor removes circuit 250, has VCTRL electricity in node 229
Pressure.Removing circuit 250 includes the loop filter resistor 255 for being connected to node 229.First switch UPZ 260 and second is opened
DNZ 265 is closed from 229 coupled in series of node, and same parallel connection is to loop filter resistor 255.RCP 255 also by
It is connected to filter capacitor 270, the coupled ground connection of the filter capacitor 270.Switch 260,265 each can be complementation
CMOS pairs.
Node 229 has voltage VCTRL, is coupled to the input of voltage controlled oscillator (VCO) 280.The output of VCO280 connects
Be fed back to PFD 210 as signal FBKCLK by feedback line 285.
In PLL circuit 200, UP line 222, which passes through control line 230 and passes through phase inverter 213, is connected to UPZ switch 260；And
DNZ switch 265 is connected to lower switch 227 by phase inverter 215 and by controlling route 235.
When UP 211 is logically high, UPZ switch 260 is opened (logic low).When UP211 is logic low, UPZ switch
260 are closed (logically high).When DN 212 is logically high, DNZ switch 265 is opened (logic low).When DN 212 is logic
Low, DNZ switch 265 is closed (logically high).
As the present inventor is understood, typically, once PLL is by " setting ", charge pump 220,225 will be only in entire PLL
The sub-fraction in period is activated, for example, approximation 5% to 10%.Therefore, loop filter Rcp255 is only relatively short at this
Interval time needed by loop stability.However, in traditional PLL, unlike the PLL 200 of the application, loop filter
Resistor is connected to node 229 in institute's having time and increases noise, such as thermal noise through institute's having time in PLL period.
In the suggesting method of the application theory, when 225 charge or discharge capacitor 270 of charge pump 220 or charge pump,
Loop filter resistor is used, such as Rcp 255.Turn off the switch 222 or switch 227 be then associated with unlatching respectively
Switch 260,265, to add loop filter resistor Rcp 255 to be used by PLL 200.However, if UP switch 222
It is open with DN switch 227, then UPZ switch 260 and DNZ switch 265 are to close, short-circuit Rcp255.It note that switch
260 and 265 resistance combination, even if can be the quantity of the resistance less than Rcp 255 when both closing and series connection is added
Grade, so as to cause the reduction of noise in circuit.Equally, switch 260 and 265 is complementary CMOS switches, and from PMOS and
NMOS noise can cancel one another.Therefore, minimum switching noise is had in node 229.
On the one hand, charge pump 220 and 225 is run by the signal generated using PFD 210, utilizes two gate circuits
The noise that 260 and 265, PLL loop filter resistor 255 generates substantially has been decreased by.For PLL circuit 200 1
The signal divided is used in the other parts of circuit 200.In PLL circuit 200, at least one for the PLL period of Rcp255
Dividing is ignored element, when needing polar-loop stability, still maintains its function.
At more aspects, PLL200 can be used to generate the clock signal for signal increment adjuster.
Fig. 3 A and 3B show the time-scale of PLL200.
About 3A, once as indicated, PLL 200 reaches stable state, clock REFCLK and FDBCLK is having the same
Frequency, and phase alignment.In this state, charge pump will only be activated during an of short duration time and avoid dead zone, and
This dead time is typically in the about 5%-10% of clock cycle Tclk.Stable state waveform is shown in figure 3 a.
About 3B, the exemplary status of switch 222,227 is shown.As indicated, when UP and DN switch opening/logically high letter
When number being applied to switch 222,227, switch 260 and 265 is opened, therefore adds loop filter resistor Rcp 255 and arrive
In filter circuit.However, when shutdown signal is applied to switch 222,227, switch 260 and 265 is closed, therefore short circuit
Rcp255 and lesser noise is added in node 229.Fig. 4 shows the loop filter with and without noise shunt circuit
The diagram of the noise spectrum density of device.Representative value is assumed to be Rcp=8000 ohm, the all-in resistance of Cap=200pF and by-pass switch
It is 350 ohm (Ohm), and by-pass switch is switched to ON during 90% clock.
Fig. 4 shows the example for comparing the noise spectral density of the loop filter with and without noise shunt circuit
Property simulation drawing.From the point of view of figure, the noise spectral density without bypass circuit is higher than the noise spectral density with bypass circuit, until
It is certain until frequency (Fcut).This " Fcut " frequency depends on the ratio of combined by-pass switch resistor and Rcp.Loop filter
Wave device noise generates band logical conversion function to final PLL output, and top cutting frequency is PLL entire gain bandwidth
(UGB).Therefore ideal whole loop filter noises more than PLL UGB frequency will be eliminated by PLL loop, and therefore quilt
Less concern.Therefore by-pass switch impedance is carefully designed, so as to for the loop filter with by-pass switch, until
Total overall noise energy of PLL UGB is smaller.
It is related with the application it will be appreciated by those skilled in the art that other and further increase, delete, replace and repair
Changing can be used in described embodiment.
Claims (17)
1. a kind of circuit, comprising:
Phase-frequency detector, i.e. PFD；
Upward current switch is connected to the output of the phase-frequency detector；
Downward current switch is connected to the output of the phase-frequency detector；
Current source is connected to node by the upward current switch,
Downward current source is connected to the node by the downward current switch,
The node is coupled to:
A) voltage controlled oscillator, i.e. VCO, wherein the output of the VCO is coupled to the input of the PFD, and
B) loop filter resistor bypass circuit, comprising:
Loop filter resistor is coupled to the node；
Capacitor, with the loop filter resistor coupled in series, the capacitor is also grounded；And
First by-pass switch is coupled to the node, and
Second by-pass switch, and the first by-pass switch coupled in series,
Second by-pass switch is also coupled to the anode of the capacitor,
Wherein first by-pass switch and second by-pass switch be coupled to one another in series and with loop filter electricity
Device parallel connection is hindered,
Wherein when first by-pass switch and second by-pass switch are not closed, the loop filter resistor quilt
For in the circuit generate zero point to generate zero pole, and
First control line is connected to first by-pass switch from the upward current switch；And
Second control line is connected to second by-pass switch from the downward current switch,
Wherein the first/second by-pass switch is opened in the up/down turn ON, and described
One/the second by-pass switch is closed when the up/down current switch disconnects,
Wherein first by-pass switch and second by-pass switch are complementary cmos pair, and
When the loop filter resistor is bypassed, the noise of the loop filter resistor is bypassed.
2. circuit according to claim 1, wherein the circuit includes phase-locked loop, i.e. PLL.
3. circuit according to claim 1,
Wherein first control line is connected to first by-pass switch from the upward current switch by the first phase inverter；
And
Wherein second control line is connected to second by-pass switch from the downward current switch by the second phase inverter.
4. circuit according to claim 1, wherein the circuit is configured as opening simultaneously and closing the electric current substantially
Source and first by-pass switch, the current source are connected to by the node and described first by the upward current switch
Way switch.
5. circuit according to claim 1, wherein the circuit be configured as opening simultaneously and close substantially it is described downwards
Current source and second by-pass switch, the downward current source are connected to the node and institute by the downward current switch
State the first by-pass switch.
6. circuit according to claim 1, wherein the first by-pass switch that the loop filter resistor is closed and
The bypass of second by-pass switch.
7. circuit according to claim 1, wherein the resistance that the loop filter resistor has is at least described
Ten times of the combined resistance of bypass switch and second by-pass switch.
8. circuit according to claim 2, wherein when the loop filter resistor is bypassed, the loop filtering
The noise of device resistor is bypassed, therefore obtains shake less in PLL loop.
9. a kind of circuit, comprising:
Phase-frequency detector, i.e. PFD；
Upward current switch is connected to the output of the phase-frequency detector；
Downward current switch is connected to the output of the phase-frequency detector；
Current source is connected to node by the upward current switch；
Downward current source is connected to the node by the downward current switch,
The node is coupled to:
A) voltage controlled oscillator, i.e. VCO, wherein the output of the VCO is coupled to the input of the PFD, and
B) loop filter resistor bypass circuit, comprising:
Loop filter resistor is coupled to the node；
Capacitor, with the loop filter resistor coupled in series, the capacitor is also grounded；And
First by-pass switch is coupled to the node, and
Second by-pass switch is coupled in series to first by-pass switch,
Second by-pass switch is also coupled to the anode of the capacitor,
Wherein first by-pass switch and second by-pass switch be coupled to one another in series and with the loop filter resistance
Device parallel connection；
First control line is connected to first by-pass switch from the upward current switch；And
Second control line is connected to second by-pass switch from the downward current switch,
Wherein the first/second by-pass switch is opened in the up/down turn ON, and described
One/the second by-pass switch is closed when the up/down current switch disconnects.
10. circuit according to claim 9, wherein the circuit includes phase-locked loop, i.e. PLL.
11. circuit according to claim 9, wherein first by-pass switch and second by-pass switch are complementary
CMOS pairs.
12. circuit according to claim 9, wherein the circuit is configured as opening simultaneously and closing the electric current substantially
Source and first by-pass switch, the current source are connected to by the node and described first by the upward current switch
Way switch.
13. circuit according to claim 9, wherein the circuit be configured as opening simultaneously and close substantially it is described downwards
Current source and second by-pass switch, the downward current source are connected to the node and institute by the downward current switch
State the first by-pass switch.
14. circuit according to claim 10, wherein the first by-pass switch that the loop filter resistor is closed
It is bypassed with the second by-pass switch.
15. circuit according to claim 14, wherein when the loop filter resistor is bypassed, the loop filter
The noise of wave device resistor is bypassed, therefore obtains the less shake in PLL loop.
16. a kind of circuit, comprising:
Phase-frequency detector, i.e. PFD；
Upward current switch is coupled to the output of the phase-frequency detector；
Downward current switch is coupled to the output of the phase-frequency detector；
Current source is connected to node by the upward current switch,
Downward current source is connected to the node by the downward current switch,
The node is coupled to:
A) voltage controlled oscillator, i.e. VCO, wherein the output of the VCO is coupled to the input of the PFD, and
B) loop filter resistor bypass circuit, comprising:
Loop filter resistor is coupled to the node；
Capacitor, with the loop filter resistor coupled in series, the capacitor is also grounded；
First by-pass switch is coupled to the node；And
Second by-pass switch, and the first by-pass switch coupled in series,
Second by-pass switch also couples with the anode of the capacitor,
Wherein first by-pass switch and second by-pass switch be coupled to one another in series and with loop filter electricity
Device parallel connection is hindered,
Wherein when first by-pass switch and second by-pass switch are not closed, the loop filter resistor
It is used to generate zero point in the circuit, and
First control line is connected to first by-pass switch from the upward current switch；And
Second control line is connected to second by-pass switch from the downward current switch,
Wherein the first/second by-pass switch is opened in the up/down turn ON, and described
One/the second by-pass switch is closed when the up/down current switch disconnects.
17. circuit according to claim 16, wherein the circuit includes phase-locked loop, i.e. PLL.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261600745P | 2012-02-20 | 2012-02-20 | |
| US61/600,745 | 2012-02-20 | ||
| US13/462,973 | 2012-05-03 | ||
| US13/462,973 US8593188B2 (en) | 2012-02-20 | 2012-05-03 | Apparatus to remove the loop filter resistor noise in charge-pump PLL |
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| CN103259536A CN103259536A (en) | 2013-08-21 |
| CN103259536B true CN103259536B (en) | 2018-12-18 |
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| CN201310123957.0A Active CN103259536B (en) | 2012-02-20 | 2013-02-20 | Eliminate the device of charge pump phase lock loop road loop filter resistor noise |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103259984B (en) | 2013-05-07 | 2016-04-27 | 上海华力微电子有限公司 | CMOS charge pump circuit |
| CN104426479B (en) * | 2013-08-29 | 2018-02-13 | 京微雅格（北京）科技有限公司 | A kind of low-power consumption, low jitter, the crystal-oscillator circuit of wide operating range |
| JP2015053628A (en) * | 2013-09-09 | 2015-03-19 | ソニー株式会社 | Phase-locked loop, phase-locked module and phase locking method |
| US9806724B1 (en) * | 2016-09-22 | 2017-10-31 | Qualcomm Incorporated | Switched-capacitor circuits in a PLL |
| CN108075773B (en) * | 2016-11-14 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Starting circuit for phase-locked loop and phase-locked loop |
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| FI108688B (en) * | 2000-06-30 | 2002-02-28 | Nokia Corp | Method and arrangement for setting the frequency |
| US7015735B2 (en) * | 2003-12-19 | 2006-03-21 | Renesas Technology Corp. | Semiconductor integrated circuit having built-in PLL circuit |
| US7145400B2 (en) * | 2004-12-02 | 2006-12-05 | Ceva Services Limited | Phase locked loop with a switch capacitor resistor in the loop filter |
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| CN1377521A (en) * | 1999-10-01 | 2002-10-30 | 艾利森公司 | PLL loop filter with switched-capacitor resistor |
| CN101030781A (en) * | 2006-01-17 | 2007-09-05 | 三星电子株式会社 | Sigma-delta fractional-n phase locked loop for reducing lock time and frequency error |
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