CN103259535B - Delay locked loop circuit and delay phase-lock technique - Google Patents
Delay locked loop circuit and delay phase-lock technique Download PDFInfo
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- CN103259535B CN103259535B CN201210034012.7A CN201210034012A CN103259535B CN 103259535 B CN103259535 B CN 103259535B CN 201210034012 A CN201210034012 A CN 201210034012A CN 103259535 B CN103259535 B CN 103259535B
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Abstract
Delay locked loop circuit and delay phase-lock technique.The invention discloses a delay locked loop circuits, include a voltage-controlled delay route, are used to generate the differential signal of multiple particular phases and a feedback signal according to an input frequency source and a control voltage；One detector, at least one in the phase and frequency for comparing the input frequency source and the feedback signal, to generate at least one detection signal；One charge pump is used to generate the control voltage according at least one detection signal；And a Selecting phasing buffer, it is used to generate the output frequency source according to the differential signal of multiple particular phases；Wherein the differential signal of each particular phases includes at least one positive phase signals and an inversion signal, and the feedback signal is the inversion signal for one of working as person for the differential signal of multiple particular phases.
Description
Technical field
The present invention relates to a kind of delay locked loop circuit and delay phase-lock technique more particularly to a kind of one reverse phase of feedback letters
Number delay locked loop circuit and delay phase-lock technique.
Background technique
In known technology, input frequency source must be carried out timing by N number of Delay Element by delay locked loop circuit
On N grade delay, and feed back a positive frequency signal, the frequency source to bolt-lock particular phases.Referring to FIG. 1, Fig. 1 is known
The schematic diagram of one delay locked loop circuit 10 of technology.As shown in Figure 1, delay locked loop circuit 10 includes a voltage controlled delay line
Road 100, a phase/frequency detector 102, a charge pump 104 and loop filter (loop filter) 106.It is voltage-controlled
After delay line (voltage controlled delay line, VCDL) 100 receives an input frequency source CLK_IN, pass through N
A delay cell DC_1~DC_N generates N grades of delays, directly to generate a feedback signal CLK_FB to phase/frequency detector
102.Phase/frequency detector 102 compares the phase difference between input frequency source CLK_IN and feedback signal CLK_FB simultaneously,
To export the detection signal DN of a first detection signal UP and one second to charge pump 104.Charge pump 104 is according to the first detection
The detection signal DN of signal UP and second further generates control voltage VC and exports to loop filter 106.Finally, circuit is filtered
Wave device 106 sends out the control voltage VC after pressure stabilizing to voltage-controlled delay route 100, and providing N number of delay cell DC_1~DC_N is to sentence
Disconnected benchmark, to export an output frequency source CLK_OUT.
Therefore, by known technology, circuit designers must pass through N number of delay cell DC_1~DC_N and feedback signal
CLK_FB is relatively lacked flexibility in circuit design with realizing the particular phases frequency source of different demands；Furthermore it is limited to make
With N number of delay cell DC_1~DC_N, the particular phases frequency source of output can just have the resolution ratio of 360/N, for inexpensive, low
For power consumption, efficient demand, it may be difficult to while reaching this purpose.
Summary of the invention
Here, disclosing a kind of delay locked loop circuit and delay phase-lock technique, resolution ratio can be improved simultaneously and reduced
Cost.
According to one aspect, a kind of delay locked loop circuit is disclosed, and to select an output frequency source, which is returned
Road circuit includes a voltage-controlled delay route, is used to generate multiple specific phases according to an input frequency source and a control voltage
Position differential wave and a feedback signal；One phase/frequency detector, for comparing the input frequency source and the feedback signal
Phase and frequency at least one, with generate at least one detection signal；One charge pump is used to according at least one inspection
It surveys signal and generates the control voltage；And a Selecting phasing buffer, it is used to be generated according to the differential signal of multiple particular phases
The output frequency source；Wherein the differential signal of each particular phases of the differential signal of multiple particular phases is just being believed comprising at least one
Number and an inversion signal, and the feedback signal is the reverse phase letter for one of working as person for the differential signal of multiple particular phases
Number.
A kind of delay phase-lock technique is disclosed according to another aspect, includes according to an input frequency source and a control electricity
Pressure, generates the differential signal of multiple particular phases and a feedback signal；Compare the input frequency source and the phase of the feedback signal
Signal is detected to generate at least one at least one in frequency in position；Control electricity is generated according at least one detection signal
Pressure；And according to the differential signal of multiple particular phases, generate an output frequency source；The wherein differential signal of multiple particular phases
The differential signal of each particular phases include at least one positive phase signals and an inversion signal, and it is multiple that the feedback signal, which is,
The differential signal of particular phases one of works as the inversion signal of person.
Detailed description of the invention
Fig. 1 is known technology the schematic diagram of a delay locked loop circuit.
Fig. 2 is the schematic diagram of one delay locked loop circuit of the present embodiment.
Fig. 3 is the thin portion schematic diagram of Selecting phasing buffer in Fig. 2.
Fig. 4 is the schematic diagram of a delay locking phase process of the present embodiment.
Fig. 5 is that the differential signal of multiple particular phases of the present embodiment is compared to the schematic diagram of known technology.
Fig. 6 is the signal that the present embodiment delay locked loop circuit is compared to known technology under different input frequency sources
Figure.
Wherein, the reference numerals are as follows：
10,20 delay locked loop circuit
100,200 voltage-controlled delay route
102 phase/frequency detectors
104,204 charge pump
2040,2042 charge pump unit
106,206 loop filter
2002 phase selectors
202 detectors
2020 phase detectors
2022 frequency detectors
208 Selecting phasing buffers
2080 selectors
2082 conversion modules
CLK_FB feedback signal
CLK_IN, T_CK1, T_CK2 input frequency source
CLK_OUT output frequency source
The differential signal of CLK_SEL1~CLK_SELm particular phases
DC_1~DC_N, DN_1~DN_m delay cell
DN1, DN2 second detects signal
PHASE_SEL, PN_SEL enable signal
The TCK period
T_DELAY working range
TOLD_VC1, TOLD_VC2, reaction time
TNEW_VC3、TNEW_VC4
UP1, UP2 first detection signal
VC controls voltage
Specific embodiment
Referring to FIG. 2, Fig. 2 is the schematic diagram of one delay locked loop circuit 20 of the present embodiment.As shown in Fig. 2, delay lock
Phase loop circuit 20 is removed to be examined comprising a voltage-controlled delay route (voltage controlled delay line, VCDL) 200, one
It surveys outside device 202, charge pump 204 and loop filter (loop filter) 206, also includes a Selecting phasing buffer
208。
Detector 202 be configured to compare an input frequency source CLK_IN and a feedback signal CLK_FB phase or
At least one in frequency, comparison result is represented to generate at least one detection signal.Fig. 2 also shows phase/frequency phase/frequency
One embodiment of the thin portion structure of rate detector 202.In this embodiment, detector 202 may include a phase detectors 2020.
Phase detectors 2020 compare the phase difference between input frequency source CLK_IN and feedback signal CLK_FB, to export respectively
The testing result of first detection signal UP1, UP2 is to charge pump 204.In addition, detector 202 also may include a frequency detector
2022, concatenation to charge pump 204.The comparable input frequency source CLK_IN and feedback signal CLK_ of this frequency detector 2022
Frequency difference between FB, the testing result of second detection signal DN1, DN2 is to charge pump 204.
Charge pump 204 is at least one the detection signal exported according to detector 202, and one control voltage of output extremely returns
Path filter 206.Loop filter 206 then can be by control voltage Vc constant in a predetermined voltage range, and exports to voltage-controlled
Delay line 200.Fig. 2 also shows an embodiment of the thin portion structure of detector 202.Charge pump 204 can be by least one electricity
Lotus pump unit is constituted.In this embodiment, charge pump 204 includes first and second charge pump unit 2040,2042, point
Not according to first detection signal UP1, UP2 and second detection signal DN1, DN2, judge to input frequency source CLK_IN and feedback signal
Phase difference and frequency difference between CLK_FB, and then it is how many to judge to need to provide in timing input frequency source CLK_IN
Offset voltage value, and control voltage VC is exported to loop filter 206.
Voltage-controlled delay route 200 is to be configured to according to the control voltage VC of input frequency source CLK_IN and one, is generated more
The differential signal CLK_SEL1~CLK_SELm of a particular phases is simultaneously supplied to Selecting phasing buffer 208, and generates a feedback
Signal CLK_FB is simultaneously supplied to detector 202.Wherein the differential signal of each particular phases all includes that a positive phase signals and one are anti-
Phase signals.And feedback signal CLK_FB is that the differential signal CLK_SEL1~CLK_SELm of multiple particular phases one of works as person's
Inversion signal.
Fig. 2 also shows an embodiment of the thin portion structure of voltage-controlled delay route 200.In this embodiment, voltage controlled delay line
Road 200 includes delay cell DN_1~DN_m, a phase selector 2002 and a conversion module 2004.Firstly, voltage-controlled delay
It after route 200 receives an input frequency source CLK_IN, first passes through conversion module 2004 and is converted to an input differential wave, to provide
To most previous delay cell DN_1 as input signal.Then, concatenated with one another by delay cell DN_1~DN_m, input frequency
Source CLK_IN is the differential signal CLK_SEL1~CLK_SELm of particular phases for sequentially generating out of phase delay in timing, and
Each differential signal of particular phases all includes a positive phase signals and an inversion signal, wherein positive phase signals and inversion signal have
Identical amplitude but phase phase difference 180 degree, and the last one delay cell DN_m exports the differential signal of its particular phases (comprising just
Phase signals and inversion signal) to phase selector 2002.Delay cell DN_1~DN_m will control voltage VC and judge base as one
Standard dynamically adjusts the differential signal CLK_SEL1~CLK_SELm of particular phases originally respectively exported, makes it stable pre- one
If in the time (can according to user's requirement definition it), and just carrying out follow-up work after reaching steady state.Next, Selecting phasing
Device 2002 is according to user's demand, for generating feedback signal CLK_FB to detector 202.Preferably, phase selector 2002
Can be according to an enable signal PN_SEL, selecting the inversion signal of the differential signal of any particular phases is feedback signal CLK_FB to make
For the reference of follow-up work.
Notably, above-mentioned work is to form a repetitive operation, for stabilisation delay cells D N_1~DN_m output
The differential signal CLK_SEL1~CLK_SELm of particular phases.Then, up to delay cell DN_1~DN_m after stable state further according to one
The differential signal CLK_SEL1~CLK_SELm of particular phases is transmitted to Selecting phasing buffer by enable signal PHASE_SEL
208.Finally, Selecting phasing buffer 208 can be generated according to the differential signal CLK_SEL1~CLK_SELm of multiple particular phases
One output frequency source CLK_OUT.
Referring to FIG. 3, Fig. 3 is the thin portion schematic diagram of Selecting phasing buffer 208 in Fig. 2.In this embodiment, phase is selected
Selecting buffer 208 may include a selector 2080 and a conversion module 2082, and using enable signal PHASE_SEL and
The differential signal CLK_SEL1~CLK_SELm of particular phases one of is worked as person and selected as a selected phase difference by selector 2080
Dynamic signal CLK_SEL, selecting phase difference signal CLK_SEL at this time is still a differential wave, i.e., selected phase difference signal
CLK_SEL also includes positive phase signals and inversion signal.Finally, conversion module 2082 is by selected phase difference signal CLK_SEL's
Positive phase signals and inversion signal are converted to output frequency source CLK_OUT, for exporting output frequency source CLK_OUT to any passive
Load circuit (not shown), in this way, completing the conversion input of delay locked loop circuit 20 frequency source CLK_IN is output frequency
The work of rate source CLK_OUT.
In simple terms, delay locked loop circuit 20 is intended to the input frequency source CLK_IN input voltage-controlled delay route of conversion
200, the phase delay in timing is generated by delay cell DN_1~DN_m of voltage-controlled delay route 200, and select by phase
It selects device 2002 and feeds back an inversion signal of the differential signal of any particular phases to detector 202, through charge pump 204 and circuit
Filter 206 generates control voltage VC finally to lock input frequency source CLK_IN, dynamically adjusts the differential signal of particular phases
CLK_SEL1~CLK_SELm with reach stable state, therefore those skilled in the art can modify according to this embodiment/increase it newly
Circuit design, the purpose person for being converted to inversion signal will input frequency source CLK_IN, is all scope of the invention.
Furthermore the differential signal CLK_SEL1~CLK_SELm of particular phases is input to Selecting phasing buffer 208, utilizes choosing
Device 2080 and conversion module 2082 are selected to select one of the differential signal CLK_SEL1~CLK_SELm of particular phases person and be formed
Output frequency source CLK_OUT, wherein user can select in advance according to actual demand and retain the differential signal CLK_ of particular phases
Person is as many as in SEL1~CLK_SELm to carry out in next step, or first converts the differential signal CLK_SEL1~CLK_ of particular phases
SELm is multiple particular phases signals, that is, integrates the positive phase signals of the differential signal of each particular phases and inversion signal is one specific
After phase signal, then by selecting at least one in all particular phases signals, export as output frequency source CLK_OUT.
Further, one used in delay locked loop circuit 20 postpones phase-lock technique, can be summarized as a delay locking phase stream
Journey 40.Referring to FIG. 4, Fig. 4 is 40 schematic diagram of delay locking phase process of the present embodiment, and postponing locking phase process 40 includes following step
Suddenly：
Step 400：Start
Step 402：According to an input frequency source and a control voltage, the differential signal of multiple particular phases and one are generated
Feedback signal CLK_FB.
Step 404：At least one compare in the phase and frequency of the input frequency source and the feedback signal, to produce
Raw at least one detection signal.The phase of input frequency source CLK_IN and feedback signal CLK_FB can for example be compared, generate the
One detection signal UP1, UP2.In addition, the frequency of input frequency source CLK_IN and feedback signal CLK_FB can be compared, again to produce
Raw second detection signal DN1, DN2.
Step 406：The control voltage is generated according at least one detection signal.For example can according to first detection signal UP1,
UP2, or control voltage VC can be generated further according to second detection signal DN1, DN2.
Step 408：According at least one detection signal, control voltage VC is generated.
Step 410：According to the differential signal of multiple particular phases, an output frequency source is generated.
Step 412：Terminate.
The differential signal of each particular phases of multiple differential signal of particular phases includes at least one positive phase signals and one
Inversion signal, and the feedback signal is the inversion signal for one of working as person for the differential signal of multiple particular phases.To sum up, prolong
The correlative detail of each step of slow locking phase process 40 can come according to the related description of delay locked loop circuit 20, Fig. 2 and Fig. 3
It further appreciates that, this will not be repeated here.
Notably, delay locked loop circuit 20 feeds back inversion signal by phase selector 2002, it is compared to
Known technology feeds back the work of a positive phase signals, and the resolution ratio of product can be improved.Referring to FIG. 5, Fig. 5 is the multiple of the present embodiment
The sequential relationship of the differential signal of particular phases is compared to the schematic diagram of known technology, and left side correspondence is known technology and it is right
While corresponding to the technology of the present embodiment.As shown in figure 5, frequency source CLK_IN is inputted at a cycle T CK, in the delay of such as Fig. 1
In the known technology of phase-locked loop circuit 10, the differential signal of the particular phases exported using N number of delay cell can be obtained 360/
The resolution ratio of N appoints the delay in the two timing only at a distance of 360/N that is, in cycle T CK, in the differential signal of particular phases.However,
Above-described embodiment by feedback inversion signal, can by each of differential signal CLK_SEL1~CLK_SELm of particular phases into
The reversion of row phase.In one case, if m is set as N/2, delay locked loop circuit 20 can reach identical resolution ratio
360/N, and then user can thereby reduce circuit area or reduce input power.At another, if m is set
For N, then can provide preferable resolution ratio is 360/2N, allows user suitably to select output frequency source.
Referring to FIG. 6, Fig. 6 is that the present embodiment delay locked loop circuit 20 is compared at different input frequency source CLK_IN
Compared with the schematic diagram of known technology.As shown in fig. 6, known technology is in different input frequency source T_CK1 or T_CK2, voltage-controlled delay
The working range of route 100 is respectively defined as T_DELAY=TOLD_VC1 or T_DELAY=TOLD_VC2, i.e., can not be by changing
Become control voltage, further changes the working range of voltage-controlled delay route 100.However, delay locked loop circuit 20 provides separately
A kind of outer design, when inputting frequency source T_CK1, providing working range is T_DELAY=TNEW_VC3+ (T_CK1/2), or is changed
It is written as TNEW_VC3=T_DELAY- (T_CK1/2), if it is pressure when inputting frequency source T_CK2 that input frequency source T_CK1, which is increased,
The reaction time of control delay line 200 will be changed to TNEW_VC4 from TNEW_VC3, also meet TNEW_VC4=T_DELAY- (T_
CK2/2), in other words, change the control voltage of voltage-controlled delay route 200, the work model of voltage-controlled delay route 200 can be changed
It encloses, so that user obtains more elastic working range under different demands.
To sum up, delay locked loop circuit provided by above-described embodiment and delay phase-lock technique, pass through a pressure
It controls one of delay line phase selector and pre-processes an input frequency source, and feed back an inversion signal, for dynamically adjusting
The differential signal of multiple particular phases that voltage-controlled delay route generates is to reach a stable state, then by a Selecting phasing buffer, turns
The differential signal of multiple particular phases is changed to export an output frequency source.If being compared under the delay cell of fixed quantity
Know that technology can provide better twice of resolution ratio output；If also can provide voltage-controlled delay route under different input frequency sources
More elastic working range improves the application range of product accordingly.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of delay locked loop circuit, includes：
One voltage-controlled delay route, which is characterized in that be used to be generated multiple specific according to an input frequency source and a control voltage
Phase difference signal and a feedback signal；
One detector, at least one in the phase and frequency for comparing the input frequency source and the feedback signal, with
Generate at least one detection signal；
One charge pump, for generating the control voltage according at least one detection signal；And
One Selecting phasing buffer is used to generate an output frequency source according to the differential signal of multiple particular phases；
Wherein the differential signal of each particular phases of the differential signal of multiple particular phases includes at least one positive phase signals and one
Inversion signal, and the feedback signal is the inversion signal for one of working as person for the differential signal of multiple particular phases；
Wherein the voltage-controlled delay route includes：
Multiple delay cells are coupled in series, and multiple delay cell connects the Selecting phasing buffer, are used to defeated according to this
Enter frequency source and the control voltage, generates the differential signal of multiple particular phases to the Selecting phasing buffer；And
One phase selector is directly connected to last one in multiple delay cell, for receiving in multiple delay cell most
The differential signal of the particular phases that the latter delay cell is exported, and export that the last one delay cell exported this is specific
The inversion signal of phase difference signal is as the feedback signal.
2. delay locked loop circuit as described in claim 1, which is characterized in that the Selecting phasing buffer includes：
One selector, is used to according to an enable signal, one of works as at most from the differential signal of multiple particular phases and selects
A selected phase difference signal out, wherein the selected phase difference signal includes a positive phase signals and an inversion signal.
3. delay locked loop circuit as claimed in claim 2, which is characterized in that the Selecting phasing buffer also includes：
One conversion module, for converting the positive phase signals for selecting phase difference signal and the inversion signal as a single-phase letter
Number the output frequency source.
4. delay locked loop circuit as described in claim 1, which is characterized in that the voltage-controlled delay route also includes a conversion
Module one of works as person for converting the input frequency source as input differential wave to multiple delay cell.
5. delay locked loop circuit as described in claim 1, which is characterized in that the delay locked loop circuit also includes one
Loop filter is coupled between the charge pump and the voltage-controlled delay route.
6. delay locked loop circuit as described in claim 1, which is characterized in that the detector includes a phase detectors,
For comparing the phase of the input frequency source and the feedback signal, one of work as person to generate at least one detection signal.
7. delay locked loop circuit as claimed in claim 6, which is characterized in that the detector also includes a frequency detecting
Device, it is another in at least one detection signal to generate for comparing the frequency of the input frequency source and the feedback signal
Person.
8. a kind of delay phase-lock technique, which is characterized in that include：
According to an input frequency source and a control voltage, multiple specific phases are generated by multiple delay cells and a phase selector
Position differential wave and a feedback signal；
At least one compare in the phase and frequency of the input frequency source and the feedback signal, to generate at least one detection
Signal；
The control voltage is generated according at least one detection signal；And
According to the differential signal of multiple particular phases, an output frequency source is generated by a Selecting phasing buffer；
Wherein the differential signal of each particular phases of the differential signal of multiple particular phases includes at least one positive phase signals and one
Inversion signal, and the feedback signal is the inversion signal for one of working as person for the differential signal of multiple particular phases；
It is multiple by multiple delay cell and phase selector generation wherein according to the input frequency source and the control voltage
The step of differential signal of particular phases and the feedback signal, include：
Multiple delay cell carries out repeatedly delay work, it is more to generate this according to the input frequency source and the control voltage
A differential signal of particular phases；And
The phase selector receives the differential signal of particular phases that the last one delay cell is exported in multiple delay cell,
And the inversion signal for the differential signal of the particular phases that the last one delay cell is exported is exported as the feedback signal；
Wherein multiple delay cell is coupled in series, and multiple delay cell connects the Selecting phasing buffer, and the phase
Digit selector is directly connected to last one in multiple delay cell.
9. delay phase-lock technique as claimed in claim 8, which is characterized in that receive in the differential signal of multiple particular phases
The person, and export the step of inversion signal of the differential signal of the particular phases is as the feedback signal, include：
According to an enable signal, one of works as at most from the differential signal of multiple particular phases and select a selected phase difference
Dynamic signal, wherein the selected phase difference signal includes a positive phase signals and an inversion signal；And
The positive phase signals for converting the selected phase difference signal and the inversion signal is the output frequencies of a monophasic pulses
Source.
10. as claimed in claim 8 delay phase-lock technique, which is characterized in that also be included in carry out the multiple delay work it
Before, the input frequency source is converted as an input differential wave, and is carried out the multiple delay work using the input differential wave and worked as
One of person.
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| CN101217277A (en) * | 2008-01-15 | 2008-07-09 | 凌阳科技股份有限公司 | A non-integer frequency difference eliminator and phase-lock loop that can product non-integer real-time clock signal |
| CN101917189A (en) * | 2005-02-03 | 2010-12-15 | 睦塞德技术公司 | The method and apparatus that is used for the initialization delay locking ring |
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| CN101917189A (en) * | 2005-02-03 | 2010-12-15 | 睦塞德技术公司 | The method and apparatus that is used for the initialization delay locking ring |
| CN101217277A (en) * | 2008-01-15 | 2008-07-09 | 凌阳科技股份有限公司 | A non-integer frequency difference eliminator and phase-lock loop that can product non-integer real-time clock signal |
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