CN103258792A - Groove-preferential dual-damascene copper-connection method reducing redundant metal coupling capacitance - Google Patents
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- CN103258792A CN103258792A CN2013101955744A CN201310195574A CN103258792A CN 103258792 A CN103258792 A CN 103258792A CN 2013101955744 A CN2013101955744 A CN 2013101955744A CN 201310195574 A CN201310195574 A CN 201310195574A CN 103258792 A CN103258792 A CN 103258792A
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Abstract
The invention provides a groove-preferential dual-damascene copper-connection method reducing redundant metal coupling capacitance. A medium layer is firstly deposited on a substrate silicon wafer, and then first photoresist is coated on the medium layer. A metal groove structure is formed in a first photoresist film through exposure and development, and the metal groove structure formed in the first photoresist penetrates through the first photoresist. In an identical development machine stand, a miniature auxiliary film is coated on the first photoresist to solidify the figure of the metal groove structure in the first photoresist, the miniature auxiliary film and the surface of the first photoresist is made to react through heating to form an isolating film not soluble in second photoresist, and then the miniature auxiliary film which does not react with the surface of the first photoresist and is left is removed. The second photoresist is coated on the first photoresist with the isolating film. A through hole structure arranged in the metal groove structure and a redundant metal groove structure arranged on the first photoresist are formed in the second photoresist through the exposure and the development.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of preferential layers for dual damascene copper interconnects method of groove that reduces redundant metal coupling capacitance.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled.Enter into after 130 nm technology node, be subjected to the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes the metal interconnected main flow that gets.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper conductor can not obtain by etching sheet metal as aluminum conductor.The manufacture method of the copper conductor that extensively adopts is the embedding technique that is called Damascus technics now.
Damascus mosaic texture copper-connection can be realized by the kinds of processes method.Wherein the preferential dual damascene process of groove is one of method that realizes plain conductor and through hole copper filling once-forming.Figure 1A-1E has showed the preferential dual damascene process flow process of groove.The low k value dielectric layer 2 of deposition at first on silicon substrate 1, at low k value dielectric layer 2 coatings first photoresist 3 (Figure 1A), by first photoetching with the first time etching with formation metallic channel 6 structures (Figure 1B) in low k value dielectric layer 2.At low k value dielectric layer 2 coating second photoresists 5 (Fig. 1 C).Form through hole 4 structures (Fig. 1 D) on metallic channel 6 structures by being etched in second photoetching and the second time.Continue follow-up metal deposition and metallochemistry mechanical lapping and finish lead metal 7 and via metal 8 fillings (Fig. 1 E).
In the metal level chemical mechanical milling tech, in order to reach uniform grinding effect, require the metallic pattern density on the silicon chip even as far as possible.And the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.The method that solves is to fill redundant metal 15(Fig. 1 F at the white space of domain) make domain pattern density homogenizing.Redundant metal has improved the uniformity of pattern density, but has introduced extra intermetallic coupling capacitance inevitably.In order to reduce the negative effect that extra coupling capacitance brings device, in the redundant filling quantity that will reduce redundant metal when metal filled as far as possible of design.
Electric capacity can be calculated by following formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.By above-mentioned formula as seen, the relative area of minimizing metal and increase intermetallic distance can reduce electric capacity.That is to say that the volume that reduces redundant metal can reduce owing to adding the extra intermetallic coupling capacitance that redundant metal is introduced.
The conventional method that reduces redundant metal need be introduced extra photomask or extra hard mask film in the Damascus technics stage, and two kinds of approach all need extra processing step, have prolonged Production Time, have increased cost of manufacture.
After the device size micro entered into 32 nm technology node, the single photolithographic exposure can't satisfy made the required resolution of intensive linear array figure.Double-pattern (double patterning) forming technique as the main method that solves this technical barrier by big quantity research and be widely used in making the intensive linear array figure of the following technology node of 32 nanometers.Fig. 2 A – 2E illustrates the process that the double-pattern forming technique is made intensive linear array figure.Make at needs on the silicon substrate 1 of intensive linear array figure, deposition substrate film 9 and hard mask 10 are coated with first photoresist 3 (Fig. 2 A), after exposure, development, the etching then, form first litho pattern 11 (Fig. 2 B) in hard mask 10, the characteristic size ratio of its lines and groove is 1:3.At this silicon chip coating second photoresist 5 (Fig. 2 C), exposure and the back of developing form second litho pattern 12 (Fig. 2 D) in second photoresist, 5 films, and the characteristic size ratio of its lines and groove also is 1:3, but its position and first litho pattern 11 are staggered.Continue to be etched in and form second litho pattern 12 (Fig. 2 E) that interlocks with first litho pattern 11 on the silicon substrate.The target lines have been formed in the combination of first litho pattern 11 and second litho pattern 11 and the trench features dimension scale is the intensive linear array figure of 1:1.
The double-pattern forming technique needs Twi-lithography and etching, i.e. photoetching-etching-photoetching-etching.Its cost is far longer than traditional single exposure forming technique.The cost that reduces the double-pattern forming technique becomes one of direction of new technology development.US Patent No. 20090142926 has been reported after first litho pattern 11 develops, in same developing machine platform, the method of first litho pattern 11 in first photoresist, 3 coating micro auxiliary film (SAFIER, Shrink Assist Film for Enhanced Resolution) curing, first photoresist 3.Double-pattern forming technology process after employing the method is photoetching (develop and solidify)-photoetching-etching.Omit first etch step in the former technology, thereby reduced the cost of double-pattern forming technique effectively.This method is also referred to as double-exposure technique.Micro auxiliary film (SAFIER, ShrinkAssist Film for Enhanced Resolution) is that Tokyo Applied Chemistry Industrial Co., Ltd. (TOK, TokyoOhka Kogyo) is for dwindling the commercial material of groove or hole pattern size exploitation.
Summary of the invention
Technical problem to be solved by this invention is at having above-mentioned defective in the prior art, a kind of preferential layers for dual damascene copper interconnects method of groove that can reduce redundant metal coupling capacitance being provided.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of preferential layers for dual damascene copper interconnects method of groove that reduces redundant metal coupling capacitance, it comprises:
First step: metallization medium layer at first on silicon substrate, subsequently at dielectric layer coating first photoresist;
Second step: form the metallic channel structure in first photoresist film by exposing and being developed in, wherein the metallic channel structure that forms in first photoresist penetrates first photoresist;
Third step: in the same developing machine platform identical with the development of second step, also heat to solidify metallic channel structure graph in first photoresist in first photoresist coating micro auxiliary film, wherein heating makes micro auxiliary film and the first photoresist surface reaction form the barrier film that is insoluble to second photoresist, and removing does not subsequently have the micro auxiliary film remaining with the first photoresist surface reaction;
The 4th step: be formed with first photoresist coating, second photoresist of barrier film;
The 5th step: by exposure be developed in second photoresist film to form and be in the through-hole structure in the metallic channel structure and be in redundant metallic channel structure on first photoresist;
The 6th step: second photoresist after utilization exposure and the development carries out preliminary etching, thereby in dielectric layer, form through hole and in first photoresist, form redundant metallic channel structure, remove second photoresist subsequently, the redundant metallic channel structure that wherein forms in first photoresist does not penetrate first photoresist;
The 7th step: utilize first photoresist that is formed with redundant metallic channel structure to continue etching, thereby form through hole, metallic channel and redundant metallic channel in dielectric layer, remove first photoresist subsequently, wherein the degree of depth of redundant metallic channel is less than the degree of depth of metallic channel;
The 8th step: carry out metal and deposit to finish filling vias, metallic channel and redundant metallic channel, carry out metallochemistry mechanical lapping subsequently to finish the filling of lead metal, via metal and redundant metal, wherein the thickness of lead metal is greater than the thickness of redundant metal.
Preferably, the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of described reduction also comprises:
The 9th step: thus the execution reduction processing partly or is fully removed the redundant metal than lead metal foil.
Preferably, first photoresist is the photoresist of silane-group containing (silyl), silicon alkoxyl (siloxyl) and cage type siloxanes (silsesquioxane).
Preferably, the anti-etching energy force rate of first photoresist and second photoresist is more than or equal to 1.5:1.
Preferably, in third step, the scope of the curing heating-up temperature of first photoresist be the first photoresist main body macromolecular material (the main body macromolecular material refers to the macromolecular material of mass percent maximum) vitrification point+/-30 ℃ preferably, in third step, the scope of curing heating time of first photoresist is 15 seconds to 300 seconds.Further preferred, in third step, the scope of curing heating time of first photoresist is 30 seconds to 120 seconds.
In the preferential layers for dual damascene copper interconnects method of groove of the redundant metal coupling capacitance of reduction according to the present invention, reduced the etch step in the metal interconnected technology of dual damascene, can improve production capacity effectively and reduce cost of manufacture; Enlarge follow-up lithographic process window effectively; Do not need extra hard mask film coating equipment or photomask, reduce or eliminate effectively because the metal level of redundant metal filled introducing is interior and the coupling capacitance of metal interlevel, further improve the performance of device.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed, will more easily more complete understanding be arranged and more easily understand its attendant advantages and feature the present invention, wherein:
Figure 1A to Fig. 1 F schematically shows the sectional view according to the preferential dual damascene process flow process of the groove of prior art.
Fig. 2 A to Fig. 2 E schematically shows the sectional view according to each step of the double-pattern forming technique of prior art.
Fig. 3 A to Fig. 3 I schematically shows the sectional view of each step of the preferential layers for dual damascene copper interconnects method of the groove that reduces redundant metal coupling capacitance according to the preferred embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear and understandable more, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Fig. 3 A to Fig. 3 I schematically shows the sectional view of each step of the preferential layers for dual damascene copper interconnects method of the groove that reduces redundant metal coupling capacitance according to the preferred embodiment of the invention.The preferential layers for dual damascene copper interconnects method of described groove is utilized double-exposure technique and the dura mater photoresist that can be shaped reduces redundant metal coupling capacitance.
Specifically, shown in Fig. 3 A to Fig. 3 I, the preferential layers for dual damascene copper interconnects method of groove that reduces redundant metal coupling capacitance according to the preferred embodiment of the invention comprises:
First step: on silicon substrate 1 at first metallization medium layer 2(preferably, dielectric layer 2 is low k value dielectric layers), be coated with first photoresist 3 at low k value dielectric layer 2 subsequently, as shown in Figure 3A.
Second step: form metallic channel 6 structures in first photoresist, 3 films by exposing and being developed in, wherein metallic channel 6 structures that form in first photoresist 3 penetrate first photoresist 3, shown in Fig. 3 B.
Third step: in the same developing machine platform identical with the development of second step, also heat to solidify metallic channel 6 structure graphs in first photoresist 3 in first photoresist, 3 coating micro auxiliary film (Resolution Enhancement Lithography Assisted byChemical Shrink), wherein heating makes micro auxiliary film and 3 surface reactions of first photoresist form the barrier film 13 that is insoluble to second photoresist 5, and removing does not subsequently have the micro auxiliary film remaining with 3 surface reactions of first photoresist.Specifically, remaining unnecessary micro auxiliary film can not removed with deionized water or the deionized water solution that contains surfactant with 3 surface reactions of first photoresist, shown in Fig. 3 C.
The 4th step: being formed with first photoresist, 3 coatings, second photoresist 5 of barrier film 13, shown in Fig. 3 D.
The 5th step: by exposure and be developed in second photoresist, 5 films form be in through hole 4 structures in metallic channel 6 structures and be on first photoresist 3 redundant metallic channel 14 structures (namely, redundant metallic channel 14 does not overlap with metallic channel 6), shown in Fig. 3 E.
The 6th step: second photoresist 5 after utilization exposure and the development carries out preliminary etching, thereby in low k value dielectric layer 2, form through hole 4 and in first photoresist 3, form redundant metallic channel 14 structures, remove second photoresist 5 subsequently, wherein redundant metallic channel 14 structures that form in first photoresist 3 do not penetrate first photoresist 3, shown in Fig. 3 F.
The 7th step: utilize first photoresist 3 that is formed with redundant metallic channel 14 structures to continue etching, thereby in low k value dielectric layer 2, form through hole 4, metallic channel 6 and redundant metallic channel 14, remove first photoresist 3 subsequently, wherein the degree of depth of redundant metallic channel 14 less than the degree of depth of metallic channel 6 (this be because, redundant metallic channel 14 structures that form in first photoresist 3 do not penetrate first photoresist 3, but metallic channel 6 structures that form in first photoresist 3 penetrate first photoresist 3), shown in Fig. 3 G.
The 8th step: carry out metal and deposit to finish filling vias 4, metallic channel 6 and redundant metallic channel 14, carry out metallochemistry mechanical lapping subsequently to finish the filling of lead metal 7, via metal 8 and redundant metal 15, shown in Fig. 3 H.Because the degree of depth of redundant metallic channel 14 is less than the degree of depth of metallic channel 6, so after metal filled, the thickness of lead metal 7 is greater than the thickness of redundant metal 15.
Preferably, can also carry out following the 9th step as required.
The 9th step: thus can further carry out reduction processing partly according to demand or remove the redundant metal 15 thinner than lead metal 7 fully, shown in Fig. 3 I, (wherein show the situation of removing redundant metal 15 fully).
Preferably, first photoresist 3 is selected the photoresist that can form dura mater for use; Further preferred, first photoresist 3 is photoresists of silane-group containing (silyl), silicon alkoxyl (siloxyl) and cage type siloxanes (silsesquioxane).
Preferably, the anti-etching energy force rate of first photoresist 3 and second photoresist 5 is more than or equal to 1.5:1.
Preferably, in third step, micro auxiliary film (the SAFIER that first photoresist 3 is solidified, Shrink Assist Film for Enhanced Resolution) be that Tokyo Applied Chemistry Industrial Co., Ltd. (TOK, Tokyo Ohka Kogyo) is for dwindling the commercial material of groove or hole pattern size exploitation.
Preferably, in third step, the scope of the curing heating-up temperature of first photoresist 3 is vitrification point+/-30 ℃ of first photoresist (3) main body macromolecular material (the main body macromolecular material refers to the macromolecular material of mass percent maximum).
Preferably, in third step, the scope of curing heating time of first photoresist 3 is 15 seconds to 300 seconds.Further preferred, in third step, the scope of curing heating time of first photoresist 3 is 30 seconds to 120 seconds.
In the preferential layers for dual damascene copper interconnects method of the groove that reduces redundant metal coupling capacitance according to the preferred embodiment of the invention, the preferential dual damascene metal interconnection of groove forming process comprises trench lithography-etching groove-steps such as through hole photoetching-via etch.Wherein etching groove and via etch are merged into a step etching, two step independent process of etching groove and via etch in the alternative former technology, and add the method that reduces redundant metal coupling capacitance, not only can reduce the cost of the preferential dual damascene metal interconnection of groove forming technology effectively, improve the production production capacity, and can further improve the performance of device.
Specifically, the preferential layers for dual damascene copper interconnects method of groove that reduces redundant metal coupling capacitance according to the preferred embodiment of the invention has following technique effect at least:
1) reduced etch step in the metal interconnected technology of dual damascene, can improve production capacity effectively and reduce cost of manufacture.
2) enlarge follow-up lithographic process window effectively.
3) do not need extra hard mask film coating equipment or photomask, reduce or eliminate effectively because the metal level of redundant metal filled introducing is interior and the coupling capacitance of metal interlevel, further improve the performance of device.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that though the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. preferential layers for dual damascene copper interconnects method of groove that reduces redundant metal coupling capacitance is characterized in that comprising:
First step: metallization medium layer at first on silicon substrate, subsequently at dielectric layer coating first photoresist;
Second step: form the metallic channel structure in first photoresist film by exposing and being developed in, wherein the metallic channel structure that forms in first photoresist penetrates first photoresist;
Third step: in the same developing machine platform identical with the development of second step, also heat to solidify metallic channel structure graph in first photoresist in first photoresist coating micro auxiliary film, wherein heating makes micro auxiliary film and the first photoresist surface reaction form the barrier film that is insoluble to second photoresist, and removing does not subsequently have the micro auxiliary film remaining with the first photoresist surface reaction;
The 4th step: be formed with first photoresist coating, second photoresist of barrier film;
The 5th step: by exposure be developed in second photoresist film to form and be in the through-hole structure in the metallic channel structure and be in redundant metallic channel structure on first photoresist;
The 6th step: second photoresist after utilization exposure and the development carries out preliminary etching, thereby in dielectric layer, form through hole and in first photoresist, form redundant metallic channel structure, remove second photoresist subsequently, the redundant metallic channel structure that wherein forms in first photoresist does not penetrate first photoresist;
The 7th step: utilize first photoresist that is formed with redundant metallic channel structure to continue etching, thereby form through hole, metallic channel and redundant metallic channel in dielectric layer, remove first photoresist subsequently, wherein the degree of depth of redundant metallic channel is less than the degree of depth of metallic channel;
The 8th step: carry out metal and deposit to finish filling vias, metallic channel and redundant metallic channel, carry out metallochemistry mechanical lapping subsequently to finish the filling of lead metal, via metal and redundant metal, wherein the thickness of lead metal is greater than the thickness of redundant metal.
2. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 is characterized in that also comprising:
The 9th step: thus the execution reduction processing partly or is fully removed the redundant metal than lead metal foil.
3. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 and 2, it is characterized in that the deionized water solution that utilizes deionized water or contain surfactant in third step is removed not the micro auxiliary film remaining with the first photoresist surface reaction.
4. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 and 2 is characterized in that, first photoresist is the photoresist of silane-group containing, silicon alkoxyl and cage type siloxanes.
5. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 and 2 is characterized in that, the anti-etching energy force rate of first photoresist and second photoresist is more than or equal to 1.5:1.
6. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 and 2, it is characterized in that, in third step, the scope of the curing heating-up temperature of first photoresist is vitrification point+/-30 ℃ of the first photoresist main body macromolecular material.
7. the preferential layers for dual damascene copper interconnects method of the groove of the redundant metal coupling capacitance of reduction according to claim 1 and 2 is characterized in that, in third step, the scope of curing heating time of first photoresist is 15 seconds to 300 seconds; Preferably, the scope of curing heating time of first photoresist is 30 seconds to 120 seconds.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116013853A (en) * | 2023-03-27 | 2023-04-25 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
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| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| CN102446827A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Manufacture process of removing redundant metal filling of metal layer |
| CN102446825A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Manufacturing technology for removing redundant metal filler of metal layer |
| CN102810510A (en) * | 2012-09-11 | 2012-12-05 | 上海华力微电子有限公司 | Method for manufacturing copper interconnection |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| CN102446827A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Manufacture process of removing redundant metal filling of metal layer |
| CN102446825A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Manufacturing technology for removing redundant metal filler of metal layer |
| CN102810510A (en) * | 2012-09-11 | 2012-12-05 | 上海华力微电子有限公司 | Method for manufacturing copper interconnection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116013853A (en) * | 2023-03-27 | 2023-04-25 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
| CN116013853B (en) * | 2023-03-27 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for preparing interconnection structure |
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Application publication date: 20130821 |