CN103257926A - A method carried by a serial flash memory and a memorizer controller in a property enhancement mode - Google Patents
A method carried by a serial flash memory and a memorizer controller in a property enhancement mode Download PDFInfo
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Abstract
The invention relates to a method carried out by a serial flash memory and a memorizer controller in a property enhancement mode. The method carried by a serial flash memory in the property enhancement mode comprises: timing is performed for an enabled stage, a serial chip selection line maintaining the enabled state continuously in the enabled stage; if the enabled stage is longer than the period of the threshold number of clock signals on a serial clock line, the information received from the memorizer controller through a serial input/output line serves as omitting order read instructions in the enabled stage; and if the enabled stage is equal to or shorter than the period of the threshold number of clock signals on the serial clock line, the information received from the memorizer controller through the serial input/output line serves as non-read instructions in the enabled stage. The method carried by the serial flash memory and the memorizer controller in the property enhancement mode can save time and can help improve property.
Description
Technical field
The present invention is relevant for serial flash (serial flash memory), and is particularly to strengthen the method for serial flash performance.
Background technology
Paralleling flash memory (parallel flash memory) and serial flash are two kinds of different flash memories.Normally, compare with paralleling flash memory, serial flash generally has less pin (pin), and (Printed Circuit Board takies less area on PCB), consumes less electric weight, is easier to control, and can reduces the total system cost at printed circuit board (PCB).Therefore, serial flash is widely used in various electronic installations, and it comprises portable electronic devices, for example mobile phone, desktop PC, portable multimedia player, handheld game device or other devices.
Yet except above-mentioned advantage, the read or write speed of serial flash is more common relatively.Especially, when serial flash is arranged in the electronic installation that needs high data bandwidths (high data bandwidth), These characteristics will become adverse condition.In order to be fit to above-mentioned electronic installation, serial flash must effectively operate to improve data throughout and reduce time delay.
Summary of the invention
In view of this, the invention provides a kind of method of under the performance enhancement mode, being carried out by serial flash and Memory Controller.
A kind of method of under the performance enhancement mode, being carried out by serial flash, wherein this serial flash selects line and many serial input/output lines to link to each other with Memory Controller by at least one serial time clock line, a serial chip, should be under the performance enhancement mode method of carrying out of serial flash comprise: the activation stage is carried out timing, wherein selects line to continue to maintain enabled status at this serial chip of this activation stage; If this activation stage greater than the cycle of the threshold number of the clock signal on this serial time clock line, then will read instruction as omitting order from the information that this Memory Controller receives by this serial input/output line in this activation stage; And if this activation stage be equal to or less than the cycle of this threshold number of this clock signal on this serial time clock line, then will read instruction as non-from the information that this Memory Controller receives by this serial input/output line in this activation stage.
A kind of method of under the performance enhancement mode, being carried out by Memory Controller, wherein this Memory Controller is by at least one serial time clock line, article one, serial chip selects line and many serial input/output lines to link to each other with serial flash, being somebody's turn to do the method that Memory Controller is carried out under the performance enhancement mode comprises: send the omission order to this serial flash if desired and read instruction, then select line to maintain enabled status this serial chip in the first activation stage, and send this omissions order in this first activation stage by this this serial flash of serial I/O alignment and read instruction; And send non-reading instruction to this serial flash if desired, then select line to maintain this enabled status this serial chip in the second activation stage, and send this non-reading instruction in this second activation stage by this serial flash of this serial I/O alignment.。
The method of being carried out by serial flash and Memory Controller under the performance enhancement mode provided by the invention can be saved time and be helped to improve performance.
Description of drawings
Fig. 1 describes in order to implement the memory module synoptic diagram of the inventive method.
Fig. 2 is in the method synoptic diagram of being carried out by Memory Controller 120 under the performance enhancement mode when memory module 100.
Fig. 3 is in the method synoptic diagram of being carried out by serial flash 140 under the performance enhancement mode when memory module 100.
Fig. 4 is the sequential chart of two schematic operation being carried out by memory module 100 under general performance enhancement mode.
Fig. 5 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the SPI pattern in performance.
Fig. 6 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the quaternary SPI pattern in performance.
Fig. 7 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the QPI pattern in performance.
Embodiment
In the middle of instructions and claims, used some vocabulary to censure specific element.The person of ordinary skill in the field should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book not with the difference of title as the mode of distinguishing element, but with the difference of element on function as the criterion of distinguishing.Be an open term mentioned " comprising " in instructions and the claim item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device if describe first device in the literary composition, then represent first device and can directly be electrically connected in second device, or be electrically connected to second device indirectly through other device or connection means.
Ensuing description is about embodiments of the invention, and it is in order to describe ultimate principle of the present invention, not as limitation of the present invention.Protection scope of the present invention is made by claims and being defined.
Fig. 1 describes in order to implement the memory module synoptic diagram of the inventive method.The memory module 100 of present embodiment comprises Memory Controller 120 and serial flash 140.Though be not described the driver that serial flash 140 can comprise memory array and be controlled access memory array by Memory Controller 120.Memory module 100 is contained in the electronic installation, thus make electronic installation other assemblies (for example processor) but storage space that access memory module 100 provides.In this example, Memory Controller 120 is thought processor control and access serial flash 140 as the center section of processor and serial flash 140.
In order to illustrate that better the present invention, Fig. 1 have omitted device and the assembly irrelevant with present embodiment.Further, ensuing paragraph will mainly illustrate present embodiment, i.e. interconnecting parts between Memory Controller 120, serial flash 140 and two assemblies.
Memory Controller 120 passes through serial clock (Serial Clock at least with serial flash 140, SCK) line, serial chip are selected (Serial Chip Select, SCS) line and many serial I/O (Serial Input/Output, SIO) line interconnection.The SCK line allows Memory Controller 120 to send the SCK signal with the running of synchronous two assemblies to serial flash 140.The SCS line also can be described as serial chip activation (Serial Chip Enable, SCE) line, it allows Memory Controller 120 to send the SCS signal to serial flash, thereby when can and when cannot communicate between notice serial flash 140 above-mentioned two assemblies.For example, Memory Controller 120 can switch the SCS signal between two states, and above-mentioned state comprises enabled status (enabled state) and disabled state (disabled state).Enabled status can be low-voltage state, its indication allow Memory Controller 120 its with serial flash 140 between communicate by letter.Disabled state can be high-voltage state, its indication do not allow Memory Controller 120 its with serial flash 140 between communicate by letter.
Each bar SIO line can be unidirectional line (unidirectional line) or bidirectional lines (bidirectional line), and wherein unidirectional line is from Memory Controller 120 to serial flash 140 or opposite.In other words, the SIO line can be serial input line, serial output line or serial input/output line.In the present embodiment, have 4 SIO lines, comprise SIO[0] line, SIO[1] line, SIO[2] line, SIO[3] line.If 100 of memory modules are supported peripheral interface (the Serial Peripheral Interface of serial, SPI) pattern, dual input/output (Dual Input/Output, Dual-IO) pattern, dual output (Dual-Output) pattern or its combination, then at SIO[2] line and SIO[3] when line keeps not active state, SIO[0] line and SIO[1] line can operate to implement read operation simultaneously.If memory module 100 is supported the peripheral interface (SPI-Quad) of quaternary serial pattern, (then four SIO lines can operate to implement read operation simultaneously for Quad Peripheral Interface, QPI) pattern or its combination at quaternary peripheral interface.
A feature of memory module 100 is that it has performance enhancement mode (performance-enhanced mode), also can be described as continuous reading mode (continuous read mode).Because Memory Controller 120 is formed memory module 100 with serial flash 140, so no matter any one in above-mentioned three is in AD HOC, other two also are in this AD HOC.
Under above-mentioned performance enhancement mode, Memory Controller 120 can order read instruction (command-omitted read instruction) to make serial flash 140 carry out read operations by sending to serial flash 140 to omit.Read instruction and comprise the address section because omit order, do not comprise the order section, so it namely comprises the weak point that reads instruction that the order section comprises the address section again than common.In response, serial flash 140 will be carried out the read operation based on above-mentioned address.In other words, under the performance enhancement mode, even serial flash 140 does not in fact receive read command, but its each address from Memory Controller 120 receptions of serial flash 140 hypothesis all is associated with read command.
To be in the instruction of the most frequent issue because read instruction, can to save 100 a lot of times of memory module and increase substantially its performance so each that allows not comprise the order section reads instruction.For example, if the length of the common order section that reads instruction is 8 and memory module 100 is in that performance strengthens the SPI pattern, performance strengthens quaternary SPI pattern or performance strengthens under the dual output pattern, each read operation can be memory module 100 and saves and be equivalent to the SCK signal time in 8 cycles.If the length of the common order section that reads instruction is 8 and memory module 100 to be in performance and to strengthen under dual input/output mode, each read operation can be memory module 100 and saves and be equivalent to the SCK signal time in 4 cycles.If the length of the common order section that reads instruction is 8 and memory module 100 to be in performance and to strengthen under the QPI pattern, each read operation can be memory module 100 and saves and be equivalent to the SCK signal time in 2 cycles.Even (double-data-rate sends 8 long orders under situation DDR), memory module 100 still can be saved above-mentioned half time in double data rate (DDR).When the electronic installation with memory module 100 needed high data bandwidth, the time of above-mentioned saving was very useful.
For Memory Controller 120, exist several modes that memory module 100 is converted into the performance enhancement mode from general mode.General mode can be common SPI pattern, common quaternary SPI pattern, common Q PI pattern, common double I/O pattern or common double output mode; The performance enhancement mode can be performance and strengthens SPI pattern, performance enhancing quaternary SPI pattern, performance enhancing QPI pattern, performance enhancing dual input/output mode or performance enhancing dual output pattern; Any common and performance enhancement mode all allows the DDR transmission.For example, in general mode, Memory Controller 120 can by send to serial flash 140 particular commands, by writing serial flash 140 the state register machine or by in the dummy instruction cycle (dummy cycle) or be sent to that placement certain bits type makes memory module 100 enter the performance enhancement mode in the pattern bit period (mode-bit cycle) of the signal of serial flash 140.Similarly, Memory Controller 120 can utilize a kind of in the said method that memory module 100 is transformed back into general mode from the performance enhancement mode.
As above-mentioned, an advantage of performance enhancement mode is that it allows to use the omission order to read instruction to strengthen and reads performance.Another advantage of performance enhancement mode is not cause at first that memory module 100 leaves under the situation of performance enhancement mode, Memory Controller 120 can be to serial flash 140 issue a plurality of non-reading instruction (non-read instruction), and wherein non-reading instruction comprises other orders except read command.Inevitably, the operation that enters and leave the performance enhancement mode will take some times and consume portion of energy.In addition, after returning general mode, memory module 100 can not be saved time under read operation.Therefore, issue non-read instruction by permission Memory Controller 120 to serial flash 140 when memory module 100 still is under the performance enhancement mode, present embodiment can further strengthen the performance of memory module 100 and reduce its energy consumption.
Fig. 2 is in the method synoptic diagram of being carried out by Memory Controller 120 under the performance enhancement mode when memory module 100.For fear of digressing from the subject, this figure does not describe the step relevant with entering and leave the performance enhancement mode, does not comprise the step irrelevant with the performance enhancement mode simultaneously yet.
In step 210, Memory Controller 120 maintains disabled state with the SCS line.Then, in step 220, Memory Controller 120 determines whether need to serial flash 140 issuing commands.If answer is for being that then Memory Controller 120 enters step 230.Otherwise it turns back to step 210.
In step 230, Memory Controller 120 determines which kind of instruction it need issue.Particularly, Memory Controller 120 determines that the instruction of issue also is non-reading instruction for the omission order reads instruction.Read instruction if Memory Controller 120 needs issue to omit order, then it enters step 240.If Memory Controller 120 needs non-the reading instruction of issue, then enter step 250.
In step 240, Memory Controller 120 switches to the SCS line enabled status and in the first activation stage it is maintained enabled status, and reads instruction by the 140 transmission omission orders of SIO alignment serial flash in the first activation stage.Omit the order read operation in order to provide, the first activation stage is greater than the cycle of the threshold number of SCK signal.Therefore, the length in the first activation stage shows to serial flash 140 that Memory Controller 120 is being issued and omits order and read instruction rather than non-reading instruction.
Particularly, in step 240, the beginning in the first activation stage does not at first send under the situation of read command, and Memory Controller 120 directly sends the address by SIO alignment serial flash 140.Then, after the cycle and before the end of the first activation stage, Memory Controller 120 receives data by the SIO line from serial flash 140 in several dummy instruction.These data are to be obtained from particular address by serial flash 140.After step 240, by being switched back disabled state Memory Controller 120, the SCS line is back to step 210.
On the other hand, if Memory Controller 120 needs non-the reading instruction of issue, then in step 250, Memory Controller 120 switches to the SCS line enabled status and in the second activation stage it is maintained enabled status, and sends non-reading instruction in this second activation stage by SIO alignment serial flash 140.Because the second activation stage only need adapt to non-reading instruction, it orders the weak point that reads instruction than omitting, so the second activation stage was equal to or less than the cycle of the threshold number of above-mentioned SCK signal.Therefore, the length in the second activation stage will show to serial flash 140, Memory Controller 120 issuing non-read instruction rather than omit order read instruction.After step 250, Memory Controller 120 returns step 210 by the SCS line is switched back disabled state.
In the present embodiment, the threshold number of SCK signal period can be equal to or less than and omit address and the number in dummy instruction cycle that order reads instruction.As another example, the threshold number of SCK signal period can be equal to or less than omits the number of ordering the address cycle that reads instruction.Because the non-read command that can hold altogether must be equal to or less than the cycle of the threshold number of SCK signal, so the number of the non-read command that the threshold number influence can be held altogether.
Fig. 3 is in the method synoptic diagram of being carried out by serial flash 140 under the performance enhancement mode when memory module 100.For fear of digressing from the subject, this figure does not describe the step relevant with entering and leave the performance enhancement mode, does not comprise the step irrelevant with the performance enhancement mode simultaneously yet.
At first, in step 310, the state of serial flash 140 monitoring SCS lines.Then, in step 320, serial flash 140 determines whether the SCS line switches to enabled status from disabled state.If answer is for being that then serial flash 140 enters step 330.Otherwise if the SCS line maintains disabled state, then serial flash 140 returns step 310.
After the SCS line had switched to enabled status, in step 330,140 pairs of SCS signals of serial flash continued to maintain the time in activation stage and carry out timing (count).In step 340, the cycle of the length in 140 comparison activation stages of serial flash and the threshold number of above-mentioned SCK signal.If the SCS signal is to maintain enabled status and the first activation stage greater than the cycle of the threshold number of SCK signal in the first activation stage, then serial flash 140 determines that Memory Controllers 120 just omit order in the issue of the first activation stage and read instruction.In response, serial flash 140 enters step 350.On the other hand, if the SCS signal is to maintain the cycle that enabled status and the second activation stage are equal to or less than the threshold number of SCK signal in the second activation stage, then serial flash 140 determines that Memory Controllers 120 are just non-the reading instruction of second activation stage issue.In response, serial flash 140 enters step 360.
In step 350, serial flash 140 will read instruction as omitting order from the information that Memory Controller 120 receives by the SIO line in the first activation stage.As above-mentioned, omit order and read instruction and comprise the address section but do not comprise the order section.Then, serial flash 140 execution are based on the read operation of this address.Then, before Memory Controller 120 switched back disabled state with the SCS signal, serial flash 140 was sent to Memory Controller 120 by the data that the SIO line will obtain from this address.Afterwards, serial flash 140 is back to step 310 and waits for that the SCS line switches to enabled status again.
Fig. 4 is the sequential chart of two schematic operation being carried out by memory module 100 under general performance enhancement mode.Particularly, last chart is described and is omitted the order read operation; Following chart is described non-read operation.In these two examples, parameter m, n and k are illustrated respectively in number, the number in dummy instruction cycle and the number in data cycle that omits address cycle in the order read operation.
In these two examples, threshold value is (m+n) the at the most individual cycle of SCK signal.In last chart, because the activation stage is greater than the cycle of the threshold number of SCK signal, so serial flash 140 will pass through SIO[3:0] information that receives from Memory Controller 120 of line is as the address that is used for read operation.In response, serial flash 140 obtains data from particular address, then passes through SIO[3:0 before the activation stage finishes] alignment Memory Controller 120 sends the data of having obtained.Because in this read operation, omitted read command, so this read operation is than the common read operation cost less time.
On the other hand, in following chart, the activation stage is less than the cycle of the threshold number of SCK signal.Therefore, serial flash 140 will pass through SIO[3:0] information that receives from Memory Controller 120 of line is as non-read command.Then, serial flash 140 is correspondingly carried out non-read command.
Several example model of serial flash allow the number (being the value of n) in the dummy instruction cycle of each read operation of adjustment, for example, adjust between 4 and 18.In other words, the value of n can reach 18.And, strengthening under the SPI pattern in performance, m can be 24.Therefore, above-mentioned threshold value can be 24 and 18 with 42 or littler value.Because utilize SIO[3:0 only] in the line one, for example SIO[0 just] line, transmit non-read command, so the maximum length of the non-read command that can hold altogether is 42.Strengthen under the quaternary QPI pattern in performance, m can be 6.Therefore, this threshold value can be 6 and 18 with 24 or littler value.Because all 4 SIO[3:0] line all can be used for transmitting non-read command, so the maximum length of the non-read command that can hold altogether is 96.
Fig. 5 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the SPI pattern in performance.Under this pattern, 120 of Memory Controllers utilize SIO[0] alignment serial flash 140 sends order and addresses, and 140 of serial flash utilize SIO[1] alignment Memory Controller 120 sends it back data.As shown in the figure, strengthen under the SPI pattern in performance, above-mentioned parameter m, n and k can be respectively 24,18 and 16.In addition, threshold value can be 24 and 18 both with 42.
Fig. 6 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the quaternary SPI pattern in performance.Under this pattern, 120 of Memory Controllers utilize SIO[0] alignment serial flash 140 sends order and utilizes all four SIO[3:0] alignment serial flash 140 sends addresses.And serial flash 140 utilizes all four SIO[3:0] alignment Memory Controller 120 sends it back data.As shown in the figure, strengthen under the quaternary SPI pattern in performance, above-mentioned parameter m, n and k can be respectively 6,18 and 4.In addition, threshold value can be 6 and 18 both with 24.
Fig. 7 is the sequential chart that strengthens two schematic operation being carried out by memory module 100 under the QPI pattern in performance.Under this pattern, Memory Controller 120 utilizes all four SIO[3:0] alignment serial flash 140 sends order and addresses, and serial flash 140 utilizes all four SIO[3:0] alignment Memory Controller 120 sends it back data.As shown in the figure, strengthen under the QPI pattern in performance, above-mentioned parameter m, n and k can be respectively 6,18 and 4.In addition, threshold value can be 6 and 18 both with 24.Though Fig. 7 is similar to Fig. 6, the bit length of the non-read command among Fig. 7 can be four times of bit length of the non-read command among Fig. 6.
As mentioned above, in omitting the order read operation, threshold value also can be equal to or less than m, i.e. the number of address cycle, and be not subjected to the influence of the value of n.For example, strengthen under the dual output pattern in performance, m can be 24.Therefore, threshold value can be 24 or littler value.Because utilize SIO[3:0 only] in the line one, for example SIO[0] line, transmit non-read command, so the maximum length of the non-read command that can hold altogether is 24, i.e. the length of 3 bytes.Strengthen under dual input/output mode in performance, m can be 12.Therefore, threshold value can be 12 or littler value.Because can utilize SIO[3:0] in the line two, for example SIO[0] line and SIO[1] line, transmit non-read command, so the maximum length of the non-read command that can hold altogether is 24, i.e. the length of 3 bytes.
If memory module 100 operates under double data rate (DDR), for example double the frequency of SCK signal, above-mentioned threshold value can be further except 2.
Above-described embodiment allows to utilize under the performance enhancement mode omission order to read instruction to strengthen and reads performance.And embodiment allows Memory Controller 120 to non-the reading instruction of serial flash 140 issue, and it takes place causing at first that not memory module is left under the situation of performance enhancement mode.Therefore, above-described embodiment is read performance and is reduced its time to strengthen the performance of whole memory module 100 by improving it.
Though the present invention discloses as above with preferred embodiment, but it is not in order to limiting scope of the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention, does variation and the modification of equalization, all belongs to covering scope of the present invention.
Claims (17)
1. method of under the performance enhancement mode, being carried out by serial flash, wherein this serial flash selects line and many serial input/output lines to link to each other with Memory Controller by at least one serial time clock line, a serial chip, is somebody's turn to do the method that serial flash is carried out under the performance enhancement mode and comprises:
The activation stage is carried out timing, wherein select line to continue to maintain enabled status at this serial chip of this activation stage;
If this activation stage greater than the cycle of the threshold number of the clock signal on this serial time clock line, then will read instruction as omitting order from the information that this Memory Controller receives by this serial input/output line in this activation stage; And
If this activation stage is equal to or less than the cycle of this threshold number of this clock signal on this serial time clock line, then will read instruction as non-from the information that this Memory Controller receives by this serial input/output line in this activation stage.
2. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this threshold number is equal to or less than address and the number in dummy instruction cycle that this omission order reads instruction.
3. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this threshold number is equal to or less than the number of the address cycle that this omissions order reads instruction.
4. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of serial, and this threshold number is equal to or less than 42.
5. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of quaternary serial, and this threshold number is equal to or less than 24.
6. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of quaternary, and this threshold number is equal to or less than 24.
7. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this performance enhancement mode is that performance strengthens the dual output pattern, and this threshold number is equal to or less than 42.
8. the method for being carried out by serial flash under the performance enhancement mode as claimed in claim 1 is characterized in that, this performance enhancement mode is that performance strengthens dual input/output mode, and this threshold number is equal to or less than 30.
9. method of under the performance enhancement mode, being carried out by Memory Controller, wherein this Memory Controller selects line and many serial input/output lines to link to each other with serial flash by at least one serial time clock line, a serial chip, is somebody's turn to do the method that Memory Controller is carried out under the performance enhancement mode and comprises:
Send to omit to order to this serial flash if desired and read instruction, then select line to maintain enabled status this serial chip in the first activation stage, and send this omissions order in this first activation stage by this this serial flash of serial I/O alignment and read instruction; And
Send non-reading instruction to this serial flash if desired, then select line to maintain this enabled status this serial chip in the second activation stage, and send this non-reading instruction in this second activation stage by this serial flash of this serial I/O alignment.
10. the method for under the performance enhancement mode, being carried out by Memory Controller as claimed in claim 9, it is characterized in that, this first activation stage is greater than the cycle of the threshold number of the clock signal on this serial time clock line, and this second activation stage is equal to or less than the cycle of this threshold number of this clock signal on this serial time clock line.
11. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this threshold number is equal to or less than address and the number in dummy instruction cycle that this omission order reads instruction.
12. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this threshold number is equal to or less than the number of the address cycle that this omissions order reads instruction.
13. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of serial, and this threshold number is equal to or less than 42.
14. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of quaternary serial, and this threshold number is equal to or less than 24.
15. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this performance enhancement mode is that performance strengthens the peripheral interface model of quaternary, and this threshold number is equal to or less than 24.
16. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this performance enhancement mode is that performance strengthens the dual output pattern, and this threshold number is equal to or less than 42.
17. the method for being carried out by Memory Controller under the performance enhancement mode as claimed in claim 10 is characterized in that, this performance enhancement mode is that performance strengthens dual input/output mode, and this threshold number is equal to or less than 30.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| IN564CH2012 | 2012-02-15 | ||
| IN564/CHE/2012 | 2012-02-15 |
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| CN (1) | CN103257926B (en) |
| BR (1) | BR102012011617A2 (en) |
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| CN106796560A (en) * | 2014-09-26 | 2017-05-31 | 英特尔公司 | Method, apparatus and system for managing implicit precharge command signaling |
| CN107507638A (en) * | 2016-06-14 | 2017-12-22 | 爱思开海力士有限公司 | Data storage device and its operating method |
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2012
- 2012-04-30 BR BRBR102012011617-0A patent/BR102012011617A2/en not_active Application Discontinuation
- 2012-05-22 CN CN201210160462.0A patent/CN103257926B/en not_active Expired - Fee Related
- 2012-05-24 TW TW101118494A patent/TWI470642B/en not_active IP Right Cessation
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| US7793031B2 (en) * | 2005-09-09 | 2010-09-07 | Laura Sartori | Memory architecture with serial peripheral interface |
| CN101828175A (en) * | 2007-10-17 | 2010-09-08 | 美光科技公司 | System and method for setting access and modification for synchronous serial interface NAND |
| CN101828174A (en) * | 2007-10-17 | 2010-09-08 | 美光科技公司 | System and method for data read of a synchronous serial interface NAND |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106796560A (en) * | 2014-09-26 | 2017-05-31 | 英特尔公司 | Method, apparatus and system for managing implicit precharge command signaling |
| CN106796560B (en) * | 2014-09-26 | 2019-08-23 | 英特尔公司 | For managing the method, apparatus and system of implicit precharge command signaling |
| CN107507638A (en) * | 2016-06-14 | 2017-12-22 | 爱思开海力士有限公司 | Data storage device and its operating method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI470642B (en) | 2015-01-21 |
| CN103257926B (en) | 2016-04-06 |
| TW201333969A (en) | 2013-08-16 |
| BR102012011617A2 (en) | 2013-11-05 |
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