CN103248217A

CN103248217A - Low-power dissipation FPGA (Field Programmable Gate Array) power supply

Info

Publication number: CN103248217A
Application number: CN2013101803351A
Authority: CN
Inventors: 张堃; 张才坤; 王勋; 熊昊
Original assignee: Northwestern Polytechnical University
Current assignee: Northwestern Polytechnical University
Priority date: 2013-05-15
Filing date: 2013-05-15
Publication date: 2013-08-14

Abstract

The invention provides a low-power dissipation FPGA (Field Programmable Gate Array) power supply. The output power of a high-power power supply system meets the starting of an FPGA and the loading of a program, and the output power of a low-power power supply system maintains the normal work of the low-power dissipation FPGA; the power supply input of the high-power power supply system is controlled through an enabling switch by a power supply main control module; an I/O (Input/Output) pin of the FPGA is connected with the power supply main control module; the power supply main control module controls the enabling switch through a feedback signal of the FPGA during normal working to realize the working state switching of the high-power power supply system; and meanwhile a power supply supplies power for the low-power power supply system. The output current is smaller, the power dissipation is small, the weight is light, the normal starting of the FPGA and the loading of the program can be ensured, and at the same time the working power dissipation of the FPGA power supply system can be reduced.

Description

The low-power consumption FPGA power supply

Technical field

The present invention relates to a kind of FPGA electric supply installation.

Background technology

FPGA needed supply current when moment starts is estimated to reach about 2A.When generally designing the FPGA power supply, often be the reference design power supply with the maximum current, realize the power supply plan of FPGA.Traditional electric power system scheme is that standard designs with the required power consumption that starts power supply usually, but because that FPGA enters after the operate as normal needed power consumption is just very little, cause electric power system power consumption after the FPGA startup is finished bigger like this, make under some special occasions, as aerospace field etc., electric power system finite energy, the electric power system of traditional design just are difficult to maintain the work use of FPGA.If the electric power system power output of design is less, can not satisfy the normal startup of FPGA and the loading of program.Therefore, a cover guarantees the low-power consumption power supply design of FPGA operate as normal, will alleviate the power-supply system burden greatly.

Summary of the invention

In order to overcome the deficiencies in the prior art, the invention provides a kind of low-power consumption FPGA power supply, the FPGA electric power system is divided into two parts, a part of electric power system is the startup electric power system of FPGA, be characterized in that electric current and power consumption thereof are bigger, can satisfy the normal startup of FPGA and the loading of program; Another part electric power system is the work electric power system of FPGA, and its characteristics are that output current is less, power consumption is little, in light weight.This programme can reduce the work power consumption of FPGA electric power system when guaranteeing that the normal startup of FPGA and program thereof load.

The technical solution adopted for the present invention to solve the technical problems is: comprise high power electric power supply system, small-power electric power system and power supply main control module.Described high power electric power supply system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and power output can satisfy the startup of FPGA and the loading of program; Described small-power electric power system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and power output can be kept the demand of low-power consumption FPGA operate as normal; The power supply main control module is by the power supply input of enable switch control high power electric power supply system; The I/O pin of FPGA connects the power supply main control module, and the power supply main control module is realized the conversion of operation state of high power electric power supply system by the feedback signal control enable switch of FPGA operate as normal; Power supply is the power supply of small-power electric power system simultaneously.

The invention has the beneficial effects as follows: scheme proposed by the invention satisfies FPGA and starts work requirements and reduce energy consumption in the power supply process.The present invention is in conjunction with the characteristics of the required power consumption process of the whole initial work of FPGA, and it is high power electric power supply system circuit, small-power electric power system circuit and feedback control circuit that the electric power system of FPGA is divided into.High power electric power supply system can satisfy FPGA and start power supply, and the small-power electric power system can satisfy the operate as normal power supply of FPGA, controls the operating state of high power electric power supply system simultaneously by feedback control circuit, with the power consumption of low electric power system.

Description of drawings

Fig. 1 is the invention process block diagram.

Fig. 2 is embodiment side circuit connection layout.

Embodiment

The present invention is further described below in conjunction with drawings and Examples.

The characteristics of low-power consumption FPGA power supply method for designing are to comprise high power electric power supply system circuit, small-power electric power system circuit, feedback control circuit.Its high power electric power supply system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and the power of designing requirement output can satisfy the startup of FPGA and the loading of program.The small-power electric power system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and designing requirement can be kept the demand of low-power consumption FPGA operate as normal for the power of output.The power supply main control module is by the power supply input of enable switch control high power electric power supply system.The feedback control circuit design is that FPGA passes through I/O pin connection power supply main control module, and the power supply main control module is realized the conversion of operation state of high power electric power supply system by the feedback signal control enable switch of FPGA operate as normal.The master control power supply powers on for simultaneously two electric power systems simultaneously, after the FPGA operate as normal working state signal fed back to the master control power module, the master control power module passes through enable switch, close high power electric power supply system, only make the small-power electric power system give the FPGA power supply of operate as normal, reduced the power consumption of whole FPGA electric power system like this.

Referring to Fig. 1, it is high power electric power supply system circuit, small-power electric power system circuit and feedback control circuit that the present invention is divided into the electric power system of FPGA.Its high power electric power supply system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and the power of designing requirement output can satisfy the startup of FPGA and the loading of program.The small-power electric power system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and designing requirement can be kept the demand of low-power consumption FPGA operate as normal for the power of output.The master control power module is controlled the operating state of high power electric power supply system by the feedback signal of FPGA operating state.The master control power supply powers on for simultaneously two electric power systems simultaneously, after the FPGA operate as normal working state signal fed back to the master control power module, the master control power module is closed high power electric power supply system by enable switch, only makes the small-power electric power system give the FPGA power supply of operate as normal.

This method is implemented structure for adopting the TPS54612 of TI company, TPS70302, TPS71825-12, FPGA and the master control power module of 4 chips such as TPS73133 and altera corp.Wherein, the electric power system that the high power electric power supply system circuit adopts TPS54612 chip and TPS70302 chip to make up, the electric power system that small-power electric power system circuit adopts TPS71825-12 chip and TPS73133 chip to make up, FPGA links to each other with the I/O of power supply main control module and constitutes feedback circuit.The power demand when electric power system that wherein adopts TPS54612 chip and TPS70302 chip to make up can satisfy the FPGA startup, the TPS54612 chip will import+the 5V voltage transitions realizes the power supply of FPGA kernel for 1.2V voltage, chip TPS70302 general+5V voltage transfers to+2.5V voltage and+3.3V voltage realization FPGAI/O confession.The power supply of adopting TPS71825-12 chip and the constructed small-power electric power system of TPS73133 chip can satisfy the FPGA operate as normal is used, chip TPS71825-12 general+5V voltage transitions is+1.2V and+2.5V voltage realizes FPGA kernel and I/O confession electricity, chip TPS73133 general+5V voltage transitions is+3.3V realization FPGAI/O confession.While power supply main control module passes through enable switch control chip TPS54612 and chip TPS70302's+input of 5V voltage.FPGA connects the power supply main control module by the I/O pin, and the master control power module is realized chip TPS54612 and chip TPS70302 conversion of operation state by the feedback signal control enable switch of FPGA operate as normal.In the normal startup of FPGA, 4 power supply chips start simultaneously, in the time of the FPGA operate as normal, FPGA feeds back signal to the master control power module, the master control power module will to chip TPS54612 and chip TPS70302 power supply+5V power enable switch disconnects, chip TPS54612 and chip TPS70302 are quit work, and keep the operate as normal of TPS71825-12, TPS73133 chip.

Referring to Fig. 2, comprise the detailed circuit design of high-power power supply circuits, small-power power supply circuits and feedback circuit.High-power power supply circuits are designed to TPS71825-12 chip pin 2 input+5V voltages, and carry out ground connection filtering by the electric capacity of a 0.1uF, and

4,6 respectively connects+5V voltage pin 5,7 ground connection by the 10K Ω resistance of connecting.TPS73133 pin of chip 1 input+5V voltage, and carry out ground connection filtering by the electric capacity of a 0.1uF, pin 3 connects+5V voltage by the 10K Ω resistance of connecting, and pin 4 is by the capacity earth of a 0.1uF, pin 2 direct ground connection.

Enable switch input+5V the voltage of the master control power supply control of the TPS54612 chip series connection in the design of small-power power supply circuits, switch output+5V voltage connects this

chip pin

2,3,10,11,

2,3 and

10,11 respectively by the tantalum electric capacity of a 10uF in parallel and the capacity earth filtering of a 0.1

uF.Pin

1,7,8,9,12,13,24 ground connection, pin 5,6 respectively by the 10K Ω resistance of connecting connect enable switch output+

5V voltage.Pin

4,, 17,20

unsettled.Pin

18,19 respectively connects pin 22 by the 10K Ω resistance of connecting.

16,21 is respectively by a 30.1K Ω grounding through

resistance.Pin

14,15 connects pin 16 by a 31.6K Ω resistance, the tantalum electric capacity of a 10uF simultaneously in parallel and the capacity earth filtering of a 0.1

uF.Pin

22,23 connects pin 21 by a 51.1K Ω resistance, the tantalum electric capacity of a 10uF simultaneously in parallel and the capacity earth filtering of a 0.1uF.

TPS70302 chip in the design of small-power power supply circuits passes through the inductance of a 3.3uH, a termination enable switch, this pin of

chip

20,21,22,23,24 of another termination, the capacity earth filtering of a 220uF tantalum electric capacity in parallel and 10uF simultaneously.

3,27,28 unsettled.Pin 4 connects pin 21 by series connection 10K Ω resistance, and pin 26 is by the capacity earth of 0.068uF, and pin 25 is by the capacity earth of 0.1uF,

1,15,16,17,18,19,29

ground connection.Pin

6,7,8,9,10,11,12,13,14 links to each other, and pin 5 connects pin 6 by the electric capacity of a 0.047uF.Pin 6 connects pin 2 by the inductance of 4.7uH, and pin 2 is by the tantalum capacity earth of 2 220uF in parallel.

FPGA and the design of power supply main control module feedback circuit: the pin 3 of chip TPS71825-12 connects the pin 2 of chip TPS54612 to the voltage of FPGA for 1.2V.The pin 1 of chip TPS71825-12 connects the pin 15 of chip TPS70302 to the voltage of FPGA for 2.5V.The pin 5 of chip TPS73133 connects the pin 22 of chip TPS70302 to the voltage of FPGA for 3.3V.Simultaneously, I/O pin of FPGA connects an I/O pin of master control power supply, I/O pin control enable switch of master control power supply enable the EN pin.

TPS54612, TPS70302, TPS71825-12, TPS73133 chip power on simultaneously in the FPGA electrifying startup, after FPGA starts successfully, when entering operate as normal, provide master control power module feedback signal, the master control power supply disconnects supply line's enable switch of TPS54612, TPS70302 chip, when being the FPGA operate as normal only TPS71825-12, TPS73133 chip power to FPGA, the characteristics that power on, work by advantage and the FPGA that utilizes various chip types have been designed the method for this reduction power consumption like this.

Claims

1. low-power consumption FPGA power supply, comprise high power electric power supply system, small-power electric power system and power supply main control module, it is characterized in that: described high power electric power supply system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and power output can satisfy the startup of FPGA and the loading of program; Described small-power electric power system will import+and the 5V direct voltage is converted to the needed voltage of FPGA, and power output can be kept the demand of low-power consumption FPGA operate as normal; The power supply main control module is by the power supply input of enable switch control high power electric power supply system; The I/O pin of FPGA connects the power supply main control module, and the power supply main control module is realized the conversion of operation state of high power electric power supply system by the feedback signal control enable switch of FPGA operate as normal; Power supply is the power supply of small-power electric power system simultaneously.