CN103247628B - SRAM device and manufacture method thereof - Google Patents
SRAM device and manufacture method thereof Download PDFInfo
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- CN103247628B CN103247628B CN201210025330.7A CN201210025330A CN103247628B CN 103247628 B CN103247628 B CN 103247628B CN 201210025330 A CN201210025330 A CN 201210025330A CN 103247628 B CN103247628 B CN 103247628B
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- source region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The embodiment of the invention discloses a kind of SRAM device and manufacture method thereof. Described SRAM device includes: substrate; Being positioned at the well region on described substrate, described well region is kept apart by shallow trench; It is positioned at the source region that described well region is adjacent with described shallow trench; Being positioned at the inter-level dielectric on described well region, be provided with the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region. SRAM device provided by the present invention, less leaking electricity produced by the edge of device, the yield of device is higher.
Description
Technical field
The present invention relates to semiconductor device fabrication process technical field, more particularly, it relates to a kind of SRAM device and manufacture method thereof.
Background technology
SRAM (StaticRAM) device, that is: SRAM, it is a kind of internal memory with static access facility, do not need refresh circuit and can preserve the data of its storage inside, therefore, dynamic RAM (DynamicRAM, DRAM) is compared, its access speed faster, thus the work efficiency of device can be improved.
Existing SRAM device, when testing wafer before packaging, it has been found that yield (yield) is relatively low, and this causes mainly due to device edge electric leakage. If the electric leakage size of diverse location test device on wafer, if the test result of Bin1 correspondence center wafer (center) position, the test result of (middle) position in the middle of Bin3 correspondence wafer, the test result of Bin6 correspondence Waffer edge (edge) position, then there is Bin1 < Bin3 < Bin6, the big I of electric leakage of Bin6 is more than 100 μ A, so that component failure.
Device edge electric leakage is mainly reflected in the source region place electric leakage of edge, with reference to Fig. 1, Fig. 1 has illustrated shallow trench 10, it is provided with source region 12 in the well region 11 adjacent with described shallow trench 10, described source region 12 is contrary with the doping type of well region 11, being provided with inter-level dielectric 13 on well region 11 and shallow trench 10, be provided with the contact hole 14 being connected with source region 12 in inter-level dielectric 13, described contact hole 14 is formed by etching technics. Etching process not only defines the contact hole at device edge position, but also define the contact hole of device middle part, but owing to the etch rate at edge is bigger, therefore, the contact hole 14 of edge will cause over etching, and the result of over etching is so that contact hole 14 extends in shallow trench 10, therefore, leakage current can enter in well region 11 (along figure arrow direction) by described contact hole 14, thus causing the serious drain of edge.
If being shortened by etch period to reduce the impact of over etching, then the contact hole that the non-edge position on device is formed is likely to realize conducting function because etch period is not enough.
Summary of the invention
In view of this, the present invention provides a kind of SRAM device and manufacture method thereof, and the problem serious to solve existing SRAM device edge current leakage, thus improving the yield of device.
For achieving the above object, the present invention provides following technical scheme:
A kind of SRAM device, this SRAM device includes:
Substrate;
Being positioned at the well region on described substrate, described well region is kept apart by shallow trench;
It is positioned at the source region that described well region is adjacent with described shallow trench;
Being positioned at the inter-level dielectric on described well region, be provided with the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region.
Preferably, in above-mentioned SRAM device, described well region is N-type well region, and described source region is the heavily doped source region of P type.
Preferably, in above-mentioned SRAM device, described contact hole distance from both sides of the edge, described source region on the direction of source region and shallow trench line is 0.08 μm～0.14 μm.
Preferably, in above-mentioned SRAM device, the cross section of described contact hole is square, and the described foursquare length of side is 0.22 μm.
Preferably, in above-mentioned SRAM device, the width in described source region is 0.38～0.50 μm.
Preferably, in above-mentioned SRAM device, the junction depth in described source region is 0.26 μm.
Present invention also offers a kind of SRAM device manufacture method, the method includes:
Substrate is provided;
Form well region over the substrate, and form the shallow trench isolating described well region;
The source region adjacent with described shallow trench is formed in described well region;
Described well region is formed inter-level dielectric;
Forming the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region.
Preferably, in said method, the well region formed is N-type well region, and the source region formed is the heavily doped source region of P type.
Preferably, in said method, the width in the source region formed is 0.38～0.50 μm, and the junction depth in source region is 0.26 μm.
Preferably, in said method, the cross section of the contact hole formed is square, and the described foursquare length of side is 0.22 μm, and the contact hole formed distance from both sides of the edge, described source region on the direction of source region and shallow trench line is 0.08 μm～0.14 μm.
From technique scheme it can be seen that SRAM device provided by the present invention includes: substrate; Being provided with well region on described substrate, described well region is kept apart by shallow trench; The source region adjacent with described shallow trench it is provided with in described well region; Being provided with the contact hole being connected with described source region in inter-level dielectric above well region, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region. Owing to described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region, therefore on the direction with shallow trench line, the source region, described source region surrounds described contact hole, that is: described contact hole has certain distance apart from described shallow trench, so that without etching described shallow trench in over etching process, therefore avoid contact hole extend to cause in shallow trench electric leakage, the yield of device may finally be improved.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic diagram that in prior art, SRAM device edge produces drain conditions;
The cross-sectional view of the SRAM device that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the top view of SRAM device in prior art;
The top view of a kind of SRAM device that Fig. 4 provides for the embodiment of the present invention;
The top view of the another kind of SRAM device that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 is the electric leakage curve synoptic diagram at P type source region place in various location N-type well region in SRAM device provided by the present invention;
The schematic flow sheet of a kind of SRAM device manufacture method that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments. Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Just as described in the background section, the reason causing SRAM device yield low is in that the electric leakage of device edge is bigger, device edge electric leakage is mainly reflected in the source region place electric leakage of edge, time this is owing to forming contact hole on device, the etch rate of edge is bigger, so that there is over etching phenomenon in the contact hole of edge, the contact hole making edge is extended in shallow trench by described over etching phenomenon, and then make to be connected with well region bottom this contact hole, so that leakage current enters well region by described contact hole, cause electric leakage.
And if shorten etch period, then on device, the contact hole at non-edge position is likely to cause turning on because etch period is not enough.
Consider that the result of over etching is so that contact hole extends in shallow trench, so that be connected with well region bottom this contact hole, ultimately result in electric leakage, therefore, if what made by the junction depth in the source region in well region is deep, so, the result of over etching is likely to the bottom not causing contact hole and is connected with the well region below source region, and then can solve electrical leakage problems. But, the junction depth in source region too senior general affects other performances of device, and therefore this method is also unworkable.
Based on this, embodiment of the present invention domain from SRAM device manufacturing process, the width in source region, device edge is increased by new layout design, and make its center corresponding of the contact hole above source region, that is: described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region, so, on the direction with shallow trench line, the source region, described source region surrounds the contact hole above it, so that described contact hole is away from the shallow trench near source region. So when forming contact hole by etching technics, even if etch period lengthens, the contact hole that edge is formed, without extending in described shallow trench, being joined directly together by shallow trench and well region thus avoiding contact hole, reducing the electric leakage at device edge place. The domain structure in source region only need to be redesigned in manufacturing process due to this SRAM device, therefore, without strengthening the junction depth in source region, just can solve, without shortening etch period, the problem that the electric leakage of device edge is serious, without other performances having influence on device while improving yield of devices.
Provided by the present invention SRAM device and manufacture method thereof are described in detail below in conjunction with accompanying drawing.
Embodiment one
With reference to the cross-sectional view of the SRAM device that Fig. 2, Fig. 2 provide for the embodiment of the present invention, this SRAM device includes: substrate 100; Being positioned at the well region 101 on described substrate 100, described well region 101 is kept apart by shallow trench 102; It is positioned at the source region 103 that described well region 101 is adjacent with described shallow trench 102; Being positioned at the inter-level dielectric 104 on described well region 101, be provided with the contact hole 105 being connected with described source region 103 in described inter-level dielectric 104, described contact hole 105 makes described source region 103 be symmetrically distributed on the direction of source region 103 and shallow trench 102 line.
Described source region 103 is contrary with the doping type of well region 101. Source region 103 described in the embodiment of the present invention and the contact hole 105 on source region 103 are the structure being in SRAM device edge.
This source region 103 is compared with source region of the prior art, width on source region with shallow trench line direction increases, and the contact hole 105 above source region 103 makes described source region 103 be symmetrically distributed on source region with shallow trench line direction, that is: on source region with shallow trench line direction, described contact hole 105 is positioned at above the center in described source region 103, performance is in fig. 2: described contact hole 105 is equal with distance d from both sides of the edge, described source region 103 on the direction of shallow trench 102 line in source region 103, therefore, on source region with shallow trench line direction, described source region 103 surrounds contact hole 105 thereon, described contact hole 105 is made to have certain distance d apart from described shallow trench 102, thus formed contact hole 105 time over etching process in, described contact hole 105 is not extend in shallow trench 102, and then avoid contact hole 105 be connected with well region 101 by shallow trench 102 and cause electric leakage, the yield of device may finally be improved.
Being the top view of SRAM device in prior art with reference to Fig. 3 and Fig. 4, Fig. 3, Fig. 4 is the top view of SRAM device provided by the present invention. SRAM device in Fig. 3, source region 20 is adjacent with shallow trench 22, contact hole 21 (in figure W1 indication) on source region 20 is oblique with shallow trench 22 adjacent, therefore, in over etching process, extending to bottom contact hole 21 in shallow trench 22, the WeakPoint (bad point) in corresponding diagram 3, namely leakage current is produced by corresponding bad point place. SRAM device in Fig. 4, contact hole 105 (in figure W1 indication) on source region 103 makes described source region 103 be symmetrically distributed (shown in broken box part) on the line direction of source region 103 and shallow trench 102, described contact hole 105 distance from both sides of the edge, described source region 103 on the line direction with shallow trench 102, source region 103 is 0.14 μm, this allows for described contact hole 105 distance from described shallow trench 102 on the line direction with shallow trench 102, source region 103 is 0.14 μm, because there being the existence of this 0.14 μm of distance, therefore in over etching process, the bottom of described contact hole 105 is not extend in described shallow trench 102, that is: shallow trench 102 will not be performed etching by over etching process, thus avoiding the generation of bad point, avoid the serious drain at device edge place. along Fig. 4, the profile of the device that AA ' does in direction cutting gained is structure shown in Fig. 2.
The cross section of the contact hole being positioned on source region in Fig. 3 and Fig. 4 is square, the described foursquare length of side is 0.22 μm, therefore, in Fig. 3, the width (i.e. width on source region with shallow trench line direction) in source region 20 is 0.36 μm, and the width in source region 103 is 0.50 μm in Fig. 4, that is: the present invention is compared with prior art, and the width in described source region adds 0.14 μm.
With reference to Fig. 5, Fig. 5 having illustrated, contact hole 105 distance from both sides of the edge, described source region 103 ' on the line direction with shallow trench 102, source region 103 ' is 0.08 μm, and the cross section of contact hole 105 is also square, the described foursquare length of side is 0.22 μm, and therefore, in Fig. 5, the width in source region 103 ' is 0.38 μm, compared with Fig. 3, the width in source region shown in Fig. 5 only need to increase by 0.02 μm, and therefore, structure shown in Fig. 5 is preferably embodiment. But, the width arranging described source region in the embodiment of the present invention is all possible between 0.38～0.50 μm, it may be assumed that ensure described contact hole on the line direction of source region and shallow trench distance from both sides of the edge, described source region between 0.08 μm～0.14 μm. The junction depth in described source region could be arranged to about 0.26 μm.
Discovery is studied through inventor, not all there is serious drain phenomenon in all of source region, device edge place place, this serious drain phenomenon mainly occurs in the P type source region place formed in device edge place N-type well region, if existing for device edge place and there is in P type trap zone N-type source region, then in this N-type source region, do not have serious drain phenomenon. With reference to Fig. 6, Fig. 6 is the electric leakage curve synoptic diagram at P type source region place in various location N-type well region in SRAM device provided by the present invention, the electric leakage that in figure, in bin1 indication curve respective devices, center (center) position place surveys, (middle in the middle of in bin3 indication curve respective devices, between center and edge) electric leakage surveyed of position place, the electric leakage that bin6 indication curve respective devices top edge (edge) position place surveys, as can be seen from Figure, the electric leakage of device center position is substantially little than the electric leakage of device edge position. This curve chart obtains only for the test of P type source region place in N-type well region, when N-type source region place carries out testing in P type trap zone, can not get this curve chart, therefore, in the embodiment of the present invention preferred only in the N-type well region at device edge place P type source region place carry out the increase of area width, described source region is made to surround contact hole thereon on the line direction with shallow trench, the source region, and then avoid over etching process making described contact hole extend in described shallow trench, the yield of device reduces the electric leakage at device edge place, thus can be improved.
Therefore, in the embodiment of the present invention, it is preferred that scheme is: only in the N-type well region at device edge place, P type source region place carries out the increase of area width, in the P type trap zone at device edge place, N-type source region place does not improve. Specifically can referring to Fig. 4 and Fig. 5, Fig. 4 and Fig. 5 merely illustrates and widens P type source region (TO (P+), i.e. heavily doped P type source region) width, N-type source region TO (N+) is not made any changes, still with identical (can comparison diagram 3) of the prior art. What in figure, GT represented is grid.
In summary, SRAM device provided by the present invention, by increasing the width in device edge source region, so that institute source region surrounds contact hole thereon on its line direction with shallow trench, and then the bottom of contact hole described in over etching process can be avoided to extend in described shallow trench, thus the produced electric leakage in device edge place can be reduced, improve the yield of device.
SRAM device provided by the present invention described in detail above, is described below its manufacture method.
Embodiment two
With reference to the schematic flow sheet of a kind of SRAM device manufacture method that Fig. 7, Fig. 7 provide for the embodiment of the present invention, the method specifically includes following steps:
Step S1: substrate is provided.
Described substrate can be silicon, germanium or other semi-conducting materials.
Step S2: form well region over the substrate, and form the shallow trench isolating described well region.
Formed N-type well region by ion implantation technology over the substrate, and form shallow trench (STI) in this N-type well region edge, so that this N-type well region and other well region are isolated.
Step S3: form the source region adjacent with described shallow trench in described well region.
In N-type well region, the P type heavily doped source region adjacent with described shallow trench is formed by ion implantation technology. Ion implantation process should use corresponding mask plate, so that the width in the P type source region formed meets requirement. The actual conditions met can referring to the description in embodiment one. The width in the P type source region formed can between 0.38～0.50 μm, and the junction depth in P type source region is 0.22 μm.
Step S4: form inter-level dielectric on described well region.
On described well region and shallow trench, inter-level dielectric is formed by chemical vapor deposition method.
Step S5: form the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region.
First spin coating photoresist layer on described inter-level dielectric, then adopt corresponding mask plate that described photoresist layer is exposed, develop afterwards, form the photoresist layer with contact hole graph, then described inter-level dielectric is performed etching with the described photoresist layer with contact hole graph for mask, thus forming contact hole in described inter-level dielectric, this contact hole is connected with source region, and this contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region.
In order to make the contact hole formed make described source region be symmetrically distributed on the direction with shallow trench line, the source region, this will when being exposed photoresist layer, corresponding mask plate position on photoresist layer is accurately set, by exposing, in photoresist layer, the figure of contact hole is defined after development, the figure of this contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region, only in this way, the follow-up contact hole for mask with the described photoresist layer with contact hole graph described inter-level dielectric being performed etching and then being formed could meet requirement.
The cross section of the contact hole formed in this step is square, and the described foursquare length of side is 0.22 μm, and the contact hole formed on the direction of source region and shallow trench line distance from both sides of the edge, described source region between 0.08 μm～0.14 μm.
As from the foregoing, in the process forming SRAM device, perform etching to form contact hole to described inter-level dielectric with the photoresist layer with contact hole graph for mask, owing to the described photoresist layer with contact hole graph makes described source region be symmetrically distributed on the direction with shallow trench line, the source region, therefore, it has equal distance in source region with edge from both sides, source region on the direction of shallow trench line, that is: it has certain distance on the direction of source region and shallow trench line and between shallow trench, therefore, when in the process carrying out over etching after having etched inter-level dielectric, what the bottom of the contact hole formed was corresponding is source region, and there is bottom this and between shallow trench certain distance, therefore shallow trench will not be performed etching by the process of over etching, and then described contact hole will not be made to extend in described shallow trench, thus reducing the produced electric leakage in device edge place, improve the yield of device.
Emphasizing particularly on different fields a little to the description of SRAM device and manufacture method thereof in the embodiment of the present invention, relevant similarity can reference mutually.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention. The multiple amendment of these embodiments be will be apparent from for those skilled in the art, and generic principles defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments. Therefore, the present invention is not intended to be limited to the embodiments shown herein, and is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (9)
1. a SRAM device, it is characterised in that including:
Substrate;
Being positioned at the well region on described substrate, described well region is kept apart by shallow trench;
It is positioned at the source region that described well region is adjacent with described shallow trench;
Being positioned at the inter-level dielectric on described well region, be provided with the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region;
Described contact hole distance from both sides of the edge, described source region on the direction of source region and shallow trench line is 0.08 μm～0.14 μm.
2. SRAM device according to claim 1, it is characterised in that described well region is N-type well region, described source region is the heavily doped source region of P type.
3. SRAM device according to claim 1, it is characterised in that the cross section of described contact hole is square, and the described foursquare length of side is 0.22 μm.
4. SRAM device according to claim 1, it is characterised in that the width in described source region is 0.38～0.50 μm.
5. SRAM device according to claim 1, it is characterised in that the junction depth in described source region is 0.26 μm.
6. a SRAM device manufacture method, it is characterised in that including:
Substrate is provided;
Form well region over the substrate, and form the shallow trench isolating described well region;
The source region adjacent with described shallow trench is formed in described well region;
Described well region is formed inter-level dielectric;
Forming the contact hole being connected with described source region in described inter-level dielectric, described contact hole makes described source region be symmetrically distributed on the direction with shallow trench line, the source region;
Described contact hole on the direction of source region and shallow trench line distance from both sides of the edge, described source region between 0.08 μm～0.14 μm.
7. method according to claim 6, it is characterised in that the well region formed is N-type well region, the source region formed is the heavily doped source region of P type.
8. method according to claim 6, it is characterised in that the width in the source region formed is 0.38～0.50 μm, the junction depth in source region is 0.26 μm.
9. method according to claim 6, it is characterized in that, the cross section of the contact hole formed is square, the described foursquare length of side is 0.22 μm, and the contact hole formed distance from both sides of the edge, described source region on the direction of source region and shallow trench line is 0.08 μm～0.14 μm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210025330.7A CN103247628B (en) | 2012-02-06 | 2012-02-06 | SRAM device and manufacture method thereof |
| PCT/CN2012/085446 WO2013117097A1 (en) | 2012-02-06 | 2012-11-28 | Sram device and manufacturing method therefor |
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| CN201210025330.7A CN103247628B (en) | 2012-02-06 | 2012-02-06 | SRAM device and manufacture method thereof |
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| CN103247628B true CN103247628B (en) | 2016-06-15 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992281A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Static random access memory and method for manufacturing the same |
| CN101924108A (en) * | 2009-05-22 | 2010-12-22 | 日本优尼山帝斯电子株式会社 | Semiconductor storage unit and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4987090A (en) * | 1987-07-02 | 1991-01-22 | Integrated Device Technology, Inc. | Static ram cell with trench pull-down transistors and buried-layer ground plate |
| WO2005119763A1 (en) * | 2004-06-04 | 2005-12-15 | Nec Corporation | Semiconductor device and manufacturing method thereof |
| US8236702B2 (en) * | 2005-10-06 | 2012-08-07 | United Microelectronics Corp. | Method of fabricating openings and contact holes |
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2012
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- 2012-11-28 WO PCT/CN2012/085446 patent/WO2013117097A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992281A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Static random access memory and method for manufacturing the same |
| CN101924108A (en) * | 2009-05-22 | 2010-12-22 | 日本优尼山帝斯电子株式会社 | Semiconductor storage unit and manufacture method thereof |
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Effective date of registration: 20171206 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |