CN103246624A - Weighted priority scheduling method for multi-interface SRAM (static random access memory) - Google Patents
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Abstract
Provided is a weighted priority scheduling method for a multi-interface SRAM (static random access memory). The weighted priority scheduling method for the multi-interface SRAM is characterized in that a weight valve is assigned to each module interface, and each corresponding module interface is provided with a counter used for recording the number of times of each corresponding module interface successfully accessing to the SRAM; in an initial state, each module interface is ranged from high to low according to an initial priority; at any state, when a plurality of module interfaces initiate an access request to the SRAM at the same time, the module interface with higher priority is allowed to access to the SRAM; when the access is successful, the counter corresponding to the module interface records the number of the successful access of the module interface; when the number of the successful access of the module interface does not reach the weight value of the module interface, the priority order of each module interface keeps unchanged; and when the number of the successful access of the module interface reaches the weight valve of the module interface, the priority of the module interface is reduced to a minimum and the corresponding counter is cleared. The weighted priority scheduling method for the multi-interface SRAM is flexible to use. Meanwhile, throughput of the system is improved, average processing time is reduced, and the overall performance of the system is enhanced.
Description
Technical field
The present invention relates to static RAM control field, relate in particular to a kind of priority dispatching method that is applied to many interfaces SRAM.
Background technology
SRAM(Static Random-Access Memory, static RAM) is a kind of internal memory with static access facility, owing to do not need refresh circuit can preserve the data of its storage inside, SRAM has become the storer of present main flow, and widespread use in embedded SOC chip (System on Chip, system level chip).Yet, development along with IC industry, the integrated module of SOC internal system gets more and more, these modules often need be visited SRAM, when these modules are carried out some parallel work-flows, because SRAM simultaneously can only be by a module accesses, so necessary alternate access SRAM of these modules, traditional method is to allow them carry out alternate access by the software coordinated mode, this method had both expended a large amount of software resources, connected reference SRAM makes free times to be visited such as SRAM existence in the time of can't realizing again that module replaces, and has influenced the access efficiency of SRAM greatly.
Chinese patent CN103049408A discloses the application for a patent for invention that a name is called " a kind of many interfaces SRAM read-write control circuit and method ".This application for a patent for invention discloses the read/writing control method of a kind of many interfaces SRAM, this control method adopts the method for fixed priority to the module interface of each visit SRAM, the good priority of hardware definition, selected cell in the control circuit is selected the highest SRAM is conducted interviews of module interface medium priority of request visit, also be provided with the counter for each module interface visit SRAM frequency of failure of record, when the frequency of failure reaches a setting numerical value, the interim priority that improves this module interface, behind SRAM of this module interface successful access, again it is returned to initial priority.The advantage of this method is because the priority of each module interface is that hardware setting is good, so circuit structure is simple; By this application embodiment as seen, the priority of each module is followed successively by USB, DMA, data encrypting and deciphering controller, CPU from high to low in the described control method, this situation is specially adapted to the USB flash disk controller, its reason is that the USB interface in the USB flash disk is relatively stricter to the requirement of real-time property, so the priority that USB interface is visited SRAM is made as the highest; Store or read data and Nandflash storer in a large number when needs and carry out when mutual, need to use DMA to finish data transfer operation between SRAM and the Nandflash, so that the priority of DMA visit SRAM is made as is time high; The data encrypting and deciphering controller only carries out encryption and decryption when operation usefulness just at needs to data, so its priority is lower than DMA; And CPU only is used for depositing some variable informations, can visit SRAM once in a while, and frequency of utilization is lower than former three, so priority is minimum.In a word, for a module interface, generally all be the priority of coming the setting module interface according to its frequency of utilization and request for utilization.Such method dirigibility is relatively poor, if the high interface of priority takies SRAM for a long time or when breaking down, will cause the module interface of low priority can't visit SRAM, occur that equipment " makes extremely full " and the phenomenon of " dying of hunger ", thereby cause the overall performance of system to descend.
Summary of the invention
The object of the invention provides a kind of priority dispatching method that many interfaces SRAM cum rights weighs that is applied to of justice.
For achieving the above object, the technical solution used in the present invention is: a kind of heavy priority dispatching method of many interfaces SRAM cum rights that is applied to, respectively give a weighted value to access frequency and the visiting demand of SRAM to each module interface according to each module interface, this weighted value is the integer greater than 1, is equipped with for the counter that records its visit SRAM number of success corresponding to each module interface;
Under original state, each module interface is arranged an initial priority, each module interface sorts from high to low according to initial priority;
Under arbitrary state, when a plurality of module interfaces are initiated request of access to SRAM simultaneously, allow the higher module interface visit SRAM of current priority, visit the successful number of times of its visit of counter records of module interface correspondence successful the time, if the visit number of success does not reach the weighted value of this module interface, then the prioritization of each module interface remains unchanged, when if the visit number of success reaches the weighted value of this module interface, the priority of this module interface is reduced to minimum, counter O reset that it is corresponding simultaneously.
Related content in the technique scheme is explained as follows:
1, in the such scheme, under arbitrary state, if the successful number of times of the minimum module interface of current priority visit is less than or equal to its weighted value, and the visit number of success of all the other module interfaces is during less than its weighted value, and the prioritization of each module interface remains unchanged.
2, in the such scheme, the weighted value of each module interface is prepared by software, and the maximal value of weighted value is determined by the scope that hardware register arranges.
Because technique scheme is used, the present invention compared with prior art has following advantage and effect:
1, the present invention uses flexibly, gets final product for the different application scenario different weighted values of configuration on the one hand, need not change hardware, also can pass through its weighted value of software change at any time in addition in a kind of application.
2, the present invention improved system handling capacity, shortened average handling time, promoted the overall performance of system.
Description of drawings
Accompanying drawing 2 is the state redirect synoptic diagram of original state in the embodiment of the invention two-state machine;
Accompanying drawing 3 is the state redirect synoptic diagram of state S5 in the embodiment of the invention two-state machine.
In the above-mentioned accompanying drawing: the weighted value of W1, module interface M1; The number of success of N1, module interface M1 visit SRAM; The weighted value of W2, module interface M2; The number of success of N2, module interface M2 visit SRAM; The weighted value of W3, module interface M3; The number of success of N3, module interface M3 visit SRAM; The weighted value of W4, module interface M4; The number of success of N4, module interface M4 visit SRAM.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment one:
Shown in accompanying drawing 1, a kind of heavy priority dispatching method of many interfaces SRAM cum rights that is applied to, three module interface M1 are arranged, M2 and M3 are, and SRAM initiates request of access, respectively give a weighted value to access frequency and the visiting demand of SRAM to each module interface according to each module interface, this weighted value is the integer greater than 1, if the weighted value of M1 is W1, the weighted value of M2 is W2, the weighted value of M3 is W3, access frequency and the visiting demand of supposing the SRAM of M1 are the highest, the access frequency of the SRAM of M2 and visiting demand are inferior high, and access frequency and the visiting demand of the SRAM of M3 are minimum, the weighted value ordering then is set is W1〉W2〉W3.
Be equipped with for the counter that records its visit SRAM number of success corresponding to each module interface, the number of success that records M1 visit SRAM respectively is N1, and the number of success of M2 visit SRAM is N2, and the number of success of M3 visit SRAM is N3.
Under original state S1, each module interface is arranged an initial priority, each module interface sorts from high to low according to initial priority, and the priority of establishing M1 is the highest, and the priority of M2 is inferior high, the priority of M3 is minimum, i.e. M1 under the S1 state in the accompanying drawing 1〉M2〉M3.
Under original state S1, reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, and the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N3 of M3 visit SRAM did not reach the weighted value W3 of M3 yet, state machine jumped to the S2 state, under the S2 state, the priority of M1 is reduced to minimum, simultaneously M1 is visited the number of success N1 zero clearing of SRAM, the priority of M2 and M3 is suitable moves, i.e. M2〉M3〉M1; Under the S2 state, reach the weighted value W2 of M2 as the number of success N2 of M2 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, and when the number of success N3 of M3 visit SRAM did not reach the weighted value W3 of M3 yet, state machine jumped to the S3 state; Under the S3 state, the priority of M2 is reduced to minimum, simultaneously M2 is visited the number of success N2 zero clearing of SRAM, and the priority of M1 and M3 is suitable moves, i.e. M3〉M1〉M2; Under the S3 state, reach the weighted value W3 of M3 as the number of success N3 of M3 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, and when the number of success N2 of M2 visit SRAM did not reach the weighted value W2 of M2 yet, state machine jumped to the S1 state; Under the S1 state, the priority of M3 is reduced to minimum, simultaneously M3 is visited the number of success N3 zero clearing of SRAM, and the priority of M1 and M2 is suitable moves, i.e. M1〉M2〉M3.
Under original state S1, do not reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, and the number of success N2 of M2 visit SRAM is when reaching the weighted value W2 of M2, and state machine jumps to the S4 state; Under the S4 state, the priority of M2 is reduced to minimum, simultaneously M2 is visited the number of success N2 zero clearing of SRAM, and the priority of M1 and M3 is suitable moves, i.e. M1〉M3〉M2.
Under original state S1, do not reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, and no matter whether the number of success N3 of M3 visit SRAM reach the weighted value W3 of M3, state machine all remains on the S1 state, because the priority of M3 was exactly minimum originally.
Be example with state S4 below, describe the state redirect of S4:
Under state S4, the priority of M1 is the highest, and the priority of M3 is inferior high, and the priority of M2 is minimum, i.e. M1 under the S4 state in the accompanying drawing 1〉M3〉M2.
Under state S4, reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, and the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, and when the number of success N3 of M3 visit SRAM did not reach the weighted value W3 of M3 yet, state machine jumped to the S5 state; Under the S5 state, the priority of M1 is reduced to minimum, simultaneously M1 is visited the number of success N1 zero clearing of SRAM, and the priority of M2 and M3 is along moving, and namely prioritization is M3〉M2〉M1.
Under state S4, when the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, and the number of success N3 of M3 visit SRAM is when reaching the weighted value W3 of M3, and state machine jumps to the S1 state; Under the S1 state, the priority of M3 is reduced to minimum, simultaneously M3 is visited the number of success N3 zero clearing of SRAM, and the priority of M1 and M2 is along moving, and namely prioritization is M1〉M2〉M3.
Under state S4, do not reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3 yet, and no matter whether the number of success N2 of M2 visit SRAM reach the weighted value W2 of M2, state machine all remains on the S4 state, be that prioritization is M1〉M3〉M2, because the priority of M2 was exactly minimum originally.
By that analogy, every kind of state all has three kinds of state redirects possibilities in the accompanying drawing 1, determines the redirect of state machine according to the number of success of each module interface visit SRAM.
Illustrate, for example SRAM is circumscribed with USB controller, dma controller and three module interfaces of CPU, the weighted value that the USB controller is set according to access frequency and the visiting demand of USB controller, dma controller and the SRAM of CPU is 16, and the weighted value of dma controller is that the weighted value of 8, CPU is 2.Under the original state, the priority of USB controller is the highest, and the priority of dma controller is inferior high, and the priority of CPU is minimum.When the number of success of USB controller access SRAM reaches 16 times, the priority of USB controller is reduced to minimum, when the number of success of dma controller visit SRAM reaches 8 times, the priority of dma controller is reduced to minimum, and when the number of success of CPU visit SRAM reached 2 times, the priority of CPU was reduced to minimum, three's priority is according to the number of success of its visit SRAM, having carried out wheel changes, in turn for the highest, simultaneously also in turn for minimum.Above-mentioned for example corresponding to the redirect situation of state machine in the accompanying drawing 1 from S1-S2-S3-S1, by that analogy, according to the situation that the three visits SRAM, priority also has different rotational orders.
Embodiment two:
Shown in accompanying drawing 2, a kind of heavy priority dispatching method of many interfaces SRAM cum rights that is applied to, four module interface M1 are arranged, M2, M3 and M4 are, and SRAM initiates request of access, respectively give a weighted value to access frequency and the visiting demand of SRAM to each module interface according to each module interface, this weighted value is the integer greater than 1, if the weighted value of M1 is W1, the weighted value of M2 is W2, the weighted value of M3 is W3, the weighted value of M4 is W4, access frequency and the visiting demand of supposing the SRAM of M1 are the highest, the access frequency of the SRAM of M2 and visiting demand are inferior high, the access frequency of the SRAM of M3 and visiting demand the 3rd height, access frequency and the visiting demand of the SRAM of M4 are minimum, the weighted value ordering then is set is W1〉W2〉W3〉W4.
Be equipped with for the counter that records its visit SRAM number of success corresponding to each module interface, the number of success that records M1 visit SRAM respectively is N1, the number of success of M2 visit SRAM is N2, and the number of success of M3 visit SRAM is N3, and the number of success of M4 visit SRAM is N4.
Under original state S1, each module interface is arranged an initial priority, each module interface sorts from high to low according to initial priority, if the priority of M1 is the highest, the priority of M2 is inferior high, the priority the 3rd of M3, the priority of M4 is minimum, i.e. prioritization M1 under the S1 state in the accompanying drawing 2〉M2〉M3〉M4.
Under original state S1, reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, and the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S2 state, under the S2 state, the priority of M1 is reduced to minimum, simultaneously M1 is visited the number of success N1 zero clearing of SRAM, the priority of M2, M3 and M4 is along moving, and namely prioritization is M2〉M3〉M4〉M1; Under the S2 state, reach the weighted value W2 of M2 when the number of success of M2 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S3 state, under the S3 state, the priority of M2 is reduced to minimum, simultaneously M2 is visited the number of success N2 zero clearing of SRAM, the priority of M1, M3 and M4 is along moving, and namely prioritization is M3〉M4〉M1〉M2; Under the S3 state, reach the weighted value W3 of M3 as the number of success N3 of M3 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S4 state, under the S4 state, the priority of M3 is reduced to minimum, simultaneously M3 is visited the number of success zero clearing of SRAM, the priority of M1, M2 and M4 is along moving, and namely prioritization is M4〉M1〉M2〉M3; Under the S4 state, when the number of success N4 of M4 visit SRAM reaches the weighted value W4 of M4, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3 yet, state machine jumps to the S1 state, under the S1 state, the priority of M4 is reduced to minimum, simultaneously M4 is visited the number of success zero clearing of SRAM, the priority of M1, M2 and M3 is along moving, and namely prioritization is M1〉M2〉M3〉M4.。
Under original state S1, reach the weighted value W2 of M2 as the number of success N2 of M2 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S5 state, under the S5 state, the priority of M2 is reduced to minimum, simultaneously M2 is visited the number of success N2 zero clearing of SRAM, the priority of M1, M3 and M4 is along moving, and namely prioritization is M1〉M3〉M4〉M2.
Under original state S1, reach the weighted value W3 of M3 as the number of success N3 of M3 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S6 state, under the S6 state, the priority of M3 is reduced to minimum, simultaneously M3 is visited the number of success zero clearing of SRAM, the priority of M1, M2 and M4 is along moving, and namely prioritization is M1〉M2〉M4〉M3.
Under original state S1, do not reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3 yet, and no matter whether the number of success of M4 visit SRAM reach the weighted value W4 of M4, state machine all remains on the S1 state, and namely prioritization is M1〉M2〉M3〉M4, because the priority of M4 was exactly minimum originally.
Shown in accompanying drawing 3, be example with the S5 state below, the redirect of S5 state is described:
Under the S5 state, the prioritization of each module interface is M1〉M3〉M4〉M2.
Under the S5 state, reach the weighted value W1 of M1 as the number of success N1 of M1 visit SRAM, and the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S7 state, under the S7 state, the priority of M1 is reduced to minimum, simultaneously M1 is visited the number of success zero clearing of SRAM, the priority of M2, M3 and M4 is along moving, and namely prioritization is M3〉M4〉M2〉M1.
Under the S5 state, reach the weighted value W3 of M3 as the number of success N3 of M3 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, state machine jumps to the S8 state, under the S8 state, the priority of M3 is reduced to minimum, simultaneously M3 is visited the number of success N3 zero clearing of SRAM, the priority of M1, M2 and M4 is along moving, and namely prioritization is M1〉M4〉M2〉M3.
Under the S5 state, reach the weighted value W4 of M4 when the number of success of M4 visit SRAM, and the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, the number of success N2 of M2 visit SRAM does not reach the weighted value W2 of M2, when the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3 yet, state machine jumps to the S9 state, under the S9 state, the priority of M4 is reduced to minimum, simultaneously M4 is visited the number of success N4 zero clearing of SRAM, the priority of M1, M2 and M3 is along moving, and namely prioritization is M1〉M3〉M2〉M4.
Under the S5 state, the number of success N1 of M1 visit SRAM does not reach the weighted value W1 of M1, when the number of success N3 of M3 visit SRAM does not reach the weighted value W3 of M3, when the number of success N4 of M4 visit SRAM does not reach the weighted value W4 of M4 yet, and no matter whether the number of success N2 of M2 visit SRAM reach the weighted value W2 of M2, state machine all keeps the S5 state, and namely prioritization is M1〉M3〉M4〉M2, because the priority of M2 was exactly minimum originally.
By that analogy, every kind of state all has four kinds of state redirects possibilities in accompanying drawing 2 and the accompanying drawing 3, determines the redirect of state machine according to the number of success of each module interface visit SRAM.
Illustrate, for example SRAM is circumscribed with USB controller, dma controller, data encrypting and deciphering module and four module interfaces of CPU, the weighted value that the USB controller is set according to access frequency and the visiting demand of USB controller, dma controller, data encrypting and deciphering module and the SRAM of CPU is 16, the weighted value of dma controller is 8, the weighted value of data encrypting and deciphering module is that the weighted value of 4, CPU is 2.Under the original state, the priority of USB controller is the highest, and the priority of dma controller is inferior high, priority the 3rd height of data encrypting and deciphering module, and the priority of CPU is minimum.Then when the number of success of USB controller access SRAM reaches 16 times, the priority of USB controller is reduced to minimum, when the number of success of dma controller visit SRAM reaches 8 times, the priority of dma controller is reduced to minimum, when the number of success of data encrypting and deciphering module accesses SRAM reached for 4 this moments, the priority of data encrypting and deciphering module is reduced to minimum, and when the number of success of CPU visit SRAM reached 2 times, the priority of CPU was reduced to minimum.Four priority has been carried out wheel and has been changeed according to the number of success of its visit SRAM, in turn for the highest, simultaneously also in turn for minimum.Above-mentioned for example corresponding to the redirect situation of state machine in the accompanying drawing 2 from S1-S2-S3-S4-S1, by that analogy, according to four situations of visiting SRAM, priority also has different rotational orders.
The weighted value of each module interface can be prepared by software according to actual needs in above-described embodiment.
The present invention is under arbitrary state, when a plurality of module interfaces are initiated request of access to SRAM simultaneously, allow the higher module interface visit SRAM of current priority, visit the successful number of times of its visit of counter records of module interface correspondence successful the time, if the visit number of success does not reach the weighted value of this module interface, then the prioritization of each module interface remains unchanged, when if the visit number of success reaches the weighted value of this module interface, the priority of this module interface is reduced to minimum, counter O reset that it is corresponding simultaneously.The present invention uses flexibly, gets final product for the different application scenario different weighted values of configuration on the one hand, need not change hardware, also can pass through its weighted value of software change at any time in addition in a kind of application; Improved system handling capacity, shortened average handling time, promoted the overall performance of system.
Above-described embodiment is for example understood respectively the situations of three module interfaces and four module interface visit SRAM, and in actual applications, module interface is two, five, six even more for a long time, and method of the present invention also is suitable for.
Above-described embodiment only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit essence is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (3)
1. one kind is applied to the heavy priority dispatching method of many interfaces SRAM cum rights, it is characterized in that: respectively give a weighted value to access frequency and the visiting demand of SRAM to each module interface according to each module interface, this weighted value is the integer greater than 1, is equipped with for the counter that records its visit SRAM number of success corresponding to each module interface;
Under original state, each module interface is arranged an initial priority, each module interface sorts from high to low according to initial priority;
Under arbitrary state, when a plurality of module interfaces are initiated request of access to SRAM simultaneously, allow the higher module interface visit SRAM of current priority, visit the successful number of times of its visit of counter records of module interface correspondence successful the time, if the visit number of success does not reach the weighted value of this module interface, then the prioritization of each module interface remains unchanged, when if the visit number of success reaches the weighted value of this module interface, the priority of this module interface is reduced to minimum, counter O reset that it is corresponding simultaneously.
2. priority dispatching method according to claim 1, it is characterized in that: under arbitrary state, if the successful number of times of module interface visit that current priority is minimum is less than or equal to its weighted value, and the visit number of success of all the other module interfaces is during less than its weighted value, and the prioritization of each module interface remains unchanged.
3. priority dispatching method according to claim 1, it is characterized in that: the weighted value of each module interface is prepared by software.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101640951A (en) * | 2008-07-28 | 2010-02-03 | 富士通株式会社 | Base station, communication terminal, communication method for base station and communication terminal |
| CN103049408A (en) * | 2012-12-28 | 2013-04-17 | 苏州国芯科技有限公司 | Multi-interface SRAM (static random access memory) read-write control circuit and multi-interface SRAM read-write control method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640951A (en) * | 2008-07-28 | 2010-02-03 | 富士通株式会社 | Base station, communication terminal, communication method for base station and communication terminal |
| CN103049408A (en) * | 2012-12-28 | 2013-04-17 | 苏州国芯科技有限公司 | Multi-interface SRAM (static random access memory) read-write control circuit and multi-interface SRAM read-write control method |
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Application publication date: 20130814 |