CN103235920A - Programmable logic device and operating authorization control method thereof - Google Patents
Programmable logic device and operating authorization control method thereof Download PDFInfo
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- CN103235920A CN103235920A CN2013101588548A CN201310158854A CN103235920A CN 103235920 A CN103235920 A CN 103235920A CN 2013101588548 A CN2013101588548 A CN 2013101588548A CN 201310158854 A CN201310158854 A CN 201310158854A CN 103235920 A CN103235920 A CN 103235920A
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Abstract
The invention discloses a programmable logic device and an operating authorization control method thereof. The programmable logic device comprises a key logic unit and a storage unit. The key logic unit compares whether a first key right signal sent out by a single chip microcomputer is consistent with a pre-stored second key right signal or not, if the first key right signal is consistent with the second key right signal, an operation permission signal is sent to the storage unit, and if the first key right signal is not consistent with the second key right signal, an operation prohibition signal is sent. The storage unit starts or closes the operating authority of the storage unit by the single chip microcomputer according to the received operation permission signal or the received operation prohibition signal. Thus, when the operating authority of the storage unit is in a closed state, the single chip microcomputer is forbidden to operate the storage unit, if the single chip microcomputer operates the storage unit due to program errors of the single chip microcomputer or external disturbances on a local bus, the single chip microcomputer can not start the operating authority of the storage unit, and misoperation of the storage unit in a programmable logic device by the single chip microcomputer is reduced.
Description
Technical field
The present invention relates to microelectronic, relate to a kind of programmable logic device (PLD) and operating right control method thereof in particular.
Background technology
Programmable logic device (PLD) (being PLD) is widely used in microelectronic.It can finish the function of many digital devices, such as: the central processing unit of high-new energy and simple NAND gate circuit.
There is abundant storage resources programmable logic device (PLD) inside, and people link to each other by microcontroller bus programmable logic device (PLD) with single-chip microcomputer usually, with the external memory storage as single-chip microcomputer.When programmable logic device (PLD) during as the external memory storage of single-chip microcomputer, can be in the corresponding local bus of programmable logic device (PLD) internal composition and chip selection signal decoding logic, thus realize that single-chip microcomputer is to the read or write of programmable logic device (PLD).
But, when single-chip microcomputer is operated the storage unit in the programmable logic device (PLD), usually because the working procedure of singlechip makes a mistake or local bus is interfered, cause single-chip microcomputer that the storage unit in the programmable logic device (PLD) is carried out maloperation, thereby cause the data of programmable logic device (PLD) storage inside to make a mistake.
Summary of the invention
In view of this, the invention provides a kind of programmable logic device (PLD) and operating right control method thereof, to make a mistake in Single Chip Microcomputer (SCM) program or local bus when being interfered, reduce single-chip microcomputer to the maloperation situation of programmable logic device (PLD).
For achieving the above object, the invention provides following technical scheme:
A kind of programmable logic device (PLD), described programmable logic device (PLD) comprises: cipher key logic unit and the storage unit that links to each other with described cipher key logic unit;
Described cipher key logic unit, whether be used for comparing the first key authority signal that is sent by single-chip microcomputer consistent with the second key authority signal of storage in advance, if comparative result unanimity, then send to described storage unit and allow operation signal, if comparative result is inconsistent, then send the quiescing signal to described storage unit;
Described storage unit is used for permission operation signal or quiescing signal according to the transmission of described cipher key logic unit, opens or close described single-chip microcomputer to the operating right of described storage unit.
Preferably, described programmable logic device (PLD) also comprises: the interface logic unit that links to each other with described storage unit;
Wherein, described interface logic unit is used for when described storage unit is opened described operating right, and described interface logic unit receives first operation signal that single-chip microcomputer sends, and described first operation signal deciphered, export discernible second operation signal of described storage unit;
Described storage unit is used for operating accordingly according to described second operation signal when opening described operating right.
Preferably, described interface logic unit links to each other with described cipher key logic unit;
Wherein, described interface logic unit is used for receiving the described first key authority signal that described single-chip microcomputer sends, and the described first key authority signal is sent to described cipher key logic unit.
Preferably, described first operation signal comprises: read operation signal or write operation signal.
Preferably, described second operation signal comprises: read operation signal or write operation signal.
Preferably, described read operation signal comprises: chip selection signal, address signal and read enable signal;
Described chip selection signal is for the storage unit of choosing described programmable logic device (PLD);
Described address signal is for the address of the described storage unit of transmitting the read operation correspondence;
The described enable signal of reading is used for expression described storage unit is carried out read operation.
Preferably, described write operation signal comprises: chip selection signal, address signal, write enable signal and data-signal;
Described chip selection signal is for the storage unit of choosing described programmable logic device (PLD);
Described address signal is for the address of the described storage unit of transmitting the write operation correspondence;
The described enable signal of writing is used for expression described storage unit is carried out write operation;
Described data-signal comprises the data that need write described storage unit.
Preferably, described programmable logic device (PLD) comprises cipher key logic unit and storage unit, and described method comprises:
Described cipher key logic unit receives the first key authority signal that is sent by single-chip microcomputer, and whether the more described first key authority signal is consistent with the second key authority signal of storage in advance;
When described cipher key logic unit determines that the described first key authority signal is consistent with the described second key authority signal, send the permission operation signal to described storage unit;
When described cipher key logic unit determines that the described first key authority signal and the described second key authority signal are inconsistent, send the quiescing signal to described storage unit;
Described storage unit receives described permission operation signal or described quiescing signal, and according to described permission operation signal or described quiescing signal, opens or close described single-chip microcomputer to the operating right of described storage unit.
Preferably, described programmable logic device (PLD) also comprises: the interface logic unit that links to each other with described storage unit;
When the operating right opened described storage unit, described interface logic unit receives first operation signal that described single-chip microcomputer sends, and described first operation signal is deciphered, and exports discernible second operation signal of described storage unit;
Described storage unit is operated accordingly according to described second operation signal.
Via above-mentioned technical scheme as can be known, compared with prior art, the present invention openly provides a kind of programmable logic device (PLD) and operating right control method thereof.Programmable logic device (PLD) among the present invention comprises: cipher key logic unit and the storage unit that links to each other with the cipher key logic unit.Whether the comparison of cipher key logic unit is consistent with the second key authority signal of storage in advance by the first key authority signal that single-chip microcomputer sends, if the comparative result unanimity then sends to storage unit and allows operation signal; Otherwise, send the quiescing signal.Single-chip microcomputer is opened or closed to storage unit to the operating right of storage unit according to the permission operation signal or the quiescing signal that receive.As known from the above: when the operating right of storage unit is in closed condition, storage unit forbids that single-chip microcomputer operates on it, like this, when the singlechip program makes a mistake or local bus is subjected to external interference and when storage unit operated, this single-chip microcomputer can not be opened the operating right of storage unit, and then storage unit forbids that this single-chip microcomputer operates on it, thereby reduced the situation of single-chip microcomputer to the maloperation of storage unit in the programmable logic device (PLD).
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiments of the invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to the accompanying drawing that provides.
Fig. 1 shows the structural representation of an embodiment of a kind of programmable logic device (PLD) of the present invention;
Fig. 2 shows the structural representation of a kind of another embodiment of programmable logic device (PLD) of the present invention;
Fig. 3 shows the structural representation of a kind of another embodiment of programmable logic device (PLD) of the present invention;
Fig. 4 shows the schematic flow sheet of an embodiment of operating right control method of a kind of programmable logic device (PLD) of the present invention;
Fig. 5 shows the schematic flow sheet of another embodiment of operating right control method of a kind of programmable logic device (PLD) of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Referring to Fig. 1, show the structural representation of an embodiment of a kind of programmable logic device (PLD) of the present invention.In the present embodiment, this programmable logic device (PLD) comprises: cipher key logic unit 1 and the storage unit 2 that links to each other with this cipher key logic unit 1.
Wherein, cipher key logic unit 1, whether be used for comparing the first key authority signal that is sent by single-chip microcomputer consistent with the second key authority signal of storage in advance.When cipher key logic unit 1 determines that this first key authority signal is consistent with the second key authority signal, then send to storage unit 2 and allow operation signal; When cipher key logic unit 1 determines that this first cipher key logic signal and the second cipher key logic signal are inconsistent, then to storage unit 2 transmission quiescing signals.
Concrete, when this storage unit 2 received the permission operation signal of cipher key logic unit 1 transmission, storage unit 2 allowed operation signal according to this, opened single-chip microcomputer to the operating right of storage unit 2.
When storage unit 2 received the quiescing signal of cipher key logic unit 1 transmission, storage unit 2 was closed single-chip microcomputer to the operating right of storage unit 2 according to this quiescing signal.
Wherein, single-chip microcomputer comprises the operating right of storage unit 2: single-chip microcomputer is to write operation authority and the read operation authority of storage unit 2.This write operation authority be point to that single-chip microcomputer is rewritten these memory cell storage data or in the storage unit authority of storage data, the read operation authority refers to that then single-chip microcomputer is to the authority that reads of the data of this memory cell storage.
In the present embodiment, the form of the first key authority signal and the second key authority signal can variation.
In the above-described embodiment, when the operating right of storage unit was in opening, storage unit allowed single-chip microcomputer to operate on it, and when the operating right of storage unit was in closed condition, storage unit forbade that single-chip microcomputer operates on it.When the singlechip program makes a mistake or local bus is subjected to external interference and when directly storage unit being operated, because this single-chip microcomputer can not be opened the operating right of storage unit, thereby storage unit forbids that this single-chip microcomputer operates on it, thereby reduced the situation of single-chip microcomputer to the maloperation of storage unit in the programmable logic device (PLD).
In actual applications, programmable logic device (PLD) usually needs the instruction that single-chip microcomputer sends is deciphered, and compiling out storage unit 2 discernible operational orders in the programmable logic device (PLD), so the present invention further also discloses another embodiment.Referring to Fig. 2, show the structural representation of a kind of another embodiment of programmable logic device (PLD) of the present invention.Different with a last embodiment is that in the present embodiment, this programmable logic device (PLD) also comprises: the interface logic unit 3 that links to each other with storage unit 2.
This interface logic unit 3 links to each other with single-chip microcomputer by the single-chip microcomputer local bus.When storage unit 2 was opened the operating right that single-chip microcomputers operate on it, this interface logic unit 3 received first operation signal that single-chip microcomputers send, and first operation signal is deciphered, and compiles out storage unit 2 discernible second operation signals.Storage unit 2 receives second operation signal, and operates accordingly according to this second operation signal.Wherein, whether this first operation signal and second operation signal just can be identified by storage unit 2 in order to distinguish this operation signal.
Wherein, single-chip microcomputer can be multiple action type to the operation of the storage unit 2 of programmable logic device (PLD), such as: read operation and write operation.
When single-chip microcomputer carried out read operation to the storage unit 2 of programmable logic device (PLD), this first operation signal was the read operation signal, and corresponding second operation signal is storage unit 2 discernible read operation signals in the programmable logic device (PLD).This read operation signal comprises: for the chip selection signal of choosing programmable logic device memory elements 2, for the address signal of storage unit 2 addresses of transmitting the read operation correspondence and the enable signal of reading that storage unit is carried out read operation for expression.
When single-chip microcomputer carried out write operation to the storage unit 2 of programmable logic device (PLD), this first operation signal was write operation signal, and corresponding second operation signal is storage unit 2 discernible write operation signals in the programmable logic device (PLD).This write operation signal comprises: the data-signal of writing enable signal and need writing this storage unit 2 that storage unit is carried out write operation for the chip selection signal of choosing programmable logic device memory elements 2, for the address signal of storage unit 2 addresses of transmitting this write operation correspondence, for expression.
With single-chip microcomputer storage unit 2 being carried out read operation below is that example specifically describes.
Cipher key logic unit 1 receives the first key authority signal that single-chip microcomputer sends, and whether the second key authority signal of relatively storing in advance in the first key authority signal and the cipher key logic unit 1 is consistent.If cipher key logic unit 2 determines that this first key authority signal is consistent with this second key authority signal, then send to the storage unit 2 that links to each other with cipher key logic unit 1 and allow operation signal; If cipher key logic unit 1 definite this first key authority signal and this second key authority signal are inconsistent, then send the quiescing signals to the storage unit 2 that links to each other with cipher key logic unit 1.
When storage unit 2 open operation authorities are storage unit 2 when allowing single-chip microcomputers to operate on it, by the interface logic unit 3 that microcontroller bus links to each other with single-chip microcomputer, receive first operation signal of single-chip microcomputer transmission.This first operation signal comprises: for the chip selection signal of choosing programmable logic device memory elements 2, for the address signal of storage unit 2 addresses of transmitting this read operation correspondence and the enable signal of reading that storage unit 2 is carried out read operation for expression.The interface logic unit is to above-mentioned chip selection signal, address signal and read enable signal and decipher, and compiles out storage unit 2 discernible chip selection signals, the address signal of programmable logic device (PLD) and reads enable signal.Storage unit 2 is carried out read operation according to above-mentioned signal to the data of storage.
In a last embodiment, this cipher key logic unit 1 links to each other with single-chip microcomputer by microcontroller bus respectively with interface logic unit 3.Cipher key logic unit 1 receives the first key authority signal that single-chip microcomputer sends, and interface logic unit 3 receives first operation signal that single-chip microcomputer sends.
Further, for the less as much as possible interface microcontroller resource that takies, when this programmable logic device (PLD) was set, interface logic unit 3 can also link to each other with cipher key logic unit 1, referring to Fig. 3, show the structural representation of a kind of another embodiment of programmable logic device (PLD) of the present invention.
In the present embodiment, interface logic unit 3 receives the first key authority signal and first operation signal that single-chip microcomputer 4 sends, and this first key authority signal is sent to cipher key logic unit 2, rather than directly the first key authority signal is sent in the cipher key logic unit 2 by single-chip microcomputer 4, thereby saved taking interface microcontroller.
In addition, storage unit 2 inside are provided with logical AND gate circuit 21 and storer 22 in the present embodiment, and the input end of this logical AND gate circuit 21 links to each other with cipher key logic unit 1 respectively at interface logic unit 3, and output terminal links to each other with the read-write Enable Pin of storer 22.
When sending, cipher key logic unit 1 allows operation signal, when interface logic unit 3 sends second operation signal to storage unit 2, behind storage unit 2 internal logics and door 21, the read-write Enable Pin of storer 22 is high level, and this moment, storer 22 permission single-chip microcomputers operated on it.
When cipher key logic unit 1 sends the quiescing signal, when interface logic unit 3 sends second operation signal to storage unit 2, after storage unit 2 internal logic AND circuit 21, the read-write Enable Pin of storage unit 22 is low level, this moment, storer 22 was forbidden carrying out the read or write corresponding with this second operation signal, thereby had forbidden the read or write of single-chip microcomputer to storage unit.
In the above-described embodiment, a kind of concrete mode that realizes control programmable logic device memory elements 2 operating rights by key is only disclosed, the present invention adopts high level as the useful signal of the read-write Enable Pin of storer 22, but those skilled in the art also can adopt low level as the useful signal of the read-write Enable Pin of storage unit 22.
Simultaneously, the present invention also can adopt other logic gates realizations to the control of storage unit 2 operating rights except adopting the logical AND gate circuit.
Based on above programmable logic device (PLD), the present invention also provides a kind of programmable logic device (PLD) operating right control method, referring to Fig. 4, shows the schematic flow sheet of an embodiment of operating right control method of a kind of programmable logic device (PLD) of the present invention.This method may further comprise the steps:
401: the cipher key logic unit receives the first key authority signal that is sent by single-chip microcomputer, and relatively whether the first key authority signal is consistent with the second key authority signal of storage in advance.
Wherein, this second key authority signal is stored in the programmable logic device (PLD) cipher key logic unit in advance, the key authority signal that it can be set to fix, also the key authority signal that is temporarily write by those skilled in the art.
402: when the cipher key logic unit determines that the first key authority signal is consistent with the second key authority signal, then send to storage unit and allow operation signal.
When single-chip microcomputer need be operated storage unit, the first consistent cipher key logic signal of the second key authority signal of storing in advance with the cipher key logic unit that single-chip microcomputer sends to the cipher key logic unit, thereby the cipher key logic unit sends the permission operation signal to storage unit, allow operation signal so that storage unit receives, and then carry out the operation of subsequent step 404.
403: when the cipher key logic unit determines that the first key authority signal and the second key authority signal are inconsistent, then send the quiescing signal to storage unit.
After single-chip microcomputer is finished corresponding operation to storage unit, single-chip microcomputer sends the first key authority signal again to the cipher key logic unit, and the second key authority signal that the first key authority signal that this moment, single-chip microcomputer sent and cipher key logic unit are stored in advance is inconsistent, thereby the cipher key logic unit sends the quiescing signal to storage unit, and then carries out mark step 405.
404: when storage unit received the permission operation signal, storage unit was opened single-chip microcomputer to the operating right of storage unit according to allowing operation signal.
After the storage unit open operation authority, can allow single-chip microcomputer that it is carried out corresponding read-write operation.
405: when storage unit receives the quiescing signal, storage unit is closed single-chip microcomputer to the operating right of storage unit according to this quiescing signal.
By above-mentioned step as can be known: when the operating right of storage unit was in opening, storage unit allowed single-chip microcomputer to operate on it, and when the operating right of storage unit was in closed condition, storage unit forbade that single-chip microcomputer operates on it.When the singlechip program makes a mistake or local bus is subjected to external interference and when directly storage unit being operated, because this single-chip microcomputer can not be opened the operating right of storage unit, thereby storage unit forbids that this single-chip microcomputer operates on it, thereby reduced the situation of single-chip microcomputer to the maloperation of storage unit in the programmable logic device (PLD).
For programmable logic device (PLD) can identify the operation signal that single-chip microcomputer sends, finish the read or write that single-chip microcomputer is carried out storage unit with the operation information that sends according to single-chip microcomputer, this programmable logic device (PLD) also needs the operation signal that single-chip microcomputer sends is deciphered, with the discernible operation signal of the storage unit that compiles out this programmable logic device (PLD), accordingly, the present invention also provides a kind of programmable logic device (PLD) operating right control method, in the method, this programmable logic device (PLD) also comprises: the interface logic unit that links to each other with storage unit.Referring to Fig. 5, show the schematic flow sheet of another embodiment of operating right control method of a kind of programmable logic device (PLD) of the present invention.The method of present embodiment comprises:
501: the cipher key logic unit receives the first key authority signal that is sent by single-chip microcomputer, and relatively whether the first key authority signal is consistent with the second key authority signal of storage in advance.
Wherein, this second key authority signal is stored in the programmable logic device (PLD) cipher key logic unit in advance, it can be set to fixed key authority signal, the also key authority signal that is temporarily write by those skilled in the art, in practical operation, directly link to each other with single-chip microcomputer owing to the interface logic unit, single-chip microcomputer is sent to the interface logic unit with the first cipher key logic signal earlier, is sent to the cipher key logic unit by the interface logic unit again.
502: when the cipher key logic unit determines that the first key authority signal is consistent with the second key authority signal, then send to storage unit and allow operation signal.
When single-chip microcomputer need be operated storage unit, the first consistent cipher key logic signal of the second key authority signal of storing in advance with the cipher key logic unit that single-chip microcomputer sends to the cipher key logic unit, thereby the cipher key logic unit sends the permission operation signal to storage unit, allow operation signal so that storage unit receives, and then carry out the operation of subsequent step 504.
503: when the cipher key logic unit determines that the first key authority signal and the second key authority signal are inconsistent, then send the quiescing signal to storage unit.
After single-chip microcomputer is finished corresponding operation to storage unit, single-chip microcomputer sends the first key authority signal again to the cipher key logic unit, and the second key authority signal that the first key authority signal that this moment, single-chip microcomputer sent and cipher key logic unit are stored in advance is inconsistent, thereby the cipher key logic unit sends the quiescing signal to storage unit, and then carries out mark step 505.
504: when storage unit received the permission operation signal, storage unit was opened single-chip microcomputer to the operating right of storage unit according to allowing operation signal.
When storage unit open operation authority, single-chip microcomputer is operated the data in the storage unit, execution in step 506.
505: when storage unit received the quiescing signal, storage unit was closed single-chip microcomputer to the operating right of storage unit according to this quiescing signal.
Storage unit is closed single-chip microcomputer to the operating right of storage unit, when carrying out operating next time, need again to the input of cipher key logic unit and the consistent first cipher key logic signal of the second key authority signal, have only when the first cipher key logic signal is consistent with the second cipher key logic signal, this operating right just can be opened again.
506: when storage unit was opened single-chip microcomputer to the operating right of storage unit, the interface logic unit received first operation signal that single-chip microcomputer sends, and first operation signal is deciphered, discernible second operation signal of output storage unit.
Wherein, when single-chip microcomputer carried out read operation to the storage unit of programmable logic device (PLD), this first operation signal was the read operation signal, and corresponding second operation signal is the discernible read operation signal of storage unit in the programmable logic device (PLD).
When single-chip microcomputer carried out write operation to the storage unit of programmable logic device (PLD), this first operation signal was write operation signal, and corresponding second operation signal is the discernible write operation signal of storage unit in the programmable logic device (PLD).
507: storage unit is operated accordingly according to second operation signal.
When second operation signal was write operation, storage unit was the data that will write that second operation signal comprises, write with the corresponding address location of secondary signal in.
When second operation signal is read operation, storage unit read with the corresponding address location of second operation signal in data, and these data are sent to single-chip microcomputer.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. a programmable logic device (PLD) is characterized in that, described programmable logic device (PLD) comprises: cipher key logic unit and the storage unit that links to each other with described cipher key logic unit;
Described cipher key logic unit, whether be used for comparing the first key authority signal that is sent by single-chip microcomputer consistent with the second key authority signal of storage in advance, if comparative result unanimity, then send to described storage unit and allow operation signal, if comparative result is inconsistent, then send the quiescing signal to described storage unit;
Described storage unit is used for permission operation signal or quiescing signal according to the transmission of described cipher key logic unit, opens or close described single-chip microcomputer to the operating right of described storage unit.
2. programmable logic device (PLD) according to claim 1 is characterized in that, described programmable logic device (PLD) also comprises: the interface logic unit that links to each other with described storage unit;
Wherein, described interface logic unit is used for when described storage unit is opened described operating right, and described interface logic unit receives first operation signal that single-chip microcomputer sends, and described first operation signal deciphered, export discernible second operation signal of described storage unit;
Described storage unit is used for operating accordingly according to described second operation signal when opening described operating right.
3. programmable logic device (PLD) according to claim 2 is characterized in that, described interface logic unit links to each other with described cipher key logic unit;
Wherein, described interface logic unit is used for receiving the described first key authority signal that described single-chip microcomputer sends, and the described first key authority signal is sent to described cipher key logic unit.
4. programmable logic device (PLD) according to claim 1 is characterized in that, described first operation signal comprises: read operation signal or write operation signal.
5. programmable logic device (PLD) according to claim 1 is characterized in that, described second operation signal comprises: read operation signal or write operation signal.
6. according to claim 4 or 5 described programmable logic device (PLD), it is characterized in that described read operation signal comprises: chip selection signal, address signal and read enable signal;
Described chip selection signal is for the storage unit of choosing described programmable logic device (PLD);
Described address signal is for the address of the described storage unit of transmitting the read operation correspondence;
The described enable signal of reading is used for expression described storage unit is carried out read operation.
7. according to claim 4 or 5 described programmable logic device (PLD), it is characterized in that described write operation signal comprises: chip selection signal, address signal, write enable signal and data-signal;
Described chip selection signal is for the storage unit of choosing described programmable logic device (PLD);
Described address signal is for the address of the described storage unit of transmitting the write operation correspondence;
The described enable signal of writing is used for expression described storage unit is carried out write operation;
Described data-signal comprises the data that need write described storage unit.
8. the operating right control method of a programmable logic device (PLD) is characterized in that, described programmable logic device (PLD) comprises cipher key logic unit and storage unit, and described method comprises:
Described cipher key logic unit receives the first key authority signal that is sent by single-chip microcomputer, and whether the more described first key authority signal is consistent with the second key authority signal of storage in advance;
When described cipher key logic unit determines that the described first key authority signal is consistent with the described second key authority signal, send the permission operation signal to described storage unit;
When described cipher key logic unit determines that the described first key authority signal and the described second key authority signal are inconsistent, send the quiescing signal to described storage unit;
Described storage unit receives described permission operation signal or described quiescing signal, and according to described permission operation signal or described quiescing signal, opens or close described single-chip microcomputer to the operating right of described storage unit.
9. method according to claim 8 is characterized in that, described programmable logic device (PLD) also comprises: the interface logic unit that links to each other with described storage unit;
When the operating right opened described storage unit, described interface logic unit receives first operation signal that described single-chip microcomputer sends, and described first operation signal is deciphered, and exports discernible second operation signal of described storage unit;
Described storage unit is operated accordingly according to described second operation signal.
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| CN112789613A (en) * | 2018-10-19 | 2021-05-11 | Arm有限公司 | Parameter signatures for domain security configuration parameters |
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