CN103235228B - Method for testing cable line sequences rapidly and accurately - Google Patents
Method for testing cable line sequences rapidly and accurately Download PDFInfo
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- CN103235228B CN103235228B CN201310108650.3A CN201310108650A CN103235228B CN 103235228 B CN103235228 B CN 103235228B CN 201310108650 A CN201310108650 A CN 201310108650A CN 103235228 B CN103235228 B CN 103235228B
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Abstract
Disclosed is a method for testing cable line sequences rapidly and accurately. The method includes that eight ports with an AD (analog-to-digital) processors are respectively connected with eight copper cores of a cable line side A, the eight copper cores of the cable line side A are then respectively connected with eight terminals of an eight-selected-one switch, and a common terminal of the eight-selected-one switch is connected to the ground via a fifth resistor; eight copper cores of a cable side B are arranged in groups of two, and one resistor and one diode are connected between every two copper cores in series connection; and high-level signals are sent in turns by lines of the cable line side A, values of level signals returned to the lines of the cable line As from lines of the cable line side B via the diode and the resistor are read and stored in a result storage device, and a specific line sequence diagram is acquired through analysis of stored values. By the method, a specific line sequence result of the cable lines including open circuits, short circuits, misconnections and reverse connections of the cable lines can be tested rapidly and accurately by the aid of several groups of resistors and the eight-selected-one switch, and therefore, costs are saved, and speed is improved.
Description
Technical field
The present invention relates to telecommunications technical field of measurement and test, the equipment of test network line sequence often will be used to analyze the fault of network in telecommunications field tests.The present invention relates to the method for testing network line sequence fast and accurately.
Background technology
In the middle of telecommunications field tests, a lot of fault is all because the fault of netting twine causes, so first the first step measured will verify the correctness that netting twine connects.Now a lot of technology all just measures the break-make of netting twine, does not measure concrete line sequence.Sometimes need to know concrete line sequence, the such as difference of cross spider and direct-connected line.
Summary of the invention
The present invention seeks to the line sequence in order to measure netting twine fast and accurately, comprising the open circuit of netting twine, short circuit, misconnection and reversal connection.
The hardware configuration implementing the inventive method comprises:
1), the side a and b of netting twine: the side a and b of netting twine has 8 copper cores.Claim in the middle of hereafter A to hold n-th (n is arbitrary integer in 1 ~ 8) root copper core to be that the A of netting twine holds n line, claim B to hold n-th (n is arbitrary integer in 1 ~ 8) root copper core to be that the B of netting twine holds n line;
2), the processor of AD is with: the processor of band AD is used for sending the high level signal of test at the A end of netting twine and receiving the level signal turning back to A end from B end through diode and resistance, and carry out analysis to the different level signal turning back to A end to judge, to obtain the concrete outcome of outlet sequence;
3), four resistance (first to fourth resistance R1, R2, R3, R4) and four diodes (first to fourth diode D1, D2, D3, D4): by the resistance of these 4 different resistances, obtain under various line sequence, the difference turning back to the level signal of A end from B end through diode and resistance being with the processor of AD to receive;
4) switch of 1 and the resistance (the 5th resistance R5) of a ground connection, is selected for one 8.Receiving at the processor of band AD holds n line to turn back to through a resistance and diode the level signal that A holds n line from B, and 8 select the switch of 1 resistance of ground connection to be switched to A holds on n line.
As shown in Figure 1, as shown in Figure 2, implementation step of quick and precisely testing the method for network line sequence provided by the invention is as follows for whole flow processs of the inventive method for hardware configuration schematic diagram of the present invention:
The connection of step 1, realization test network line sequence hardware circuit used
Be connected by 8 copper cores that 8 ports of the processor of band AD are held with netting twine A respectively, 8 copper cores that netting twine A holds are connected 8 terminals that 8 select 1 switch respectively, 8 select the common port of 1 switch through the 5th resistance eutral grounding simultaneously; One group between two, 8 copper cores that netting twine B holds, each serial connection resistance and a diode between two copper cores, diode direction is pointed to 1 line by 2 lines respectively, pointed to 3 lines by 4 lines, is pointed to 5 lines and point to 7 lines by 8 lines by 6 lines;
Step 2, determine the Standard resistance range of 5 resistance according to the method realizing test network line sequence;
This method is by being with the processor of AD to send high level at the A end of netting twine, judging the concrete outcome of line sequence according to the value receiving the level signal turning back to A end from B end through diode and resistance; This just needs in not collinear sequence situation, the level signal received is different, the value of level signal is finally read out by the processor of band AD, and what read out is the AD value of level signal, and the AD value of level signal and the actual value of level signal have certain error, so require in error range, the AD value of the level signal read out under making not collinear sequence is different;
Through above-mentioned analysis, the resistance R of the first resistance
1, the resistance R of the second resistance
2, the resistance R of the 3rd resistance
3, the resistance R of the 4th resistance
4, the resistance R of the 5th resistance
5meet following condition:
Condition 1:V
12, V
34, V
56, V
78be less than the reference voltage V of the AD in the processor of band AD
benchmark.
Condition 2:V
12, V
34, V
56, V
78at the AD value AD of the correspondence that the processor of band AD reads out
12, AD
34, AD
56, AD
78different within the error range of AD, namely
AD
l2× (1 ± d%) ≠ AD
34 ×(1 ± d%) ≠ AD
56× (1 ± d%) ≠ AD
78× (1 ± d%) ≠ AD
short× (1 ± d%)
Wherein, the high level signal being with the processor of AD is V
high(unit volt), diode D is common diode, and conducting voltage is V
d(unit volt), in the processor of band AD, the reference voltage of AD is V
benchmark, the number of significant digit of AD is the number of significant digit of N, AD is N.The error of AD is: ± d%.
V
12for under correct line sequence, the processor of band AD is held 2 lines to send out high level signal at the A of netting twine to hold 2 lines to B, and the first diode D1 held through B and the first resistance R1 turns back to the actual value that A holds the level signal of 1 line.Computing formula is as shown in Equation (1):
AD
12for the AD value read out through band AD processor.Following formula (2) is utilized to calculate AD
12value;
V
34for under correct line sequence, the processor of band AD is held 4 lines to send out high level signal at the A of netting twine to hold 4 lines to B, and the second diode D2 held through B and the second resistance R2 turns back to the level signal actual value that A holds 3 lines.Computing formula is as shown in Equation (3):
AD
34for V
34through the AD value that band AD processor reads out.Following formula (4) is utilized to calculate AD
34value;
V
56for under correct line sequence, the processor of band AD is held 6 lines to send out high level signal at the A of netting twine to hold 6 lines to B, and the 3rd diode D3 held through B and the 3rd resistance R3 turns back to the level signal actual value that A holds 5 lines.Following formula (5) is utilized to calculate V
56value;
AD
56for V
56through the AD value that band AD processor reads out.Following formula (6) is utilized to calculate AD
56value;
V
78for under correct line sequence, the processor of band AD is held 8 lines to send out high level signal at the A of netting twine to hold 8 lines to B, and the 4th diode D3 held through B and the 4th resistance R4 turns back to the level signal actual value that A holds 7 lines.Following formula (5) is utilized to calculate V
78value;
AD
78for V
78through the AD value that band AD processor reads out.Following formula (8) is utilized to calculate AD
78value;
V
shortfor any wire and A in A end in netting twine hold other line short circuits when, processor with AD is when the A end of netting twine sends out high level signal at any wire, in the level signal actual value that A holds other lines to receive, the level signal received at other each lines is all the same;
At V
benchmark≤ V
hightime, V
short=V
benchmark.
V
shortthe AD value read out through band AD processor is AD
short, utilize following formula (9) to calculate V
shortthrough the AD value that band AD processor reads out;
The processor of step 3, band AD holds each line to send high level signal in turn at the A of netting twine, reads and holds each line to turn back to through diode and resistance the value that A holds the level signal of each line from B, and be stored in result memory.
The data storage of data field as line sequence result of data storage 8 × 1 character types in the processor of AD is with in definition, called after result memory, the data field defining data storage 8 × 1 integer types in the processor of band AD holds the level signal turning back to A end to pass through the data storage of the AD value that band AD processor reads out as receiving from B, two memories are reset by called after AD value memory.
Represent that netting twine A holds the sequence number of 8 lines with positive integer m, n, wherein the initial value of positive integer m is n+1.
Judge the value of n:
The initial value of positive integer n is 1; When n is less than or equal to 8, carry out step 3.1; Otherwise enter step 4;
Step 3.1. is with the processor of AD to hold n line to send high level signal to A
Judge the value of m:
When m is greater than 8, then carry out the operation of step 3.2; When m is less than or equal to 8, by the AD value read out through band AD processor of holding m line to receive at A, the level signal value holding m line to receive as A is also stored in m position in AD value memory.
Value in AD value memory is analyzed.
1) if the value of m position in AD value memory is at AD
short× (1-d%) and AD
shortbetween × (1+d%), then by the n-th position storage-n of result memory, by storage-n in m position in result memory;
2) if the value of m position in AD value memory is at AD
12× (1-d%) and AD
12between × (1+d%), and the value of the n-th position in result memory is zero or 2, then store 2 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 2, store 9 by the n-th position of result memory.If the value of m position is zero or 1 in result memory, then store 1 by m position of result memory; If the value storing wherein m position is greater than zero and is not 1, then store 9 by m position of result memory;
3) if the value of m position in AD value memory is at AD
34× (1-d%) and AD
34between × (1+d%), and the value of the n-th position in result memory is zero or 4, then store 4 by the n-th position of result memory; If the n-th value in result memory is greater than zero and is not 4, store 9 by the n-th position of result memory.If the value of m position is zero or 3 in result memory, then store 3 by m position of result memory; If the value of m position is greater than zero and is not 3 in result memory, then store 9 by m position of result memory;
4) if the value of m position in AD value memory is at AD
56× (1-d%) and AD
56between × (1+d%), and the value of the n-th position in result memory is zero or 6, then store 6 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 6, store 9 by the n-th position of result memory.If the value of m position is zero or 5 in result memory, then store 5 by m position of result memory; If the value of m position is greater than zero and is not 5, then store 9 by m position of result memory;
5) if the value of m position in AD value memory is at AD
78× (1-d%) and AD
78between × (1+d%), and the value of the n-th position in result memory is zero or 8, then store 8 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 8, then store 9 by the n-th position of result memory.If the value of m position is zero or 7 in result memory, then store 7 by m position of result memory; If the value of m position is greater than zero and is not 7 in result memory, then store 9 by m position of result memory;
If the value of m position not to meet in step 3.1 the 1st in AD value memory) ~ the 5th) any condition in step, then any change is not made to the value of result memory.
The numerical value of m adds 1, repeats the 2nd in above step 3.1) to the 5th) operation of step; When m is greater than 8, then carry out the operation of step 3.2;
Step 3.2. judges the value of n, and when n is less than or equal to 8, the processor of band AD holds n line to send out high level signal to A.Otherwise, enter step 4;
The initial value of positive integer m is 1, judges the value of m and the relation of n value
1) when m is less than or equal to n-1, the AD value through the level signal value being with AD processor to read out of holding m line to receive at A is stored in m position in AD value memory, repeat the 2nd in step 3.1) to the 5th) operation of step, the value in AD value memory is analyzed.
2) numerical value of m adds 1, rejudges the value of m, to repeat in above step 3.2 the 1st) operation of step; When m is greater than n-1, the numerical value of n adds 1, rejudges the value of n, repeats step 3.1; When n is greater than 8, the number stored in result memory is exactly the result of line sequence;
Value in step 4. pair result memory is analyzed, and draws concrete line sequence figure;
What deposit in the n-th position in result memory is m(m=1 ~ 8), represent that A holds n line and B to hold m line to be connected, if what store in memory n-th position is 0, then represent that A holds n line to be open circuit.If what store in memory n-th position is 9, then represent that A holds n line to be high resistant (i.e. input and output resistance is all very large).If what the n-th position stored is-m(m=1 ~ 7), then A holds n line and B to hold m short circuit.
Advantage of the present invention and beneficial effect:
The present invention utilizes several groups of resistance and 8 to select 1 switch can measure the concrete line sequence result of netting twine rapidly and accurately, cost-saving, improves speed.
Accompanying drawing illustrates:
Fig. 1 is hardware configuration schematic diagram of the present invention;
Fig. 2 is the flow chart of survey line sequence;
Fig. 3 is the flow chart of step 2;
Fig. 4 is the line sequence figure of netting twine to be tested;
Fig. 5 is the network line sequence figure after the present invention tests.
Detailed description of the invention
Embodiment
As shown in Figure 1, be connected by 8 copper cores that 8 ports of the processor of band AD are held with netting twine A respectively, 8 copper cores that netting twine A holds are connected 8 terminals that 8 select 1 switch respectively, 8 select the common port of 1 switch through the 5th resistance eutral grounding simultaneously; One group between two, 8 copper cores that netting twine B holds, each serial connection resistance and a diode between two copper cores, diode direction is pointed to 1 line by 2 lines respectively, pointed to 3 lines by 4 lines, is pointed to 5 lines and point to 7 lines by 8 lines by 6 lines.
The hardware configuration of the inventive method is described below in conjunction with an example: the processor of the band AD of selection is C8051F410, with 10 AD functions, diode is exactly common diode.Get out the netting twine having a specific network line sequence, as shown in Figure 4, two crystal heads of netting twine are connected on above the side a and b of two netting twines network line sequence respectively.
Step 1, determine the Standard resistance range of 5 resistance according to the method realizing test network line sequence;
This method is by being with the processor of AD to send high level at the A end of netting twine, holds the value of the level signal turning back to A end to judge the concrete outcome of line sequence according to receiving from B.This just needs in not collinear sequence situation, the level signal received is different, the value of level signal is finally read out by the processor of band AD, and what read out is the AD value of level signal, and the AD value of level signal has certain error, so the AD value of the level signal read out under not collinear sequence will be made to be different in error range;
The high level signal of C8051F410 is 3.3 volts, and the conducting voltage of diode is 0.58 volt.The number of significant digit of AD is 10, and the error of AD is: ± 2%
The value that can set resistance R5 is 10k, V
12, V
34, V
56, V
78these four level signal value first order several value according to the condition write before, setting V
12=2.1 volts, V
34=1.1 volts, V
56=0.75, V
78=0.325.The resistance calculating R1, R2, R3, R4 according to above-mentioned formula (1), formula (3), formula (5), formula (7) is respectively: 2.9k, 14.7k, 26k, 75k.AD is calculated according to formula (2), formula (4), formula (6), formula (8)
12, AD
34, AD
56, AD
78value be: 0x28b, 0x155,0xe8,0x64; AD is calculated according to formula (9)
shortvalue be 0x3FF.
The processor of step 2, band AD holds each line to send high level signal in turn at the A of netting twine, reads and holds each line to turn back to through diode and resistance the value that A holds the level signal of each line from B, and be stored in result memory.
Define the data storage of data field as line sequence result of data storage 8 × 1 character types in single-chip microcomputer, called after result memory, in definition single-chip microcomputer, the data field of data storage 8 × 1 integer types is as the data storage receiving the AD value that the level signal that turns back to A end from B end reads out through single-chip microcomputer, two memories are reset by called after AD value memory.
Represent that netting twine A holds the sequence number of 8 lines with positive integer m, n;
The initial value of positive integer n is 1, judges the value of n:
Now n=1 is less than 8, carry out step 2.1;
Step 2.1. single-chip microcomputer holds n line to send high level signal to A;
The value of positive integer m is 2, judges the value of m:
Now m=2 is less than 8, and the level signal value received holding 2 lines at A is stored in through the AD value that single-chip microcomputer reads out in the 2nd position in AD value memory.The value of the 2nd position in AD value memory is: 0x288;
Value in AD value memory is analyzed;
The value of the 2nd position in AD value memory be 0x288 between 0x28b × (1-2%) ~ 0x28b × (1+2%) because the 1st value in result memory is initial value 0, so store 2 by the 1st of result memory the position; Because the result value stored in the 2nd position is initial value 0, then store 1 by the 2nd of result memory the position;
The value of m adds 1, m and 3 is less than 8, and the level signal value received holding 3 lines at A is stored in through the AD value that single-chip microcomputer reads out in the 3rd position in AD value memory.The value of the 3rd position in AD value memory is: 0;
Value in AD value memory is analyzed;
The value of the 3rd position in AD value memory is 0, not to meet in step 2.1 the 1st) ~ the 5th) in any condition, then any change is not made to the value of result memory;
The value of m adds 1, m and 4 is less than 8, and the level signal value received holding 4 lines at A is stored in through the AD value that single-chip microcomputer reads out in the 4th position in AD value memory.The value of the 4th position in AD value memory is: 0;
Value in AD value memory is analyzed;
The value of the 4th position in AD value memory is 0, not to meet in step 2.1 the 1st) ~ the 5th) in any condition, then any change is not made to the value of result memory;
The value of m adds 1, m and 8 equals 8, and the level signal value received holding 8 lines at A is stored in through the AD value that single-chip microcomputer reads out in the 8th position in AD value memory.The value of the 8th position in AD memory is: 0;
Value in AD memory is analyzed;
The value of the 8th position in AD memory is 0, not to meet in step 2.1 the 1st) ~ the 5th) in any condition, then any change is not made to the value of result memory;
The value of m adds 1, m and 9 is greater than 8, carries out the operation of step 2.2;
Step 2.2. judges the value of n, and n 1 is less than 8, and single-chip microcomputer holds 1 line to send out high level signal to A;
The value of positive integer m is 1, judges the value of m: m is as being greater than n-1, and the numerical value of n adds 1, rejudges the value of n,
The value of n is 2, is less than 8.Repeat step 2.1;
The value of n is 8, equals 8.Repeat step 2.1;
The value of positive integer m is 8+1, judges the value of m:
9 are greater than 8, then carry out the operation of step 2.2;
Judge the value of n, n equals 8, and single-chip microcomputer holds 8 lines to send out high level signal to A;
The value of positive integer m is 1, judges the value of m: m 1 is less than 7, and the level signal value received holding 1 line at A is stored in through the AD value that single-chip microcomputer reads out in the 1st position in AD value memory, and the value of the 1st position in AD value memory is: 0;
Value in AD value memory is analyzed;
The value of the 1st position in AD value memory is 0, not to meet in step 2.1 the 2nd) ~ the 5th) in any condition, then any change is not made to the value of result memory;
The value of m adds 1, m and 2 is less than 7, and the level signal value received holding 2 lines at A is stored in through the AD value that single-chip microcomputer reads out in the 2nd position in AD value memory.The value of the 2nd position in AD value memory is: 0;
Value in AD value memory is analyzed;
The value of the 2nd position in AD value memory is 0, not to meet in step 2.1 the 2nd) ~ the 5th) in any condition, then any change is not made to the value of result memory;
It is that to add 1 be 9 to 8 numerical value being greater than 7, n that the value of m adds 1, m, rejudges the value of n, and n 9 is greater than 8, enters step 3;
Value in step 3. pair result memory is analyzed, and draws concrete line sequence figure;
The value of 8 positions of result memory is respectively: 2,1,5,6,0,0 ,-7 ,-7.So concrete line sequence result is that A holds 2 lines and B to hold 1 line to be connected, A holds 1 line and B to hold 2 lines to be connected, and A holds 3 lines and B to hold 5 lines to be connected, and A end 4 holds 6 lines to be connected with B, and A holds 5 line open circuits, and A holds 6 line open circuits.A holds 7 lines and A to hold 8 line short circuits.Result as shown in Figure 5.Can see, Fig. 4 with Fig. 5 is consistent.
Claims (1)
1. quick and precisely test a method for network line sequence, it is characterized in that the implementation step of the method is as follows:
The connection of step 1, realization test network line sequence hardware circuit used
Be connected by 8 copper cores that 8 ports of the processor of band AD are held with netting twine A respectively, 8 copper cores that netting twine A holds are connected 8 terminals that 8 select 1 switch respectively, 8 select the common port of 1 switch through the 5th resistance eutral grounding simultaneously; One group between two, 8 copper cores that netting twine B holds, each serial connection resistance and a diode between two copper cores, diode direction is pointed to 1 line by 2 lines respectively, pointed to 3 lines by 4 lines, is pointed to 5 lines and point to 7 lines by 8 lines by 6 lines;
Step 2, determine the condition of 5 resistance demand fulfillment according to the method realizing test network line sequence;
By being with the processor of AD to send high level at the A end of netting twine, judge the concrete outcome of line sequence according to the value receiving the level signal turning back to A end from B end through diode and resistance; This just needs in not collinear sequence situation, the level signal received is different, the value of level signal is finally read out by the processor of band AD, and what read out is the AD value of level signal, and the AD value of level signal and the actual value of level signal have certain error, so require in error range, the AD value of the level signal read out under making not collinear sequence is different;
Therefore, the resistance R of the first resistance
1, the resistance R of the second resistance
2, the resistance R of the 3rd resistance
3, the resistance R of the 4th resistance
4, the resistance R of the 5th resistance
5meet following condition:
Condition 1:V
12, V
34, V
56, V
78be less than the reference voltage V of the AD in the processor of band AD
benchmark;
Condition 2:V
12, V
34, V
56, V
78at the AD value AD of the correspondence that the processor of band AD reads out
12, AD
34, AD
56, AD
78different within the error range of AD, namely
Wherein, the high level signal being with the processor of AD is V
high, unit lies prostrate, and diode D is common diode, and conducting voltage is V
d, in the processor of band AD, the reference voltage of AD is V
benchmark, to be the error of N, AD be for the number of significant digit of AD: ± d%; And,
V
12for under correct line sequence, the processor of band AD is held 2 lines to send out high level signal at the A of netting twine to hold 2 lines to B, and turn back to through the first diode D1 of B end and the first resistance R1 the actual value that A holds the level signal of 1 line, calculating is as shown in formula (1):
AD
12for the AD value read out through band AD processor, following formula (2) is utilized to calculate AD
12value;
V
34for under correct line sequence, the processor of band AD is held 4 lines to send out high level signal at the A of netting twine to hold 4 lines to B, and turn back to through the second diode D2 of B end and the second resistance R2 the level signal actual value that A holds 3 lines, calculating is as shown in formula (3):
AD
34for V
34through the AD value that band AD processor reads out, following formula (4) is utilized to calculate AD
34value;
V
56for under correct line sequence, the processor of band AD is held 6 lines to send out high level signal at the A of netting twine to hold 6 lines to B, and the 3rd diode D3 held through B and the 3rd resistance R3 turns back to the level signal actual value that A holds 5 lines; Following formula (5) is utilized to calculate V
56value;
AD
56for V
56through the AD value that band AD processor reads out, following formula (6) is utilized to calculate AD
56value;
V
78for under correct line sequence, the processor of band AD is held 8 lines to send out high level signal at the A of netting twine to hold 8 lines to B, and the 4th diode D3 held through B and the 4th resistance R4 turns back to the level signal actual value that A holds 7 lines, utilizes following formula (7) to calculate V
78value;
AD
78for V
78through the AD value that band AD processor reads out, following formula (8) is utilized to calculate AD
78value;
V
shortfor any wire and A in A end in netting twine hold other line short circuits when, processor with AD is when the A end of netting twine sends out high level signal at any wire, in the level signal actual value that A holds other lines to receive, the level signal received at other each lines is all the same;
At V
benchmark≤ V
hightime, V
short=V
benchmark;
V
shortthe AD value read out through band AD processor is AD
it is short,following formula (9) is utilized to calculate V
shortthrough the AD value that band AD processor reads out;
The processor of step 3, band AD holds each line to send high level signal in turn at the A of netting twine, reads and holds each line to turn back to through diode and resistance the value that A holds the level signal of each line from B, and be stored in result memory
The data storage of data field as line sequence result of data storage 8 × 1 character types in the processor of AD is with in definition, called after result memory, the data field defining data storage 8 × 1 integer types in the processor of band AD holds the level signal turning back to A end to pass through the data storage of the AD value that band AD processor reads out as receiving from B, two memories are reset by called after AD value memory;
Represent that netting twine A holds the sequence number of 8 lines with positive integer m, n, wherein the initial value of positive integer m is n+1;
Judge the value of n:
The initial value of positive integer n is 1; When n is less than or equal to 8, carry out step 3.1; Otherwise enter step 4;
Step 3.1. is with the processor of AD to hold n line to send high level signal to A
Judge the value of m:
When m is greater than 8, then carry out the operation of step 3.2; When m is less than or equal to 8, by the AD value read out through band AD processor of holding m line to receive at A, the level signal value holding m line to receive as A is also stored in m position in AD value memory;
Value in AD value memory is analyzed
1) if the value of m position in AD value memory is at AD
short× (1-d%) and AD
shortbetween × (1+d%), then by the n-th position storage-n of result memory, by storage-n in m position in result memory;
2) if the value of m position in AD value memory is at AD
12× (1-d%) and AD
12between × (1+d%), and the value of the n-th position in result memory is zero or 2, then store 2 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 2, store 9 by the n-th position of result memory; If the value of m position is zero or 1 in result memory, then store 1 by m position of result memory; If the value storing wherein m position is greater than zero and is not 1, then store 9 by m position of result memory;
3) if the value of m position in AD value memory is at AD
34× (1-d%) and AD
34between × (1+d%), and the value of the n-th position in result memory is zero or 4, then store 4 by the n-th position of result memory; If the n-th value in result memory is greater than zero and is not 4, store 9 by the n-th position of result memory; If the value of m position is zero or 3 in result memory, then store 3 by m position of result memory; If the value of m position is greater than zero and is not 3 in result memory, then store 9 by m position of result memory;
4) if the value of m position in AD value memory is at AD
56× (1-d%) and AD
56between × (1+d%), and the value of the n-th position in result memory is zero or 6, then store 6 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 6, store 9 by the n-th position of result memory; If the value of m position is zero or 5 in result memory, then store 5 by m position of result memory; If the value of m position is greater than zero and is not 5, then store 9 by m position of result memory;
5) if the value of m position in AD value memory is at AD
78× (1-d%) and AD
78between × (1+d%), and the value of the n-th position in result memory is zero or 8, then store 8 by the n-th position of result memory; If the value of the n-th position in result memory is greater than zero and is not 8, then store 9 by the n-th position of result memory; If the value of m position is zero or 7 in result memory, then store 7 by m position of result memory; If the value of m position is greater than zero and is not 7 in result memory, then store 9 by m position of result memory;
If the value of m position not to meet in step 3.1 the 1st in AD value memory) ~ the 5th) any condition in step, then any change is not made to the value of result memory;
The numerical value of m adds 1, repeats the 2nd in step 3.1) to the 5th) operation of step; When m is greater than 8, then carry out the operation of step 3.2;
Step 3.2. judges the value of n, and when n is less than or equal to 8, the processor of band AD holds n line to send out high level signal to A; Otherwise, enter step 4;
The initial value of positive integer m is 1, judges the value of m and the relation of n value
1) when m is less than or equal to n-1, the AD value through the level signal value being with AD processor to read out of holding m line to receive at A is stored in m position in AD value memory, repeat the 2nd in step 3.1) to the 5th) operation of step, the value in AD value memory is analyzed;
2) numerical value of m adds 1, repeats the 1st in above step 3.2) operation of step; When m is greater than n-1, the numerical value of n adds 1, rejudges the value of n, repeats step 3.1; When n is greater than 8, the number stored in result memory is exactly the result of line sequence;
Value in step 4. pair result memory is analyzed, and draws concrete line sequence figure;
What deposit in the n-th position in result memory is m, m=1 ~ 8, represents that A holds n line and B to hold m line to be connected, if what store in memory n-th position is 0, then represents that A holds n line to be open circuit; If what store in memory n-th position is 9, then represent that A holds n line to be high resistant, i.e. input and output resistance is all very large; If what the n-th position stored is-m, m=1 ~ 7, then A holds n line and B to hold m short circuit.
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