CN103219239B - Method for manufacturing AlGaN/GaN HEMT (High Electron Mobility Transistor) with high thermal stability - Google Patents
Method for manufacturing AlGaN/GaN HEMT (High Electron Mobility Transistor) with high thermal stability Download PDFInfo
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Abstract
The invention provides a method for manufacturing an AlGaN/GaN HEMT (High Electron Mobility Transistor). The method for manufacturing the AlGaN/GaN HEMT with the high thermal stability is characterized in that a grid electrode of the AlGaN/GaN HEMT adopts a schottky grid structure; a schottky grid electrode of the schottky grid structure consists of a potential barrier metal layer and a grid cap metal layer; the potential barrier metal layer consists of a WN metal layer and a W metal layer in sequence from the surface of a potential barrier layer; the grid cap metal layer comprises multiple layers of metal systems, Ti/Pt/Au/Ti, Ti/Pt/Au/Pt/Ti and Ti/Pt/Au/Ni; the grid electrode also adopts a schottky grid structure in the form of a groove grid; the schottky grid electrode of the schottky grid structure in the form of the groove grid also consists of the potential barrier metal layer and the grid cap metal layer; and the difference of the schottky grid electrode of the schottky grid structure in the form of the groove grid is that a groove is formed in the potential barrier layer after part of the potential barrier layer touching the potential barrier metal layer is removed. The method for manufacturing the AlGaN/GaN HEMT with the high thermal stability has the advantages that the manufacture is easy and the manufactured component has a better temperature resistance characteristic to meet the requirement of higher temperature work.
Description
Technical field
What the present invention relates to is a kind of AlGaN/GaN HEMT manufacture method of applicable aluminum gallium nitride compound/GaN high electron mobility transistor.
Background technology
Aluminum gallium nitride compound/GaN high electron mobility transistor has the features such as power output is large, operating frequency is high, high temperature resistant as third generation wide bandgap compound semiconductor device, applicable millimeter involves the high-power applications of following frequency range, and this makes it become the focus of semiconductor microwave power device research in recent years.Power output aspect, the output power density of disclosed small size AlGaN/GaN HEMT can reach more than 30W/mm (Wu et al. IEEE Electron Device Lett. at present, Vol.25, No.3, pp.117-119, 2004.), large-size device single-chip continuous wave output power has also reached more than 100W (Nagy et al. IEEE MTT-S International Microwave Symposium Digest, pp.483-486, 2005.), pulse power exports and even reaches 368W(Therrien et al. IEEE IEDM Tech. Digest, pp.568-571, 2005.), operating frequency aspect, disclosed AlGaN/GaN HEMT microwave power device operating frequency reaches 3mm frequency range (M. Micovic et al., IEEE IMS Symp. Dig., pp.237-239,2006.) at present, high-temperature stability aspect, disclosed AlGaN/GaN HEMT microwave power device working junction temperature reaches as high as 225 DEG C of (Donald A. Gajewski et al. at present, 26th Annual JEDEC ROCS Workshop, pp.141-145,2011), far above the existing BJT based on Si and LDMOS device, also far above devices such as GaAs pHEMT and HFET.
The high-temperature stability aspect of AlGaN/GaN HEMT device, have benefited from the high-temperature stability in material itself on the one hand, the Debye temperature of GaN material is up to more than 700 DEG C, far above Si and GaAs material, thus ensure that device has lower concentration of background carriers at a higher temperature, make device have higher operational temperature.Certainly only have good material behavior or inadequate, also need the thermal stability of gate electrode in device to ensure in addition, namely when hot operation, device gate electrode can also form the effective control to charge carrier in raceway groove.
The gate electrode form of current AlGaN/GaN HEMT mainly contains schottky gate electrode and metal-insulator semiconductor (MIS) structure gate electrode two kinds of forms.In schottky gate electrode form, gate electrode metal directly contacts with the semiconductor layer of AlGaN/GaN HEMT device, metal and semiconductor form Schottky rectifying contact, are formed and realize the work of device by applying different grid voltages to the control of carrier concentration in device channel on gate electrode.In AlGaN/GaN HEMT device Schottky gate structure, the most frequently used at present as the metal level forming Schottky rectifying contact with device semiconductor layer is W metal, experimental result shows that the Schottky contacts that Ni and AlGaN/GaN HEMT device is formed has good thermal stability below 400 DEG C, but when temperature is more than 400 DEG C, because the reaction of Ni metal and AlGaN/GaN HEMT device semiconductor layer or other factors can cause the degeneration of Characteristics of Schottky Barrier, time serious, also component failure can be caused.
In another structure of AlGaN/GaN HEMT device gate electrode and metal-insulator semiconductor structure, insulated gate AlGaN/GaN HEMT is made by introducing the insulating barrier with high breakdown field strength under device gate metal electrode, the benefit done like this is that grid metal does not directly contact with semiconductor, there is not the danger that metal and semiconductor at high temperature react.Insulating barrier in insulated gate AlGaN/GaN HEMT can be taken on by the material of various ways, is SiO as the people such as Khan (Khan et al. Appl. Phys. Letters, Vol.77, p.1339,2000) disclose insulating barrier
2insulated gate AlGaN/GaN HEMT, wherein SiO
2insulating barrier adopts PECVD deposition process to obtain; The people such as Hu (Hu et al. Appl. Phys. Letters, Vol.79, p.2832,2000) then disclose the insulated gate AlGaN/GaN HEMT that insulating barrier is silicon nitride (SiN), wherein SiN insulating barrier adopts PECVD deposition process to obtain; The people such as Ye (Ye et al. Appl. Phys. Letters, Vol.86, p.2832,2005) disclose the alundum (Al2O3) (Al that insulating barrier is employing atomic layer deposition fabrication techniques
2o
3) insulated gate AlGaN/GaN HEMT.
Although avoid the possibility that grid metal and semiconductor interface at high temperature react after touch in insulated gate AlGaN/GaN HEMT device, but there is the surface state of higher density in AlGaN/GaN HEMT device surface, this is one of the main reasons (the R.Vetury et al. IEEE.Trans Electron Devices causing AlGaN/GaN HEMT device current collapse, Vol.48, No.3, pp.560-566,2001).On AlGaN/GaN HEMT semiconductor layer after deposit one insulating barrier, the surface state of semiconductor layer surface gesture will introduce a highdensity interfacial state between semiconductor and insulator layer, this can cause the drift of threshold voltage in device operation, cause other integrity problems, the gate electrode that therefore up to the present AlGaN/GaN HEMT product adopts all have employed the form of Schottky gate instead of the form of insulated gate simultaneously.
In view of the problems existed in insulated gate structure AlGaN/GaN HEMT, want the thermal stability improving AlGaN/GaN HEMT further, only have and the Schottky contact metal layer in Schottky gate structure AlGaN/GaN HEMT is made improvements, further promoted to make the thermal stability of itself and semiconductor layer.In GaAs pHEMT device manufacturing processes, be the thermal stability of boost device, usually adopt metal W as the Schottky contact metal (F. Benkhelifa et al. GaAs Manufacturing Technology Conference, 2001.) of device.Because the fusing point of W is up to 3410 DEG C, the fusing point 1453 DEG C comparing W metal is much higher, the probability that itself and semiconductor react also will be reduced greatly, therefore can carry out the thermal stability of further boost device as the Schottky contact metal of AlGaN/GaN HEMT.
W can also by with gas N
2reaction generates WN alloy, and WN alloy the simplest implementation method in semiconductor fabrication process is obtained by magnetron sputtering.The principle of being carried out metal level deposit by sputtering is the Ar gas bombardment metallic target source utilizing ionization, atom bombardment in metallic target source is out deposited to afterwards semiconductor surface and forms required metal level, the object of magnetic control reaches to increase effective Ar ion source the object accelerating deposition rate.Acquisition for WN alloy can add N in Ar gas
2gas component, N in the process of Ar gas ionization
2gas have also been obtained ionization, the W atom produced behind other bombardment W target sources of Ar and the N after ionizing
2gas combination is deposited on semiconductor surface and just can obtains WN alloying metal layer.WN and W is the same not easily to react with the semiconductor layer in AlGaN/GaN HEMT, and experiment simultaneously shows, it is higher that the schottky barrier height that the schottky barrier height that WN and AlGaN/GaN HEMT is formed is formed than W and AlGaN/GaN HEMT comes.According to Semiconductive Theory, high schottky barrier height contributes to the leakage current reducing schottky junction, thus contributes to improving the electrical characteristics such as device electric breakdown strength.The disadvantageous one side of WN alloy be compare W metal its more easily and alkaline chemical react, and the chemical substances such as developer solution used in AlGaN/GaN HEMT manufacture process have stronger alkalescence, WN alloy is probably subject to the corrosion of the chemical substances such as developer solution in the fabrication process, has a negative impact to the device reliability manufactured.Therefore need to invent a kind of method, make full use of the advantage of WN alloy and W two kinds of metals, obtain AlGaN/GaN HEMT device that is highly reliable, high thermal stability.
Summary of the invention
The invention provides a kind of AlGaN/GaN HEMT manufacture method adopting applicable aluminum gallium nitride compound/GaN high electron mobility transistor, is that one have employed WN/W barrier metal layer Schottky gate structure AlGaN/GaN HEMT device manufacture method concretely.
Technical solution of the present invention: a kind of AlGaN/GaN HEMT manufacture method, it is characterized in that: on the barrier layer of the epitaxial material of AlGaN/GaN HEMT employing, deposited metal is as device source electrode and drain electrode, makes source electrode and drain electrode and semiconductor epitaxial material form ohmic contact by high temperature alloy; Dielectric layer deposited on the surface of source electrode, drain electrode and barrier layer; Dielectric layer applies photoresist layer and by defining a window in photoresist layer between device source electrode and drain electrode of the method for photoetching; Photoresist layer is utilized to remove the dielectric layer in window as mask and remove the grid pin window that photoresist layer obtains leading in dielectric layer barrier layer surface; In the sidewall and grid pin bottom of window of dielectric layer, grid pin window, deposit WN metal level and W metal level obtain barrier metal layer successively the surface of barrier layer; Barrier metal layer applies photoresist layer, by photoetching, is developed in the grid cover window carved and define complete covering gate pin window in glue-line; Evaporation grid cover metal level to the bottom of grid cover window, the surface of sidewall and photoresist layer; Peel off remove photoresist layer and on metal level, only leave the grid cover metal level in window; Grid cover metal level described in utilization removes the barrier metal layer except the barrier metal layer below the aforementioned grid cover metal level stayed as mask large area etching.
Advantage of the present invention: easily manufacture realization, manufactured device has better resistance to temperature characterisitic, and the device that temperature resistance can manufacture than existing common process is high more than 100 DEG C; Meet higher temperature requirements of one's work, most high workload junction temperature can reach more than 225 DEG C.
Accompanying drawing explanation
Fig. 1 be AlGaN/GaN HEMT adopt the general structure schematic diagram of epitaxial material.
Fig. 2-Figure 10 is the implementation step of embodiments of the invention 1.
Figure 11-Figure 13 express possibility exist grid cover window cover forbidden situation.
Figure 14-Figure 19 is the implementation step of the embodiment of the present invention 2.
Specific embodiment
Contrast Fig. 1, be AlGaN/GaN HEMT adopt the general structure of epitaxial material, include substrate 1, GaN resilient coating 2 and AlGaN potential barrier 3.Formed can report with reference to pertinent literature about material, GaN resilient coating 2 and AlGaN potential barrier 3 that substrate 1 in AlGaN/GaN HEMT is used; In addition Fig. 1 be AlGaN/GaN HEMT adopt the general structure schematic diagram of epitaxial material, show the epitaxial material structure that also there is other form, other version with reference to pertinent literature, can be not described further.
Embodiment 1
Contrast Fig. 2-Figure 10, implementation step, first as shown in Figure 2 in AlGaN potential barrier 3, deposited metal forms source electrode 4 and the drain electrode 5 with certain intervals distance, source electrode 4 and drain electrode 5 can adopt and include but are not limited to Ti/Al/Ni/Au, the multiple layer metal systems such as Ti/Al/Mo/Au, the metal level of source electrode and drain electrode generally needs to form good ohmic contact with the semiconductor epitaxial layers under it by high temperature alloy, numerous bibliographical information is had about source electrode 4 and the adoptable metal system of drain electrode 5 and the alloy condition that will take for obtaining best ohmic contact, repeat no more herein.
Deposit one dielectric layer 6 on source electrode 4, drain electrode 5 and barrier layer 3; protection or passivation are played to source electrode 4, drain electrode 5 and barrier layer 3; the selectable material of dielectric layer 6 includes but are not limited to SiN, SiO2 etc., preferably SiN, and preferred thickness is 50nm-300nm.As shown in Figure 3.
Dielectric layer 6 applies photoresist layer 7, and form window 8 in the photoresist layer of the step such as photoetching, development between source electrode 4 and drain electrode 5, the width of window 8 between source electrode 4 and drain electrode 5 is determined according to the device gate that will develop is long.As shown in Figure 4.
With photoresist layer 7 for mask, the method of dry plasma is adopted to be removed by the dielectric layer 6 in window 8, and on dielectric layer 6, after removing the photoresist on dielectric layer 6, be referred to as the window 9 of grid pin as shown in Figure 5, the method that dry plasma removes the dielectric materials such as SiN, SiO2 is well-known in this area, can report with reference to pertinent literature, repeat no more herein.
The method obtaining barrier metal layer 10, WN and the deposit of W metal level in the sidewall of dielectric layer 6, grid pin window 9 and bottom deposit successively deposit WN metal level and W metal level includes but not limited to chemical vapor deposition and sputtering.The method of chemical vapor deposition WN metal level can see the people such as T.Nakajima (T.Nakajima et al. J.Electrochem.Soc., Vol.134, p.3175, 1987.) report, the method of sputtering deposit WN can see the people such as N.Uchitomi (N.Uchitomi et al. J.Vac.Sci.Technol.B, Vol.4, No.6, p.1392, 1986) or people (the A.E.Gisserger et al. J.Vac.Technol.A such as A.E.Gisserger, Vol.4, No.6, p.3091, 1986) or people (the L.Boukhris et al. Thin Solid Films such as L.Boukhris, Vol.310, p.222, 1997) report, the method of chemical vapor deposition W metal level can see the people such as Y.T.Kim (Y.T.Kim et al. Appl.Phys.Lett., Vol.58, No.8, p.330,1993) report, the method for sputtering W metal level is a kind of processing method of routine in this area, repeats no more herein.In the present invention, preferred WN and W metal layer deposition method is the mode of sputtering, in this area, the equipment of sputtering deposit metallic film can add the plasma that formed in Magnetic control sputter procedure to strengthen the density of effective plasma toward contact, the sputtering carried out in this equipment is referred to as magnetron sputtering, direct current sputtering and radio frequency sputtering is divided in addition according to the difference of the power supply adopted in sputter procedure, adopt in sputter procedure during DC power supply and be referred to as direct current sputtering, adopt during radio-frequency power supply and be then referred to as radio frequency sputtering, in the present invention, WN and W metal level preferably adopts the mode deposit of magnetically controlled DC sputtering.The preferred thickness of barrier metal layer 10 is 50nm-300nm, and wherein the preferred thickness of WN metal level is the preferred thickness of 30nm-100nm, W metal level is 20nm-200nm.
On barrier metal layer 10, apply photoresist layer 11, and form window 12 as shown in Figure 7 in photoresist layer 11 on aforesaid grid pin window 9 after the operation such as photoetching, development, window 12 also can be referred to as grid cover window.Must ensure in the design of grid cover window 12 and forming process grid pin window 9 completely cover by grid cover window 12, grid pin window 9 some or all of not the situation that covers by grid cover window 12 must avoid in the present invention.
As shown in figures 11-13, grid pin window 9 part not cover by grid cover window 12 citing of situation, in Figure 11 the right side of grid pin window 9 have part not cover by grid cover window 12, in Figure 12 the left side of grid pin window 9 have part not cover by grid cover window 12, in Figure 13 grid pin window 9 all not cover by grid cover window 12, Figure 11-Figure 13 be grid pin window 9 some or all of not the citing that covers by grid cover window 12, certainly also exist other grid pin windows 9 some or all of not the situation that covers by grid cover window 12, here will not enumerate.Avoid occurring grid pin window 9 some or all of not the problem that covers by grid cover window 12, first grid cover window 12 designs that upper will to ensure than window 9 large, the lithographic equipment that employing has a more high registration accuracy on this basis just can avoid occurring grid pin window 9 some or all of not the problem that covers by grid cover window 12.
Deposit grid cover metal level 13 in barrier metal layer 10 in photoresist layer 11 and grid cover window 12, the object of grid cover metal level 13, an aspect is that subsequent etching barrier metal layer 10 plays mask effect, and another one effect is the grid resistance reducing device, the frequency characteristic of boost device.Grid cover metal level preferably adopts the mode of evaporation to carry out deposit, or adoptable metal includes but not limited to the multiple layer metal systems such as Ti/Pt/Au/Ti or Ti/Pt/Au/Pt/Ti Ti/Pt/Au/Ni, wherein the effect of metal Ti plays the adhesiveness strengthened between barrier metal layer 10 and grid cover metal level 13, its thickness preferably 20nm-100nm; Pt metal between Ti and Au is the effect playing isolation Ti and Au, and avoid Au and Ti to react, its preferred thickness is 30nm-50nm; Au mainly plays the effect reducing device grid resistance, and its preferred thickness is 400nm-600nm; The metal levels such as Ti or Pt/Ti on Au or Ni mainly subsequent etching barrier metal layer 10 play mask effect, the selection of thickness is relevant to the thickness of barrier metal layer 10, when the barrier metal layer ensureing except the barrier metal layer 10 below grid cover metal level 13 is etched and removes, the metal levels such as Ti or Pt/Ti on Au or Ni still have residue, as shown in Figure 8.
Adopt stripping technology remove photoresist layer 11 and on grid cover metal level 13 after obtain as shown in Figure 9 figure, be well-known in this area about stripping technology, repeat no more herein.
Utilize the grid cover metal level 13 in Fig. 9 to be mask, the method barrier metal layer removed except the barrier metal layer 10 below grid cover metal level 13 of employing dry plasma obtains device as shown in Figure 10.The dry plasma method that can adopt comprises reactive ion etching and inductively coupled plasma etching etc., and in the present invention, preferred dry plasma method is inductively coupled plasma etching.In dry plasma process, available reacting gas comprises sulphur hexafluoride (SF
6), carbon tetrafluoride (CF
4), chlorine (Cl
2), boron chloride (BCl
3) etc., in the present invention, preferred gas is BCl
3, therefore the present invention preferably adopts based on BCl
3the inductively coupled plasma etching of reacting gas removes the barrier metal layer except the barrier metal layer 10 below grid cover metal level 13.
Embodiment 2
Contrast Figure 14-Figure 19, implementation step, first with in embodiment 1 shown in Fig. 2, barrier layer 3 forms source electrode 4 and drain electrode 5; Deposit protective dielectric layer 6 as shown in Figure 3 afterwards, preferred dielectric layer material and thickness are with embodiment 1; Dielectric layer 6 applies photoresist layer 7 and in photoresist layer 7, obtains window 8 as shown in Figure 4 through techniques such as development, exposures; Adopt the method for dry plasma to be removed by the dielectric layer 6 in window 8, and in dielectric layer 6, after removing the photoresist layer 7 on dielectric layer 6, obtain grid pin window 9 as shown in Figure 5.
As shown in figure 14, with dielectric layer 6 for mask, the barrier layer 3 under grid pin window 9 provides a groove 14.The formation of groove 14 can adopt the method for dry plasma or wet etching, preferred lithographic method is dry plasma, comprise reactive ion etching (RIE) and inductively coupled plasma etching, well-known for the method for dry plasma group III-nitride and principle, here repeat no more, specifically can see the document of the people such as Egawa (Egawa et al. Appl. Phys. Lett., vol. 76, pp. 121 – 123, 2000) or document (the Coffie et al. Applied Physics Letters Vol.83 of the people such as Coffie, p.4779, 2003).
Deposit WN metal level and W metal level obtain the barrier metal layer 10 shown in Figure 15 successively to form the sidewall of the grid pin window 9 after groove 14 in the surface of the bottom of groove 14 and sidewall and dielectric layer 6 and dielectric layer 6, the preferred deposit mode of barrier metal layer 10 and thickness with embodiment 1, WN metal level and the preferred thickness of W metal level with embodiment 1.
On barrier metal layer 10, apply photoresist layer 11, and form window 12 as shown in Figure 16 in photoresist layer 11 after the operation such as photoetching, development on aforesaid grid pin window 9 in other words conj.or perhaps groove 14, window 12 also can be referred to as grid cover window.With embodiment 1, must ensure in the design of grid cover window 12 and forming process grid pin window 9 completely cover by grid cover window 12, grid pin window 9 some or all of not the situation that covers by grid cover window 12 must avoid in the present invention.Avoid occurring grid pin window 9 some or all of not the problem that covers by grid cover window 12, first grid cover window 12 designs that upper will to ensure than grid pin window 9 large, the lithographic equipment that employing has a more high registration accuracy on this basis just can avoid occurring grid pin window 9 some or all of not the problem that covers by grid cover window 12.
As shown in figure 17, deposit grid cover metal level 13 in the barrier metal layer 10 in photoresist layer 11 and grid cover window 12, the effect of grid cover metal level, the metal system adopted and preferred deposit mode are with embodiment 1.Adopt stripping technology remove photoresist layer 11 and on grid cover metal level 13 after obtain as shown in figure 16 figure.
The grid cover metal level 13 in Figure 16 is utilized to be mask, the method barrier metal layer 10 removed except the barrier layer below grid cover metal level 13 of employing dry plasma obtains device as shown in figure 17, and the preferred etching mode of barrier metal layer 10 is with embodiment 1.
Claims (10)
1. an AlGaN/GaN HEMT manufacture method, it is characterized in that: on the barrier layer of the epitaxial material of AlGaN/GaN HEMT employing, deposited metal is as device source electrode and drain electrode, makes source electrode and drain electrode and semiconductor epitaxial material form ohmic contact by high temperature alloy; Dielectric layer deposited on the surface of source electrode, drain electrode and barrier layer; This dielectric layer applies photoresist layer and by defining a window in photoresist layer between device source electrode and drain electrode of the method for photoetching; Photoresist layer is utilized to remove the dielectric layer in window as mask and remove the grid pin window that photoresist layer obtains leading in dielectric layer barrier layer surface; In the sidewall and grid pin bottom of window of dielectric layer, grid pin window, deposit WN metal level and W metal level obtain barrier metal layer successively the surface of barrier layer; Barrier metal layer applies photoresist layer, by photoetching, is developed in the grid cover window carved and define complete covering gate pin window in glue-line; Evaporation grid cover metal level to the bottom of grid cover window, the surface of sidewall and photoresist layer; Peel off remove photoresist layer and on metal level, only leave the grid cover metal level in window; Grid cover metal level described in utilization removes the barrier metal layer except the barrier metal layer below the aforementioned grid cover metal level stayed as mask large area etching.
2. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, is characterized in that the material that dielectric layer is selected comprises SiN or SiO
2, thickness is 50nm-300nm.
3. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, its feature is the mode adopting dry plasma at the minimizing technology of the dielectric layer utilizing photoresist layer to remove in window as mask.
4. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, is characterized in that WN metal layer deposition method is the mode of magnetically controlled DC sputtering.
5. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, is characterized in that W metal layer deposition method is the mode of magnetically controlled DC sputtering.
6. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, is characterized in that the thickness of barrier metal layer is 50nm-300nm, and wherein the thickness of WN metal level is the thickness of 30nm-100nm, W metal level is 20nm-200nm.
7. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, it is characterized in that grid cover metal level adopts the mode deposit of evaporation to obtain, grid cover metal level includes but not limited to Ti/Pt/Au/Ti or Ti/Pt/Au/Pt/Ti or Ti/Pt/Au/Ni multiple layer metal.
8. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, it is characterized in that the etching minimizing technology of barrier metal layer is the mode adopting inductively coupled plasma etching, the gas that etching adopts is for using BCl
3.
9. a kind of AlGaN/GaN HEMT manufacture method according to claim 1, is characterized in that before barrier metal layer deposit, is take dielectric layer as mask, by etching barrier layer thus under grid pin window barrier layer surface formed a groove.
10. a kind of AlGaN/GaN HEMT manufacture method according to claim 9, is characterized in that groove is provided by the mode of dry plasma.
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| CN103618003B (en) * | 2013-11-18 | 2017-04-12 | 石以瑄 | High-electronic-mobility transistor with improved grid electrode |
| CN103745922A (en) * | 2013-12-09 | 2014-04-23 | 中国电子科技集团公司第五十五研究所 | Method for manufacturing GaN high electron mobility transistor composite medium insulated gate |
| CN103824854B (en) * | 2014-02-22 | 2016-09-28 | 石以瑄 | Switched circuit based on HEMT and microwave integrated circuit |
| CN103928324A (en) * | 2014-03-24 | 2014-07-16 | 中国电子科技集团公司第五十五研究所 | AlGaN/GaN HEMT manufacturing method |
| CN106226672B (en) * | 2016-08-01 | 2019-05-03 | 北京工业大学 | The thermal reliability evaluation method of GaN base HEMT device |
| CN109461655B (en) * | 2018-09-21 | 2022-03-11 | 中国电子科技集团公司第五十五研究所 | Method for manufacturing nitride high electron mobility transistor with multi-gate structure |
| EP3891814A1 (en) * | 2018-12-07 | 2021-10-13 | MACOM Technology Solutions Holdings, Inc. | Gate metal formation on gallium nitride or aluminum gallium nitride |
| IT201800011065A1 (en) * | 2018-12-13 | 2020-06-13 | St Microelectronics Srl | HEMT TRANSISTOR INCLUDING A PERFECTED PORT REGION AND RELATED MANUFACTURING PROCESS |
| CN112885899A (en) * | 2020-12-17 | 2021-06-01 | 南京中电芯谷高频器件产业技术研究院有限公司 | Self-aligned low-ohmic contact resistance GaN HEMT device and manufacturing method thereof |
| CN116676571B (en) * | 2023-04-26 | 2024-01-19 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
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