CN103218345A - Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method - Google Patents
Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method Download PDFInfo
- Publication number
- CN103218345A CN103218345A CN2013100849042A CN201310084904A CN103218345A CN 103218345 A CN103218345 A CN 103218345A CN 2013100849042 A CN2013100849042 A CN 2013100849042A CN 201310084904 A CN201310084904 A CN 201310084904A CN 103218345 A CN103218345 A CN 103218345A
- Authority
- CN
- China
- Prior art keywords
- data
- reconfigurable
- controller
- processing unit
- embedded microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to the technical field of reconfigurable circuits and systems, and discloses a dynamic reconfigurable system adaptable to a plurality of dataflow computation modes and an operating method. The dynamic reconfigurable system comprises an embedded microprocessor, a configuration controller, a multi-port memory controller and a plurality of reconfigurable processing units. A dataflow communication interface and a control interface, which can be separated, are adopted for each reconfigurable processing unit, so that the embedded microprocessor can be used for dynamically configuring the functions and interconnection structure of each reconfigurable processing unit to be adapted to the dataflow computation modes. Compared with the conventional system with a bus and a fast simplex link (FSL) structure, the system has the advantages that the resource reconfigurability of a field programmable gate array (FPGA) is fully utilized, and functions and structures, which are matched with the dataflow computation modes, are configured during operation to improve a communication bandwidth and the processing performance of dataflow driving application; and moreover, the system is high in structural adaptability and expansibility, and the invention is significant for a dataflow processing-oriented dynamic reconfigurable system.
Description
Technical field
The present invention relates to reconfigurable circuit and systems technology field, particularly can adapt to dynamic reconfigurable system and How It Works that the several data flowmeter is calculated pattern.
Background technology
With field programmable gate array (Field Programmable Gate Array, FPGA) for the dynamic reconfigurable system on basis from being suggested, just handle at data encryption/decryption, multimedia is handled and data flow driven application such as digital signal processing in demonstrate good calculated performance and reconfigurable dirigibility.Data Stream Processing module in the above-mentioned application adopts the combination of separation-polymerization (Fork-Join), streamline (Pipeline) and three kinds of elementary stream computation schemas of feedback loop (Feedback Loop) or above-mentioned data-flow computation pattern to realize usually.
In recent years, continuous expansion along with the FPGA scale, the dynamic reconfigurable internal system can have been held the reconfigurable processing unit of a plurality of coarsenesses, but and function dynamic-configuration, the executed in parallel of each reconfigurable processing unit, for utilize interconnected between the reconfigurable processing unit in single-chip, realizing that different data-flow computation patterns provides may.Yet, the most employing of existing dynamic reconfigurable system based on bus or quick single link (Fast Simplex Link, FSL) mutual contact mode, though but reconfigurable processing unit function dynamic-configuration, interface communication limited bandwidth, system architecture immobilize.Not not matching of not the matching of this just Interface design mode and data-flow computation feature, fixed system structure and data-flow computation pattern, can not adapt to the several data flowmeter and calculate the processing demands of pattern, the performance that makes data flow driven use can not effectively be promoted.
Summary of the invention
The object of the present invention is to provide a kind of dynamic reconfigurable system and How It Works that the several data flowmeter is calculated pattern that adapt to, this system supports the dynamic-configuration of data stream interconnect architecture, improve the handling property that data flow driven is used, and had good structure adaptability and extensibility.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of dynamic reconfigurable system that the several data flowmeter is calculated pattern that adapts to, comprise: by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller, above-mentioned reconfigurable processing unit comprises the data flow communication interface, control interface, interconnected controller of data stream and data-flow computation functional module, the interconnected controller of this data stream is connected with other reconfigurable processing unit with above-mentioned multiport memory controller by above-mentioned data flow communication interface, interconnected controller of this data stream and above-mentioned data-flow computation functional module are by input, output channel interconnects, and is connected with system bus by above-mentioned control interface;
Above-mentioned embedded microprocessor is used to read hardware task and the software task with data dependence relation, set up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to this hardware task and software task, and by above-mentioned control interface above-mentioned data-flow computation functional module is carried out functional configuration according to the above-mentioned Configuration Control Unit of this functional configuration information Control, with control the interconnected controller of above-mentioned data stream to the interconnected structural arrangements of carrying out of above-mentioned data flow communication interface, to adapt to predefined data-flow computation pattern according to this data stream interconnect architecture configuration information by above-mentioned control interface;
Above-mentioned multiport memory controller is used for Data transmission between above-mentioned embedded microprocessor and a plurality of reconfigurable processing unit.
Embodiments of the present invention also disclose a kind of How It Works that the several data flowmeter is calculated the dynamic reconfigurable system of pattern that adapts to, this system comprises by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller, above-mentioned reconfigurable processing unit comprises the data flow communication interface, control interface, interconnected controller of data stream and data-flow computation functional module, the interconnected controller of this data stream is connected with other reconfigurable processing unit with above-mentioned multiport memory controller by above-mentioned data flow communication interface, interconnected controller of this data stream and above-mentioned data-flow computation functional module are by input, output channel interconnects, and is connected with the said system bus by above-mentioned control interface; Above-mentioned How It Works may further comprise the steps:
Above-mentioned embedded microprocessor reads hardware task and the software task with data dependence relation;
Above-mentioned embedded microprocessor is set up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to this hardware task and software task; And
Above-mentioned embedded microprocessor carries out functional configuration by above-mentioned control interface to above-mentioned data-flow computation functional module according to the above-mentioned Configuration Control Unit of this functional configuration information Control, with control the interconnected controller of above-mentioned data stream to the interconnected structural arrangements of carrying out of above-mentioned data flow communication interface, to adapt to predefined data-flow computation pattern according to this data stream interconnect architecture configuration information by above-mentioned control interface;
Wherein, above-mentioned multiport memory controller Data transmission between above-mentioned embedded microprocessor and a plurality of reconfigurable processing unit.
Embodiment of the present invention compared with prior art, the key distinction and effect thereof are:
Dynamic reconfigurable of the present invention system comprises a plurality of reconfigurable processing units, embedded microprocessor, Configuration Control Unit and multiport memory controller, wherein each reconfigurable processing unit adopts data flow communication interface and the control interface that separates, thereby above-mentioned embedded microprocessor can carry out dynamic-configuration to the function and the interconnect architecture of each reconfigurable processing unit, calculates the needs of pattern to adapt to the several data flowmeter; Compare with the conventional dynamic reconfigurable system that adopts bus structure and FSL structure, the present invention makes full use of the resource restructural characteristic of FPGA, function and structural arrangements in when operation by being complementary with the data-flow computation pattern, improved the handling property that communication bandwidth and data flow driven are used, and have good structure adaptability and extensibility, significant for the dynamic reconfigurable system that data-oriented stream is handled.
Further, by employing overall situation data memory, but the bigger task of deal with data amount adapts to the data processing under the various situations, and dirigibility is bigger.
Further,, can read file more quickly, to quicken dynamic-configuration by the system controller access external memory.
Further, above-mentioned embedded microprocessor is used to monitor the ruuning situation of above-mentioned reconfigurable processing unit, and abnormal conditions is handled can guarantee further that each functional configuration and structural arrangements and predefined pattern of traffic adapt.
Description of drawings
Fig. 1 is a kind of structural representation that adapts to the dynamic reconfigurable system of several data flowmeter calculation pattern in the first embodiment of the invention;
Fig. 2 a kind ofly in the first embodiment of the invention adapts to the structural representation that the several data flowmeter is calculated reconfigurable processing unit in the dynamic reconfigurable system of pattern;
Fig. 3 is the synoptic diagram of a kind of data-flow computation pattern in the first embodiment of the invention;
Fig. 4 is the synoptic diagram of a kind of data-flow computation pattern in the first embodiment of the invention;
Fig. 5 is the synoptic diagram of a kind of data-flow computation pattern in the first embodiment of the invention;
Fig. 6 is a kind of structural representation that adapts to the dynamic reconfigurable system of several data flowmeter calculation pattern in the second embodiment of the invention;
Fig. 7 a kind ofly in the third embodiment of the invention adapts to the schematic flow sheet of How It Works that the several data flowmeter is calculated the dynamic reconfigurable system of pattern.
Embodiment
In the following description, in order to make the reader understand the application better many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on the many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the purpose, technical solutions and advantages of the present invention clearer, embodiments of the present invention are described in further detail below in conjunction with accompanying drawing.
First embodiment of the invention relates to a kind of dynamic reconfigurable system that the several data flowmeter is calculated pattern that adapts to.Fig. 1 is the structural representation of this dynamic reconfigurable system, and Fig. 2 is the structural representation of reconfigurable processing unit in this dynamic reconfigurable system.
As shown in Figure 1, this dynamic reconfigurable system comprises: by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller.
(Microprocessor Unit MPU) is developed by the CPU in the multi-purpose computer embedded microprocessor.Different with CPU in the multi-purpose computer is, in Embedded Application, microprocessor is assemblied on the custom-designed circuit board, only keep and functional hardware that Embedded Application is closely related, remove other redundancy feature part, so just realize the specific (special) requirements of Embedded Application with minimum power consumption and resource.In addition, in order to satisfy the specific (special) requirements of Embedded Application, the CPU of embedded microprocessor in the relative multi-purpose computers in aspect such as working temperature, anti-electromagnetic interference (EMI), reliability done various enhancings.In the present embodiment, above-mentioned embedded microprocessor is mainly used among the FPGA, is to embed FPGA inner and tightly coupled stone processor of fpga logic or soft-core processor.
Memory Controller Hub is inside computer system control internal memory and the important component part that makes swap data between internal memory and the CPU by Memory Controller Hub.In the present embodiment, above-mentioned multiport memory controller is used for Data transmission between embedded microprocessor and a plurality of reconfigurable processing unit.
Above-mentioned reconfigurable processing unit comprises data flow communication interface, control interface, the interconnected controller of data stream and data-flow computation functional module, as shown in Figure 2, the interconnected controller of this data stream is connected with other reconfigurable processing unit with above-mentioned multiport memory controller by above-mentioned data flow communication interface, interconnected controller of this data stream and above-mentioned data-flow computation functional module interconnect, and are connected with the said system bus by above-mentioned control interface by input, output channel.
Be appreciated that above-mentioned data flow communication interface is a high-speed data-flow communication interface configurable, point-to-point mode, it can be forward, reverse or two-way, is distributed in as required between each reconfigurable processing unit.
As optional embodiment, the interconnected controller of above-mentioned data stream is to realize by the configurable multi-way switch (MUX) that is dispersed in each reconfigurable processing unit inside, whether the gating of these multi-way switchs is controlled by the register of reconfigurable processing unit inside, and design feature is simple and practical.Yet, if reconfigurable processing unit number more (〉 3), above-mentioned " the interconnected controller of distributed data stream " may just relatively have been wasted on area.In other embodiments of the present invention, also can realize by an interconnected controller of concentrated data stream, the interconnected controller of this data stream is an IP(intellecture property of design separately) nuclear, directly it is controlled by embedded microprocessor, realize the interconnected of data flow path.Centralized method for designing is than distributing method for designing complexity, but under the many situations of unit number, has superiority on area.
Above-mentioned embedded microprocessor is used to read hardware task and the software task with data dependence relation, sets up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to this hardware task and software task.As this embedded microprocessor all hardware task that read and software task are traveled through, write down the data dependence relation between each hardware task and other software tasks or the hardware task, set up hardware task deployment queue (functional configuration information) and data interconnect architecture allocation list (data stream interconnect architecture configuration information).
Above-mentioned embedded microprocessor also is used for by above-mentioned control interface above-mentioned data-flow computation functional module being carried out functional configuration according to the above-mentioned Configuration Control Unit of this functional configuration information Control.In view of functional configuration is those skilled in the art's a common practise, do not repeat them here.
Above-mentioned embedded microprocessor is controlled the interconnected controller of above-mentioned data stream to the interconnected structural arrangements of carrying out of above-mentioned data flow communication interface, to adapt to predefined data-flow computation pattern according to this data stream interconnect architecture configuration information by above-mentioned control interface.
Be appreciated that, according to Xilinx dynamic reconfigurable system design flow process, data flow communication interface and control interface all are positioned at static region (Static Region), the data-flow computation functional module is positioned at restructural zone (Reconfigurable Region), and the dynamic-configuration of aforementioned calculation functional module does not influence the normal operation of other static part.
In case function and the configuration of data stream interconnect architecture finish, each reconfigurable processing unit can be according to predefined data-flow computation pattern, constantly receive data by above-mentioned multiport memory controller, inner data-flow computation functional module is constantly read in these data the local data input block, is carried out data processing, sends the result in the local data buffer zone again.
The several data flowmeter calculation pattern that above-mentioned dynamic reconfigurable system adapts to comprises separation-polymerization, streamline, feedback loop and combination thereof etc.Specifically be described below:
In a preferred example, use Xilinx Virtex-4XC4VFX60FPGA as hardware platform, comprising PowerPC405 stone microprocessor, HWICAP(Hardware Internal Configuration Access Port) Configuration Control Unit IP(Intellectual Property, intellecture property) nuclear, multiport memory controller IP kernel and three reconfigurable processing units.Be appreciated that in other embodiments of the present invention reconfigurable processing unit also can be two, four or more a plurality of.
Described microprocessor, Configuration Control Unit, multiport memory controller and three reconfigurable processing units respectively connection processing device local bus (Processor Local Bus, PLB).So in the present embodiment, described reconfigurable processing unit adopts control interface, the Xilinx LocalLink data flow communication interface based on the PLB bus.Between reconfigurable processing unit and the multiport memory controller, all undertaken interconnected between reconfigurable processing unit and the reconfigurable processing unit by LocalLink data flow communication interface, adaptive by data stream interconnect architecture and computation schema, support different types of walking abreast, further promote calculated performance and structure adaptability.
As shown in Figure 3, the foregoing description can be configured to separation-aggregation scheme, is used for realizing based on ECB(Electronic Code Book) the AES(Advanced Encryption Standard of mode) encryption.Three reconfigurable processing units are configured to AES encryption hardware task, and are undertaken interconnected by the LocalLink interface between each reconfigurable processing unit and the multiport memory controller.Operate in the AES encryption hardware task on the reconfigurable processing unit, the software task that operates on the PowerPC405 stone microprocessor communicates by the data flow path based on LocalLink, adopt single program multiple data (Single Program Multiple Data, SPMD) mode realizes data parallel, has promoted handling property.
Further, as shown in Figure 4, the foregoing description can be configured to pipeline mode, is used to realize 3DES(Triple Data Encryption Standard) encryption.Three reconfigurable processing units all are configured to the des encryption hardware task, and are undertaken interconnected by the LocalLink interface between the each processing unit.Operate in the des encryption hardware task on the reconfigurable processing unit, the software task that operates on the PowerPC405 stone microprocessor communicates by the data flow path based on the LocalLink interface, form grand flowing structure, adopt the flowing water parallel mode to improve handling property.
The foregoing description can also be configured to feedback loop pattern as shown in Figure 5, is used for realizing based on CBC(Cipher-Block Chaining) the AES encryption of mode.Any two in three reconfigurable processing units are configured to AES encryption hardware task, and input traffic passage and feedback data circulation road all adopt interconnected based on the LocalLink interface, utilize tasks in parallel to promote handling property, strengthened structure adaptability.
In addition, be appreciated that above-mentioned dynamic reconfigurable system is not limited to above-mentioned configuration, also can adopt other hardware platforms to be configured and adapt to various data-flow computation patterns and combination thereof.
Dynamic reconfigurable of the present invention system comprises a plurality of reconfigurable processing units, embedded microprocessor, Configuration Control Unit and multiport memory controller, wherein each reconfigurable processing unit adopts data flow communication interface and the control interface that separates, thereby above-mentioned embedded microprocessor can carry out dynamic-configuration to the function and the interconnect architecture of each reconfigurable processing unit, calculates the needs of pattern to adapt to the several data flowmeter.Compare with the conventional dynamic reconfigurable system that adopts bus structure and FSL structure, the present invention makes full use of the resource restructural characteristic of FPGA, function and structural arrangements in when operation by being complementary with the data-flow computation pattern, improved the handling property that communication bandwidth and data flow driven are used, and have good structure adaptability and extensibility, significant for the dynamic reconfigurable system that data-oriented stream is handled.
Second embodiment of the invention relates to a kind of dynamic reconfigurable system that the several data flowmeter is calculated pattern that adapts to.Fig. 6 is that this can adapt to the structural representation that the several data flowmeter is calculated the dynamic reconfigurable system of pattern.
Second embodiment improves on the basis of first embodiment.
As shown in Figure 6, above-mentioned dynamic reconfigurable system also comprises overall situation data memory, and above-mentioned software task is made up of instruction sequence, is stored in this overall situation data memory.Above-mentioned embedded microprocessor reads this software task and operation by above-mentioned multiport memory controller from this overall situation data memory.Be appreciated that, above-mentioned overall situation data memory can be Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory, " SDRAM "), static RAM (Static Random Access Memory, " SRAM ") or other storeies.
By employing overall situation data memory, but the bigger task of deal with data amount adapts to the data processing under the various situations, and dirigibility is bigger.
Further, above-mentioned dynamic reconfigurable system also comprises external memory storage, and above-mentioned hardware task is comprehensive in advance and is mapped to circuit function module in the above-mentioned reconfigurable processing unit that it is stored in the external memory storage with part bit stream file form.Be appreciated that the said external storer can be volatile memory, also can be nonvolatile memory.Preferably, adopt FLASH, ROM (read-only memory) nonvolatile memories such as (Read-Only Memory are called for short " ROM ") in the present embodiment, to guarantee safety of files.
In addition, above-mentioned dynamic reconfigurable system also comprises system high configuration series (Advanced Configuration Environment, be called for short " ACE ") controller, above-mentioned embedded microprocessor by the ACE of this system controller access external memory storage to read above-mentioned part bit stream file.
By the ACE of system controller access external memory storage, can read file more quickly, to quicken dynamic-configuration.
Be appreciated that also not using system ACE controller, these part bit stream files are stored in the above-mentioned overall situation data memory with above-mentioned software task.In addition, be appreciated that also not using system ACE controller, external memory storage and overall situation data memory, all tasks be stored in the internal memory of above-mentioned embedded microprocessor, also can realize technical scheme of the present invention.
In addition, above-mentioned embedded microprocessor also is used for by above-mentioned control interface above-mentioned reconfigurable processing unit being monitored when above-mentioned reconfigurable processing unit deal with data, and abnormal conditions are handled.
Above-mentioned embedded microprocessor is used to monitor the ruuning situation of reconfigurable processing unit, and abnormal conditions is handled can guarantee further that each functional configuration and structural arrangements and predefined pattern of traffic adapt.
Need to prove, each unit of mentioning in each equipment embodiment of the present invention all is a logical block, physically, a logical block can be a physical location, it also can be the part of a physical location, can also realize that the physics realization mode of these logical blocks itself is not most important with the combination of a plurality of physical locations, the combination of the function that these logical blocks realized is only the key that solves technical matters proposed by the invention.In addition, for outstanding innovation part of the present invention, above-mentioned each the equipment embodiment of the present invention will not introduced not too close unit with solving technical matters relation proposed by the invention, and this does not show that there is not other unit in the said equipment embodiment.
Third embodiment of the invention relates to a kind of How It Works that the several data flowmeter is calculated the dynamic reconfigurable system of pattern that adapts to.Fig. 7 is the schematic flow sheet of the How It Works of this dynamic reconfigurable system.
This dynamic reconfigurable system comprises by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller, above-mentioned reconfigurable processing unit comprises the data flow communication interface, control interface, interconnected controller of data stream and data-flow computation functional module, the interconnected controller of this data stream is connected with other reconfigurable processing unit with above-mentioned multiport memory controller by above-mentioned data flow communication interface, the interconnected controller of this data stream and this data-flow computation functional module are by input, output channel interconnects, and is connected with the said system bus by above-mentioned control interface.
Be appreciated that above-mentioned data flow communication interface is a high-speed data-flow communication interface configurable, point-to-point mode, it can be forward, reverse or two-way, is distributed in as required between each reconfigurable processing unit.
As optional embodiment, the interconnected controller of above-mentioned data stream is realized by register and at least one multi-way switch.In addition, be appreciated that in other embodiments of the present invention that the interconnected controller of above-mentioned data stream also can be realized by IP kernel or other devices of independent design.
As shown in Figure 7, above-mentioned How It Works may further comprise the steps:
Above-mentioned embedded microprocessor reads hardware task and the software task with data dependence relation.
Above-mentioned embedded microprocessor is set up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to this hardware task and software task; And
Above-mentioned embedded microprocessor carries out functional configuration by above-mentioned control interface to above-mentioned data-flow computation functional module according to the above-mentioned Configuration Control Unit of this functional configuration information Control, with control the interconnected controller of above-mentioned data stream to the interconnected structural arrangements of carrying out of above-mentioned data flow communication interface, to adapt to predefined data-flow computation pattern according to this data stream interconnect architecture configuration information by above-mentioned control interface.
If configuration is finished, then start each reconfigurable processing unit and carry out Data Stream Processing, otherwise proceed configuration.
Wherein, above-mentioned multiport memory controller Data transmission between above-mentioned embedded microprocessor and a plurality of reconfigurable processing unit.
The several data flowmeter calculation pattern that this dynamic reconfigurable system adapts to comprises separation-polymerization, streamline, feedback loop and combination thereof etc.
Dynamic reconfigurable of the present invention system comprises a plurality of reconfigurable processing units, embedded microprocessor, Configuration Control Unit and multiport memory controller, wherein each reconfigurable processing unit adopts data flow communication interface and the control interface that separates, thereby above-mentioned embedded microprocessor can carry out dynamic-configuration to the function and the interconnect architecture of each reconfigurable processing unit, to realize adapting to the dynamic reconfigurable system that the several data flowmeter is calculated pattern.Compare with the conventional dynamic reconfigurable system that adopts bus structure and FSL structure, the present invention makes full use of the resource restructural characteristic of FPGA, function and structural arrangements in when operation by being complementary with the data-flow computation pattern, improved the handling property that data flow driven is used, and have good structure adaptability and extensibility, significant for the dynamic reconfigurable system that data-oriented stream is handled.
Present embodiment is and the corresponding method embodiment of first embodiment, present embodiment can with the enforcement of working in coordination of first embodiment.The correlation technique details of mentioning in first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in first embodiment.
Four embodiment of the invention relates to a kind of How It Works that the several data flowmeter is calculated the dynamic reconfigurable system of pattern that adapts to.
The 4th embodiment improves on the basis of the 3rd embodiment.
As shown in Figure 6, above-mentioned dynamic reconfigurable system also comprises the ACE of system controller and external memory storage, above-mentioned hardware task is comprehensive in advance and is mapped to circuit function module in the reconfigurable processing unit that it is stored in the external memory storage with part bit stream file form.
In addition, above-mentioned dynamic reconfigurable system also comprises overall situation data memory, and above-mentioned software task is stored in this overall situation data memory.
In the step that reads this hardware task and software task, above-mentioned embedded microprocessor reading above-mentioned part bit stream file, and reads above-mentioned software task by above-mentioned multiport memory controller by said system ACE controller access said external storer from above-mentioned overall situation data memory.
Be appreciated that the said external storer can be volatile memory, also can be nonvolatile memory.Preferably, adopt nonvolatile memories such as FLASH, ROM in the present embodiment, to guarantee safety of files.
In addition, be appreciated that above-mentioned overall situation data memory can be SDRAM, SRAM or other storeies.
By employing overall situation data memory, but the bigger task of deal with data amount adapts to the data processing under the various situations, and dirigibility is bigger; By the ACE of system controller access external memory storage, can read file more quickly, to quicken dynamic-configuration.
Be appreciated that also not using system ACE controller, these part bit stream files are stored in the above-mentioned overall situation data memory with above-mentioned software task.In addition, be appreciated that also not using system ACE controller, external memory storage and overall situation data memory, all tasks be stored in the internal memory of above-mentioned embedded microprocessor, also can realize technical scheme of the present invention.
In addition, above-mentioned embedded microprocessor is used to monitor the ruuning situation of above-mentioned reconfigurable processing unit, and abnormal conditions are handled, and can guarantee further that each functional configuration and structural arrangements and predefined pattern of traffic adapt.Specifically:
Above-mentioned How It Works is further comprising the steps of:
When above-mentioned reconfigurable processing unit deal with data, above-mentioned embedded microprocessor is monitored above-mentioned reconfigurable processing unit by above-mentioned control interface, and abnormal conditions are handled.
In a preferred example, realizing adapting to the several data flowmeter based on the feedback loop pattern of Fig. 5, to calculate the concrete grammar of dynamic reconfigurable system of pattern as follows:
The Data Stream Processing task is divided into a plurality of hardware task and software tasks that have data dependence relation, and handles according to predefined data-flow computation pattern; Software task is made up of instruction sequence, operates on the PowerPC405 stone microprocessor (embedded microprocessor); Hardware task is comprehensive in advance and is mapped to circuit function module in the reconfigurable processing unit, is stored in Compact Flash(external memory storage with part bit stream file form) in; SDRAM storer (overall situation data memory) is as the global data buffer zone, is used to realize the storage to source data and result data.
Above-mentioned microprocessor travels through all tasks, data dependence relation between record hardware task and other software task or the hardware task, set up hardware task deployment queue (functional configuration information) and interconnect architecture allocation list (data stream interconnect architecture configuration information): this microprocessor reads the part bit stream file of hardware task correspondence on the one hand successively from nonvolatile memory (external memory storage), the hardware task of putting into appointment reads buffer zone in advance, sets up hardware task deployment queue (functional configuration information); On the other hand, in interconnect architecture allocation list (data stream interconnect architecture configuration information), the LocalLink interface interconnecting relation that is complementary with predefined data-flow computation pattern has been described;
This microprocessor is according to hardware task deployment queue (functional configuration information) and interconnect architecture allocation list (data stream interconnect architecture configuration information), reconfigurable processing unit is carried out function and interconnect architecture configuration: this microprocessor utilizes the HWICAP Configuration Control Unit that reconfigurable processing unit is carried out functional configuration earlier, again by the dynamic-configuration of each reconfigurable processing unit internal control interface realization to LocalLink data stream interconnect architecture;
In case function and interconnect architecture configuration finish, each reconfigurable processing unit can constantly receive data from the LocalLink input interface according to predefined data-flow computation pattern, handles, and sends result data to the LocalLink output interface; When system moved, above-mentioned microprocessor also can carry out status monitoring, abnormality processing to hardware task by reconfigurable processing unit internal control interface.
Be appreciated that above each improvement combination back forms better embodiment of the present invention, but each improvement can be used respectively also.In addition, above-mentioned dynamic reconfigurable system is not limited to above-mentioned configuration, also can adopt other hardware platforms to be configured to adapt to various data-flow computation patterns and combination thereof.
Present embodiment is and the corresponding method embodiment of second embodiment, present embodiment can with the enforcement of working in coordination of second embodiment.The correlation technique details of mentioning in second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in second embodiment.
Be appreciated that the present invention can be used for any integrated circuit that possesses the dynamic restructuring ability, as the restructural computing platform of restructural heterogeneous multi-nucleus processor, domain-oriented.
Each method embodiment of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention be with software, hardware, or the firmware mode realize, instruction code can be stored in the storer of computer-accessible of any kind (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium or the like).Equally, storer can for example be programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc is called for short " DVD ") or the like.
Though pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. one kind can adapt to the dynamic reconfigurable system that the several data flowmeter is calculated pattern, it is characterized in that, comprise: by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller, described reconfigurable processing unit comprises the data flow communication interface, control interface, interconnected controller of data stream and data-flow computation functional module, the interconnected controller of described data stream is connected with other reconfigurable processing unit with described multiport memory controller by described data flow communication interface, interconnected controller of described data stream and described data-flow computation functional module are by input, output channel interconnects, and is connected with described system bus by described control interface;
Described embedded microprocessor is used to read hardware task and the software task with data dependence relation, set up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to described hardware task and software task, and by described control interface described data-flow computation functional module is carried out functional configuration according to the described Configuration Control Unit of described functional configuration information Control, with control the interconnected controller of described data stream to the interconnected structural arrangements of carrying out of described data flow communication interface, to adapt to predefined data-flow computation pattern according to described data stream interconnect architecture configuration information by described control interface;
Described multiport memory controller is used for Data transmission between described embedded microprocessor and a plurality of reconfigurable processing unit.
2. dynamic reconfigurable according to claim 1 system is characterized in that, the interconnected controller of described data stream is realized by register and at least one multi-way switch.
3. dynamic reconfigurable according to claim 1 system is characterized in that described system also comprises overall situation data memory, and described software task is stored in the described overall situation data memory;
Described embedded microprocessor reads described software task by described multiport memory controller from described overall situation data memory.
4. dynamic reconfigurable according to claim 1 system, it is characterized in that, described system also comprises external memory storage, described hardware task is comprehensive in advance and is mapped to circuit function module in the described reconfigurable processing unit that it is stored in the described external memory storage with part bit stream file form;
Described system also comprises system high configuration series A CE controller, described embedded microprocessor by the described external memory storage of the ACE of this system controller access to read described part bit stream file.
5. according to each described dynamic reconfigurable system in the claim 1 to 4, it is characterized in that, described embedded microprocessor also is used for by described control interface described reconfigurable processing unit being monitored when described reconfigurable processing unit deal with data, and abnormal conditions are handled.
6. according to each described dynamic reconfigurable system in the claim 1 to 4, it is characterized in that the several data flowmeter calculation pattern that described system adapts to comprises separation-polymerization, streamline, feedback loop and combination thereof;
Described data flow communication interface is a high-speed data-flow communication interface configurable, point-to-point mode.
7. one kind can adapt to the How It Works that the several data flowmeter is calculated the dynamic reconfigurable system of pattern, it is characterized in that, described system comprises by the interconnective a plurality of reconfigurable processing units of system bus, embedded microprocessor, Configuration Control Unit and multiport memory controller, described reconfigurable processing unit comprises the data flow communication interface, control interface, interconnected controller of data stream and data-flow computation functional module, the interconnected controller of described data stream is connected with other reconfigurable processing unit with described multiport memory controller by described data flow communication interface, interconnected controller of described data stream and described data-flow computation functional module are by input, output channel interconnects, and is connected with described system bus by described control interface; Described How It Works may further comprise the steps:
Described embedded microprocessor reads hardware task and the software task with data dependence relation;
Described embedded microprocessor is set up functional configuration information and the data stream interconnect architecture configuration information that adapts with predefined data-flow computation pattern according to described hardware task and software task; And
Described embedded microprocessor carries out functional configuration by described control interface to described data-flow computation functional module according to the described Configuration Control Unit of described functional configuration information Control, with control the interconnected controller of described data stream to the interconnected structural arrangements of carrying out of described data flow communication interface, to adapt to predefined data-flow computation pattern according to described data stream interconnect architecture configuration information by described control interface;
Wherein, described multiport memory controller Data transmission between described embedded microprocessor and a plurality of reconfigurable processing unit.
8. the How It Works of dynamic reconfigurable according to claim 7 system, it is characterized in that, described system also comprises the ACE of system controller and external memory storage, described hardware task is comprehensive in advance and is mapped to circuit function module in the described reconfigurable processing unit that it is stored in the described external memory storage with part bit stream file form;
Described system also comprises overall situation data memory, and described software task is stored in the described overall situation data memory;
In the step that reads described hardware task and software task, described embedded microprocessor reading described part bit stream file, and reads described software task by described multiport memory controller by the described external memory storage of described system ACE controller access from described overall situation data memory.
9. the How It Works of dynamic reconfigurable according to claim 7 system is characterized in that, and is further comprising the steps of:
When described reconfigurable processing unit deal with data, described embedded microprocessor is monitored described reconfigurable processing unit by described control interface, and abnormal conditions are handled;
In addition, in the step of functional configuration and structural arrangements, the interconnected controller of described data stream is realized by register and at least one multi-way switch.
10. according to the How It Works of each described dynamic reconfigurable system in the claim 7 to 9, it is characterized in that the several data flowmeter calculation pattern that described system adapts to comprises separation-polymerization, streamline, feedback loop and combination thereof;
Described data flow communication interface is a high-speed data-flow communication interface configurable, point-to-point mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100849042A CN103218345A (en) | 2013-03-15 | 2013-03-15 | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100849042A CN103218345A (en) | 2013-03-15 | 2013-03-15 | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103218345A true CN103218345A (en) | 2013-07-24 |
Family
ID=48816150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100849042A Pending CN103218345A (en) | 2013-03-15 | 2013-03-15 | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103218345A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914429A (en) * | 2014-04-18 | 2014-07-09 | 东南大学 | Multi-mode data transmission interconnection device for coarseness dynamic reconfigurable array |
| CN104951385A (en) * | 2015-07-09 | 2015-09-30 | 首都师范大学 | Channel health state recording device of dynamic reconfigurable bus monitoring system |
| CN108027806A (en) * | 2015-09-22 | 2018-05-11 | 高通股份有限公司 | Configuration coarseness configurable arrays (CGRA) perform for data flow instruction block in block-based data flow instruction collection framework (ISA) |
| CN111433758A (en) * | 2018-11-21 | 2020-07-17 | 吴国盛 | Programmable operation and control chip, design method and device thereof |
| WO2021089009A1 (en) * | 2019-11-08 | 2021-05-14 | 中国科学院深圳先进技术研究院 | Data stream reconstruction method and reconstructable data stream processor |
| CN113468099A (en) * | 2021-05-31 | 2021-10-01 | 深圳致星科技有限公司 | Reconfigurable computing device, processor and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279729A (en) * | 2011-06-14 | 2011-12-14 | 清华大学 | Method, buffer and processor for dynamic reconfigurable array to schedule configuration information |
| CN102411555A (en) * | 2011-08-17 | 2012-04-11 | 清华大学 | Method for telescopically and dynamically configuring configuration information of reconfigurable array |
| CN102650980A (en) * | 2012-04-09 | 2012-08-29 | 清华大学 | Method and device for generating configuration information with multi-core dynamic reconfigurable processor |
| US20120303932A1 (en) * | 2011-05-27 | 2012-11-29 | New York University | Runtime reconfigurable dataflow processor |
| CN203204615U (en) * | 2013-03-15 | 2013-09-18 | 上海安路信息科技有限公司 | Dynamic reconfigurable system adaptable to various data flow calculation modes |
-
2013
- 2013-03-15 CN CN2013100849042A patent/CN103218345A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120303932A1 (en) * | 2011-05-27 | 2012-11-29 | New York University | Runtime reconfigurable dataflow processor |
| CN102279729A (en) * | 2011-06-14 | 2011-12-14 | 清华大学 | Method, buffer and processor for dynamic reconfigurable array to schedule configuration information |
| CN102411555A (en) * | 2011-08-17 | 2012-04-11 | 清华大学 | Method for telescopically and dynamically configuring configuration information of reconfigurable array |
| CN102650980A (en) * | 2012-04-09 | 2012-08-29 | 清华大学 | Method and device for generating configuration information with multi-core dynamic reconfigurable processor |
| CN203204615U (en) * | 2013-03-15 | 2013-09-18 | 上海安路信息科技有限公司 | Dynamic reconfigurable system adaptable to various data flow calculation modes |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914429A (en) * | 2014-04-18 | 2014-07-09 | 东南大学 | Multi-mode data transmission interconnection device for coarseness dynamic reconfigurable array |
| CN103914429B (en) * | 2014-04-18 | 2016-11-23 | 东南大学 | Multimode data for coarseness dynamic reconfigurable array transmits connectors |
| CN104951385A (en) * | 2015-07-09 | 2015-09-30 | 首都师范大学 | Channel health state recording device of dynamic reconfigurable bus monitoring system |
| CN104951385B (en) * | 2015-07-09 | 2017-10-13 | 首都师范大学 | Passage health status tape deck in dynamic reconfigurable bus monitoring system |
| CN108027806A (en) * | 2015-09-22 | 2018-05-11 | 高通股份有限公司 | Configuration coarseness configurable arrays (CGRA) perform for data flow instruction block in block-based data flow instruction collection framework (ISA) |
| CN111433758A (en) * | 2018-11-21 | 2020-07-17 | 吴国盛 | Programmable operation and control chip, design method and device thereof |
| WO2021089009A1 (en) * | 2019-11-08 | 2021-05-14 | 中国科学院深圳先进技术研究院 | Data stream reconstruction method and reconstructable data stream processor |
| CN113468099A (en) * | 2021-05-31 | 2021-10-01 | 深圳致星科技有限公司 | Reconfigurable computing device, processor and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103218345A (en) | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method | |
| US10515046B2 (en) | Processors, methods, and systems with a configurable spatial accelerator | |
| US10445250B2 (en) | Apparatus, methods, and systems with a configurable spatial accelerator | |
| US10445234B2 (en) | Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features | |
| CN203204615U (en) | Dynamic reconfigurable system adaptable to various data flow calculation modes | |
| Pellauer et al. | Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration | |
| US7945764B2 (en) | Processing unit incorporating multirate execution unit | |
| US20190101952A1 (en) | Processors and methods for configurable clock gating in a spatial array | |
| US20190004878A1 (en) | Processors, methods, and systems for a configurable spatial accelerator with security, power reduction, and performace features | |
| CN102073481B (en) | Multi-kernel DSP reconfigurable special integrated circuit system | |
| JP5364543B2 (en) | A multiprocessor computer architecture incorporating multiple memory algorithm processors in a memory subsystem. | |
| US9317294B2 (en) | Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core | |
| CN108121672A (en) | A kind of storage array control method and device based on Nand Flash memorizer multichannel | |
| US10564929B2 (en) | Communication between dataflow processing units and memories | |
| WO2014081457A1 (en) | Processing system with interspersed processors dma-fifo | |
| US10659396B2 (en) | Joining data within a reconfigurable fabric | |
| US20180212894A1 (en) | Fork transfer of data between multiple agents within a reconfigurable fabric | |
| US20190171416A1 (en) | Power control for a dataflow processor | |
| Tabkhi et al. | Function-level processor (FLP): A high performance, minimal bandwidth, low power architecture for market-oriented MPSoCs | |
| CN104360979A (en) | GPU-based (Graphic Processing Unit) computer system | |
| Park et al. | MoDe-X: Microarchitecture of a layout-aware modular decoupled crossbar for on-chip interconnects | |
| US11163605B1 (en) | Heterogeneous execution pipeline across different processor architectures and FPGA fabric | |
| Chen et al. | Customizable computing | |
| IT202000013390A1 (en) | An IT platform to prevent side channel attacks | |
| Rettkowski et al. | Application-specific processing using high-level synthesis for networks-on-chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130724 |