CN103218207B - Microprocessor instruction processing method based on mono-/bis-firing order collection and system - Google Patents
Microprocessor instruction processing method based on mono-/bis-firing order collection and system Download PDFInfo
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- CN103218207B CN103218207B CN201210016166.3A CN201210016166A CN103218207B CN 103218207 B CN103218207 B CN 103218207B CN 201210016166 A CN201210016166 A CN 201210016166A CN 103218207 B CN103218207 B CN 103218207B
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Abstract
The present invention relates to microprocessor instruction processing method based on mono-/bis-firing order collection and system, including: according to the address of instruction, reading an instruction from memorizer, comprising the described instruction of instruction in wherein said instruction is single firing order or the flag of double firing order;Instruction to being read decodes, it is thus achieved that include the decoding result of described flag, operation code, operand, according to described flag, determines that described instruction is for single firing order or double firing order;If it is determined that this instruction is single firing order, in first-class waterline, then complete the operation of this list firing order, if it is determined that this instruction is double firing orders, in first-class waterline, then complete the first operation in this pair of firing order, the second operation of this pair of firing order, first-class waterline and the parallel running in an identical manner of second waterline is completed in second waterline;And the operation result of described first-class waterline and the operation result of described second waterline are write back to depositor.
Description
Technical field
The present invention relates to command processing method and the system of microprocessor, particularly to based on mixing
Single-shot penetrates/the microprocessor instruction processing method of bis-firing order collection and system.
Background technology
In the basic framework of microprocessor, the instruction performed within an instruction cycle processed
Journey mainly includes instruction addressing, instruction reading, Instruction decoding, read operation number, computing, result
The step such as write back.Traditional microprocessor based on single firing order is in the mistake processing an instruction
Journey is only performed once computing.Although actually a lot of computings can with parallel processing, but due to
Arithmetic unit ALU is only performed once the restriction of computing within a cycle and cannot realize, therefore
ALU becomes the bottleneck of conventional microprocessor efficiency so that this traditional penetrate finger based on single-shot
The work efficiency of the microprocessor of order is relatively low.
In order to improve the work efficiency of microprocessor, have been proposed for double firing order technology at present.
The concept of double transmittings is, each instruction can read four operands, carries out two differences (also
Be probably identical) computing, current high-end processors the most all supports double firing order, very
Refer to multi-emitting so that microprocessor work efficiency is greatly improved.
The instruction processing mode of existing microprocessor based on double firing orders mainly has following several
Kind:
First kind of way is that every instruction the most only comprises a computing, during instruction processes,
Instruction process system reads two instructions simultaneously, by hardware according to the dependence between two instructions
Relation calculates whether these two instructions can be carried out simultaneously temporarily, if the result calculated is permissible
Carry out simultaneously, then two instructions are respectively written into two streamlines.Owing to two instructions are at two
It is likely to occur precedence during streamline performs respectively to overturn, therefore at two flowing water
After line is respectively completed computing, two operation results to be resequenced, then carry out result
Write back.This processing mode have a problem in that implement more complicated, instruction rely on close
The links such as the calculating of system and result rearrangement, all can introduce the hugest logical complexity
And hardware spending.
The second way is to realize single-shot in an instruction to penetrate or double transmitting, say, that
Instruction set comprises single firing order and double firing order two kinds instruction, is become by extra state
Amount distinguishes both instructions, say, that repaiied by program in the application of microprocessor
Changing this state variable to the instruction indicating microprocessor current is single firing order or double transmitting
Instruction.In the prior art, ARM series microprocessor is the typical case worked based on this mode
Microprocessor, the repertoire of its pair of firing order also support microcontroller is in order to save
Save the instruction space.This mode makes the hardware configuration of microprocessor relatively easy, but software is compiled
Journey is sufficiently complex.Due to single-shot penetrate/bis-firing order between not switching at runtime, but need logical
Cross the state of amendment microprocessor thus process single-shot by the two different logics of set and penetrate and double transmitting
Instruction, it is therefore desirable to explicit tell that next instruction of microprocessor is single firing order or double
Firing order, this makes the programming complexity of microprocessor be greatly increased.And because single-shot is penetrated
Instruction and double firing order are all complete or collected works, realize the repertoire of microprocessor the most respectively, cause
Article two, streamline will realize all instructing, say, that all of operation will repeat twice.
Further, owing to instruction number is huge, cause instruction encoding (operation code) field the longest, compression
The space of other fields such as address field, immediate field, which limits microprocessor and exists
Otherwise performance.Such as typical ARM microprocessor is bigger sky owing to instruction field takies
Between, cause register field to reduce so that the depositor degree of depth can only support 16.
As can be seen here, it is difficult to get both between performance and cost/power consumption, is conventional microprocessor
Crucial limitation.Especially in the certain applications such as graphics process or multi-media processing, need
A kind of high-performance, low cost, low-power consumption, the finger of novel microprocessor of low application complexity
Make processing system and method.
Summary of the invention
The present invention proposes and a kind of penetrates the/microprocessor instruction of bis-firing order collection based on mixing single-shot
Processing system, solves problems of the prior art, by asymmetric single-shot penetrate/bis-send out
Penetrate instruction set arrange reduce instruction field space, by static state switching simplify single-shot penetrate/bis-send out
Penetrate instruction handover mechanism, greatly reduce hardware cost and programming complexity.
Utilize the microprocessor that the microprocessor instruction treating method and apparatus of the present invention designs, tool
Having low cost, low-power consumption, the advantage of high treatment efficiency, under 40nm technique, with less than 0.03mm2
Chip area, operating frequency and the instruction of about 1.5Mips/Mhz of 1Ghz can be achieved over
Perform speed.
According to an aspect of the invention, it is proposed that a kind of microprocessor instruction processing method, including:
Instruction read step, according to the address of instruction, reads an instruction from memorizer, its
Described in comprise the described instruction of instruction in instruction be single firing order or the mark of double firing order
Position;
Instruction decoding step, the instruction to being read decodes, it is thus achieved that include described flag,
Operation code, the decoding result of operand, according to described flag, determine that described instruction is single-shot
Penetrate instruction or double firing order;
Calculation step: if it is determined that this instruction is single firing order, then complete in first-class waterline
Become the operation of this list firing order, if it is determined that this instruction is double firing orders, then first-class
Waterline completes the first operation in this pair of firing order, second waterline completes this pair and sends out
Penetrate the second operation of instruction, first-class waterline and the parallel running in an identical manner of second waterline;
Write back step: by operation result and the fortune of described second waterline of described first-class waterline
Calculate result and write back to depositor.
Preferably, the single-shot being made up of described single firing order penetrates instruction set and by described double transmittings
Double firing order collection that instruction is constituted realize the partial function of microprocessor respectively.
Preferably, the normal instruction frequently used is set to both is penetrated instruction set by single-shot and realizes,
Realized by double firing order collection again;The non-unconventional instruction frequently used is set to only by single-shot
Penetrate instruction set to realize, or only realized by double firing order collection.
Preferably, described first-class waterline and second waterline can include reading the first operation respectively
Number the first order, read second operand the second level and to first operand and second behaviour
Count and carry out the third level of computing.
Preferably, if the address of the operation result of first-class waterline and the computing of second waterline
The address of result clashes, then two operation results are carried out inclusive-OR operation.
According to another aspect of the invention, it is proposed that a kind of microprocessor instruction processing system, bag
Include:
Depositor, storage includes instruction, operand, the data of operation result;
Instruction reading device, according to the address of instruction, reads an instruction from memorizer, its
Described in comprise the described instruction of instruction in instruction be single firing order or the mark of double firing order
Position;
Instruction decoding device, the instruction to being read decodes, it is thus achieved that include described flag,
Operation code, the decoding result of operand, according to described flag, determine that described instruction is single-shot
Penetrate instruction or double firing order;
Instruction pipeline arrangements, including first-class production line apparatus and second production line apparatus, wherein
If it is determined that this instruction is single firing order, then in this first-class production line apparatus, complete this single-shot
Penetrate the operation of instruction, if it is determined that this instruction is double firing orders, then complete in first-class waterline
Become first in this pair of firing order to operate, in second waterline, complete this pair of firing order
Second operation, first-class production line apparatus and second production line apparatus are the most parallel
Run;
Write back device, by operation result and the fortune of described second waterline of described first-class waterline
Calculate result and write back to depositor.
Preferably, described instruction reading device is posted by program counter, address register and instruction
Storage realizes.
Preferably, described first-class production line apparatus includes the first order being made up of the first buffer,
The second level being made up of the second buffer and the third level being made up of first arithmetic device;Described second
Streamline includes the first order being made up of the 3rd buffer, the second level being made up of the 4th buffer
With the third level being made up of second arithmetic device.
Preferably, if it is determined that described instruction is single firing order, then at described first buffer
The middle first operand reading instruction, reads the second operation of instruction in described second buffer
Number, carries out computing to first operand and second operand in described first arithmetic device;If
Determine that described instruction for double firing orders, then reads the first of instruction in described first buffer
Operation first operand, read in described second buffer instruction first operation second
Operand, to the first first operand operated and the second of the first operation in first arithmetic device
Operand carries out computing;The first behaviour of the second operation of instruction is read in described 3rd buffer
Count, described 4th buffer reads the second operand of the second operation of instruction, the
The first operand of the second operation and the second operand of the second operation are transported by two arithmetical units
Calculate.
Preferably, write back device described in and include being connected to the first result buffer of first arithmetic device
Be connected to the second result buffer of second arithmetic device, store the computing of two arithmetical units respectively
As a result, and by bus the appropriate address in depositor is write back to.
Accompanying drawing explanation
Fig. 1 is the flow chart of the microprocessor instruction processing method of the present invention;
Fig. 2 a and Fig. 2 b is a single firing order according to an embodiment of the invention and
The order code topology example of the double firing order of bar;
Fig. 3 is the structure chart of a kind of microprocessor instruction processing system of the present invention;
Fig. 4 is the structure chart of a preferred embodiment of the instruction process system of the present invention;
Fig. 5 is the structure chart of flow-line equipment according to a preferred embodiment of the present invention.
Detailed description of the invention
The present invention proposes and a kind of penetrates the/new microprocessor of bis-firing order collection based on mixing single-shot
Command processing method and system.
Fig. 1 is the flow chart of the microprocessor instruction processing method of the present invention, specifically includes that
Instruction read step, according to the address of instruction, reads an instruction from memorizer, its
Described in comprise the described instruction of instruction in instruction be single firing order or the mark of double firing order
Position;
Instruction decoding step, the instruction to being read decodes, it is thus achieved that include described flag,
Operation code, the decoding result of operand, according to described flag, determine that described instruction is single-shot
Penetrate instruction or double firing order;
Calculation step: if it is determined that this instruction is single firing order, then complete in first-class waterline
Become the operation of this list firing order, if it is determined that this instruction is double firing orders, then first-class
Waterline completes the first operation in this pair of firing order, second waterline completes this pair and sends out
Penetrating the second operation of instruction, first-class waterline and second waterline are the most parallel
Run;
Write back step: by operation result and the fortune of described second waterline of described first-class waterline
Calculate result and write back to depositor.
Being different from traditional mixing single-shot and penetrate/bis-firing order mode set, the instruction of the present invention processes
Single-shot involved in method penetrates instruction set and double firing order collection takes asymmetrical design,
It is to say, single-shot penetrates instruction set and double firing order collection are not respectively completed the institute of microprocessor
There is function, but realize the partial function of microprocessor respectively, single-shot penetrate instruction set and double
Penetrate the function summation of instruction set to complete all functions of microprocessor.Excellent of the present invention
Select in embodiment, the instruction of microprocessor can be divided according to such principle:
-the normal instruction that frequently uses, such as commonly use arithmetic operator instruction, logic instruction,
Read/write memory instruction, bit manipulation instruction etc., both penetrated instruction set support by single-shot, again by double transmittings
Instruction set is supported;
-use frequency low but the unconventional instruction of necessity, such as jump instruction etc., only penetrate at single-shot
Instruction set is supported, or only concentrates support at double firing orders.
Such distribution principle so that the quantity of double firing orders is relatively fewer, is therefore supporting
On the premise of double transmittings, reduce the length of opcode field so that according to the instruction of the present invention
Processing system, while improve treatment effeciency, remains to support the biggest register array, carries
High combination property.
In the present invention, carry out the single-shot of bordering compounding by calculating the most as prior art to penetrate
Instruction forms double firing order, is not to be come by extra state variable in programming process
Differentiation both instructs, on the contrary, in the command processing method of the present invention so that every finger
Order is all independent event, arranges a flag (the most secondary high position) in every instruction, according to
Independent interpretation this flag of result identification of every instruction, thus determine its be single firing order also
It is double firing orders.
Fig. 2 a and Fig. 2 b is a single firing order according to an embodiment of the invention and
The order code topology example of the double firing order of bar, in fig. 2 a, gives the finger of single firing order
Make code structure, its from left to right by flag, operation code, operand 1, operand 2, other
The part such as Optional Field is constituted, and wherein flag indicates this instruction for single firing order, figure for " 0 "
In 2b, give the order code structure of double firing order, its flag, first behaviour from left to right
Make code, operand 1, operand the 2, second operation code, operand 3, operand 4, other
The part such as Optional Field is constituted, and wherein flag indicates this instruction for double firing orders for " 1 ".Should
Double firing orders can complete the first comprised operation and the second operation simultaneously.
From the point of view of the angle of hardware, do not introduce due to the present invention be dynamically assigning to two or more
Mechanism in streamline, but distribute single firing order and double transmitting statically according to decoding result
Instruction, The method avoids extra hardware burden so that hardware cost is greatly reduced, from
From the point of view of the angle of upper layer application, the method for the present invention makes the program space completely the same, and upper strata is compiled
Journey is not required to define when especially into single firing order or double firing order, single firing order and double
Switching between firing order is fully transparent for upper layer software (applications), and this is just substantially reduced
Programming complexity in application.
Below as a example by jump instruction, illustrate that the asymmetric mechanism of the present invention is reducing hardware cost
The contribution of aspect.When performing jump routine, need to decide whether to jump according to mark FLAG
Turn, such as when realizing the program of " then redirecting as a > b ", according to conventional process mode, two
The streamline that bar is symmetrical all introduces FLAG, produces on two streamlines to distinguish simultaneously
FLAG, is necessary for log history condition to determine the transfer of follow-up state, and logic is sufficiently complex,
This situation is the rarest in the running of microprocessor, but rare in order to solve this
Problem, it is necessary to introduce the biggest hardware spending.By contrast, a present invention stream the most wherein
FLAG is updated by waterline, it is no longer necessary to carry out the district of FLAG on two streamlines
Point, this makes the pipeline design independent simple, reduces hardware cost.
If after Instruction decoding, the flag obtained indicates this instruction to be single firing order,
In first-class waterline, then complete the operation of this list firing order, such as at typical microprocessor
In architecture, first-class waterline can include the first order: reads first operand;The second level:
Read second operand;And the third level: computing, obtain operation result.
If after Instruction decoding, the flag obtained indicates this instruction to be double firing orders,
In first-class waterline, then complete the first operation in this pair of firing order, in second waterline
Complete this pair of firing order second operation, first-class waterline with second waterline with identical
Mode parallel running.
Two arithmetical units in most situations of microprocessor work, in two streamlines
The address that writes back of the result that ALU produces is different, therefore can be simply by two computing knots
Fruit writes back in respective register address simultaneously.In a preferred embodiment of the invention, examine
Considering in pole in particular cases, the address of two operation results is if it occur that conflict, then two
Result carries out the computing of "or" OR, by this simple logical process so that in two streamlines
Operation all part come into force.
Fig. 3 is the structure chart of a kind of microprocessor instruction processing system of the present invention, specifically includes that
Depositor 301, storage includes instruction, operand, the data of operation result;
Instruction reading device 302, according to the address of instruction, reads an instruction from memorizer,
Comprising the described instruction of instruction in wherein said instruction is single firing order or the mark of double firing order
Position;
Instruction decoding device 303, the instruction to being read decodes, it is thus achieved that include described mark
Position, operation code, the decoding result of operand, according to described flag, determine that described instruction is
Single firing order or double firing order;
Instruction pipeline arrangements 304, fills including first-class production line apparatus 3041 and second waterline
Put 3042, wherein if it is determined that this instruction is single firing order, then at this first-class production line apparatus
In complete the operation of this list firing order, if it is determined that this instruction is double firing orders, then the
One streamline completes the first operation in this pair of firing order, in second waterline, completes this
Second operation of double firing orders, first-class production line apparatus and second production line apparatus are with complete phase
Same mode parallel running;
Write back device 305: by the operation result of described first-class waterline and described second waterline
Operation result writes back to depositor.
Fig. 4 is the structure chart of a preferred embodiment of the instruction process system of the present invention, and this is excellent
Selecting embodiment based on typical microprocessor architecture design, wherein instruction reading device can be by programmed counting
Device PC, address register ITCM and command register INS realize, program counter PC
For depositing and indicate the address of instruction to be performed, address register is for preserving the ground in PC
Location, command register, for temporarily depositing the instruction taken out according to address, waits to be decoded.
Instruction decoding device can be realized by command decoder IND, and order code is transformed into execution by it
The signal of telecommunication required for this instruction, in the present invention, comprising this instruction of instruction in decoding result is
Single firing order or the flag of double firing order.
Fig. 5 is the structure chart of flow-line equipment according to a preferred embodiment of the present invention, the
One flow-line equipment V-PIPE and second production line apparatus U-PIPE can include by buffer respectively
First order S1 that VR1/UR1 is constituted, is used for reading first operand;By buffer VR2/UR2
The second level S2 constituted, is used for reading second operand, and by ALU1/AUL2 arithmetical unit
The third level S3 constituted, has been used for computing.Can design as required streamline progression and not
It is confined to the mode that the present embodiment provides.In the present invention, if it is determined that this instruction is that single-shot is penetrated
Instruction, then complete the operation of this list firing order in this first-class production line apparatus, i.e. read and refer to
The first operand of order is to the first buffer VR1, and the second operand reading instruction is temporary to second
Storage VR2, and in first arithmetic device, the first and second operands are calculated, transported
Calculate result.If it is determined that this instruction is double firing orders, then in first-class waterline, complete this pair
The first operation in firing order, i.e. the first operand of reading the first operation is to buffer VR1,
Read the second operand of the first operation to buffer VR2, and in first arithmetic device ALU1
The two operand is carried out computing;The second of this pair of firing order is completed in second waterline
Operation, the first operand i.e. reading the second operation operates to buffer UR1, reading second
Second operand is to buffer UR2, and to the two operand in second arithmetic device ALU2
Carry out computing;First-class production line apparatus and second production line apparatus are the most parallel
Run.
Write back device to include being connected to two of first arithmetic device and second arithmetic device and keep in
Device, it is stored the result of two arithmetical units respectively, and is write back to the phase in depositor by bus
Answer address.
The principle of being illustrative for property of above-described embodiment explanation present invention and effect thereof, not for
Limit the present invention.Any those skilled in the art all can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore protection scope of the present invention, should be such as the present invention
Listed by claims.
Claims (8)
1. a microprocessor instruction processing method, including:
Instruction read step, according to the address of instruction, reads an instruction from memorizer, its
Described in comprise the described instruction of instruction in instruction be single firing order or the mark of double firing order
Position;
Instruction decoding step, the instruction to being read decodes, it is thus achieved that include described flag,
Operation code, the decoding result of operand, according to described flag, determine that described instruction is single-shot
Penetrate instruction or double firing order;
Calculation step: when determining this instruction for single firing order, complete in first-class waterline
The operation of this list firing order, when determining this instruction for double firing order, at first-class waterline
In complete in this pair of firing order first operation, second waterline completes this pair of transmitting and refers to
Second operation of order, first-class waterline and the parallel running in an identical manner of second waterline;
Write back step: by operation result and the fortune of described second waterline of described first-class waterline
Calculate result and write back to depositor,
Wherein said first-class waterline and second waterline can include reading first operand respectively
The first order, read second operand the second level and to first operand and second operand
Carry out the third level of computing;
When the address of operation result of first-class waterline and the address of the operation result of second waterline
When clashing, two operation results are carried out inclusive-OR operation.
Microprocessor instruction processing method the most according to claim 1, wherein by described list
The single-shot that firing order is constituted penetrates instruction set and the double firing orders being made up of described pair of firing order
Collection realizes the partial function of microprocessor respectively.
Microprocessor instruction processing method the most according to claim 2, wherein,
The normal instruction frequently used is set to both penetrated instruction set by single-shot realize, again by double
Penetrate instruction set to realize;
The non-unconventional instruction frequently used is set to only penetrated instruction set by single-shot realize, or only
Realized by double firing order collection.
4. a microprocessor instruction processing system, including:
Depositor, storage includes instruction, operand, the data of operation result;
Instruction reading device, according to the address of instruction, reads an instruction from memorizer, its
Described in comprise the described instruction of instruction in instruction be single firing order or the mark of double firing order
Position;
Instruction decoding device, the instruction to being read decodes, it is thus achieved that include described flag,
Operation code, the decoding result of operand, according to described flag, determine that described instruction is single-shot
Penetrate instruction or double firing order;
Instruction pipeline arrangements, including first-class production line apparatus and second production line apparatus, wherein
When determining this instruction for single firing order, in this first-class production line apparatus, complete this single-shot penetrate
The operation of instruction, when determining this instruction for double firing order, complete in first-class production line apparatus
Become first in this pair of firing order to operate, second production line apparatus completes this pair of transmitting and refers to
Second operation of order, first-class production line apparatus and second production line apparatus are in an identical manner
Parallel running;
Write back device, by operation result and the described second waterline of described first-class production line apparatus
The operation result of device writes back to depositor.
Microprocessor instruction processing system the most according to claim 4, described instruction is read
Device is realized by program counter, address register and command register.
Microprocessor instruction processing system the most according to claim 4, described first flowing water
Line apparatus includes the first order being made up of the first buffer, the second level being made up of the second buffer
With the third level being made up of first arithmetic device;Described second production line apparatus includes being kept in by the 3rd
The first order that device is constituted, the second level that is made up of the 4th buffer and being made up of second arithmetic device
The third level.
Microprocessor instruction processing system the most according to claim 6, wherein,
When determining described instruction for single firing order, described first buffer reads instruction
First operand, described second buffer reads the second operand of instruction, described
First arithmetic device carries out computing to first operand and second operand;
When determining described instruction for double firing order, described first buffer reads instruction
First operation first operand, read in described second buffer instruction first operation
Second operand, in first arithmetic device to first operation first operand and first operation
Second operand carry out computing;The second operation of instruction is read in described 3rd buffer
First operand, reads the second operand of the second operation of instruction in described 4th buffer,
The first operand of the second operation and the second operand of the second operation are entered by second arithmetic device
Row operation.
Microprocessor instruction processing system the most according to claim 4, described in write back device
Including being connected to the first result buffer of first arithmetic device and being connected to the second of second arithmetic device
Result buffer, stores the operation result of two arithmetical units respectively, and writes back to post by bus
Appropriate address in storage.
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CN105955711A (en) * | 2016-04-25 | 2016-09-21 | 浪潮电子信息产业股份有限公司 | Buffering method supporting non-blocking miss processing |
CN111240747B (en) * | 2020-01-13 | 2022-05-06 | Oppo广东移动通信有限公司 | Instruction generation method and device, test framework and electronic equipment |
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