CN103218207A - Microprocessor instruction processing method and system based on single/dual transmitting instruction set - Google Patents

Microprocessor instruction processing method and system based on single/dual transmitting instruction set Download PDF

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CN103218207A
CN103218207A CN2012100161663A CN201210016166A CN103218207A CN 103218207 A CN103218207 A CN 103218207A CN 2012100161663 A CN2012100161663 A CN 2012100161663A CN 201210016166 A CN201210016166 A CN 201210016166A CN 103218207 A CN103218207 A CN 103218207A
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instruction
pipeline
operation
operand
single
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CN2012100161663A
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CN103218207B (en
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沙力
兰军强
朱磊
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上海算芯微电子有限公司
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Abstract

The invention relates to a microprocessor instruction processing method and system based on a single/dual transmitting instruction set. The processing method comprises the following steps of reading an instruction from a memory according to the address of the instruction, and the instruction comprises a marking position indicating the instruction to be a single transmitting instruction or a dual transmitting instruction; carrying out decoding on the read instruction, obtaining a decoding result of the marking position, an operating code and an operating number, and according to the marking position, determining the instruction to be the single transmitting instruction or the dual transmitting instruction; if the instruction is determined to be the single transmitting instruction, finishing the operation of the single transmitting instruction in a first assembly line, if the instruction is determined to be the dual transmitting instruction, finishing the first operation in the dual transmitting instruction in the first assembly line, finishing the second operation of the dual transmitting instruction in a second assembly line, and the first assembly line and the second assembly line operate in parallel in the same manner; and writing the operation results of the first assembly line and the second assembly line back to a register.

Description

基于单/双发射指令集的微处理器指令处理方法及系统 Microprocessor-based processing method and system commands single / dual emission instruction set

技术领域 FIELD

[0001] 本发明涉及微处理器的指令处理方法及系统,特别涉及基于混合单发射/双发射指令集的微处理器指令处理方法及系统。 [0001] The present invention relates to a method and system for processing instructions of a microprocessor, and more particularly to a method and system for processing microprocessor instructions based mixed single emitter / dual emission instruction set.

背景技术 Background technique

[0002] 在微处理器的基本架构中,在一个指令周期内执行的指令处理过程主要包括指令寻址、指令读取、指令译码、读操作数、运算、结果写回等步骤。 [0002] In the basic architecture of the microprocessor, the instruction executed in one instruction cycle process includes instruction addressing, instruction fetch, instruction decode, operand read, operation, the result is written back to other steps. 传统的基于单发射指令的微处理器在处理一条指令的过程中仅执行一次运算。 A conventional microprocessor-based single emission instruction operation performed only once in the processing of an instruction process. 虽然实际上很多运算可以并行处理,但是由于运算单元ALU在一个周期内仅执行一次运算的限制而无法实现,因此ALU成为了传统微处理器效率的瓶颈,使得这种传统的基于单发射指令的微处理器的工作效率较低。 Although in practice many operations can be processed in parallel, but since the arithmetic unit ALU performs a limiting operation only in one cycle can not be achieved, thus become the bottleneck of the conventional microprocessor ALU efficiency, so that such conventional emission command based on single lower operating efficiency of the microprocessor.

[0003] 为了提高微处理器的工作效率,目前已经提出了双发射指令技术。 [0003] In order to improve the efficiency of a microprocessor, it has been proposed dual emission INSTRUCTIONS. 双发射的概念是,每一条指令能够读取四个操作数,进行两个不同(也可能是相同)的运算,目前的高端处理器一般都支持双发射指令,甚至多发射指,使得微处理器工作效率大大提高。 Dual emission concept that every four instruction operands can be read, for two different (possibly the same) operation, the current high-end processors typically support instruction dual emission, and even multiple transmitting means, such that the microprocessor working efficiency is greatly improved.

[0004] 现有的基于双发射指令的微处理器的指令处理方式主要有以下几种: [0004] The conventional approach based on an instruction of the microprocessor instruction dual emission are the following:

[0005] 第一种方式是每条指令仍只包含一个运算,在指令处理的过程中,指令处理系统同时读取两条指令,通过硬件根据两条指令之间的依赖关系临时计算这两条指令是否可以同时进行,如果计算的结果为可以同时进行,则将两条指令分别写入两条流水线。 [0005] The first way is still each contain only one operation instruction, during instruction processing, the instruction processing system reads two instructions simultaneously, the two interim calculated by hardware of a dependency between two instructions whether the instruction can be simultaneously performed, if the result of calculations that can be performed simultaneously, then the two instructions are written into two lines. 由于两条指令在两个流水线中分别执行的过程中可能出现先后次序颠倒,因此在两条流水线分别完成运算之后,要对两个运算结果进行重新排序,再进行结果的写回。 Since the process two instructions in the pipeline are two possible execution of the order is reversed, so after two pipelines were completed operation, two operations to reorder the results, and then write the results back. 这种处理方式的问题在于实现起来比较复杂,在指令依赖关系的计算以及结果重新排序等环节,都会引入相当庞大的逻辑复杂度和硬件开销。 The problem with this approach is that the process is more complicated to implement, reorder instruction dependencies calculated and the results and other links, that introduce very large logical complexity and hardware costs.

[0006] 第二种方式是在一条指令中实现单发射或双发射,也就是说,在指令集中包含单发射指令和双发射指令两种指令,通过额外的状态变量来区分这两种指令,也就是说,在微处理器的应用中通过程序来修改这个状态变量来指示微处理器当前的指令是单发射指令还是双发射指令。 [0006] A second way is for single or double emission in an emission instruction, i.e., an instruction set comprising a single emitter dual emission instruction and instructions into two instruction, both instructions are distinguished by an additional state variable, that is, the application of the microprocessor to modify the state variable indicates that the current program by instructions of a microprocessor instruction is a single emission or dual emission instruction. 在现有技术中,ARM系列微处理器是基于这种方式工作的典型微处理器,其双发射指令也支持微处理器的全部功能,目的是为了节省指令空间。 In the prior art, the ARM microprocessor family is based on a typical microprocessor works in this way, dual emission which instructions may also support all features of a microprocessor, instruction purpose is to save space. 这种方式使得微处理器的硬件结构相对简单,但软件编程十分复杂。 Such a way that the microprocessor hardware structure is relatively simple, but very complex software programming. 由于单发射/双发射指令之间并非动态切换,而是需要通过修改微处理器的状态从而用两套不同的逻辑来处理单发射和双发射指令,因此需要显式的告诉微处理器下一条指令是单发射指令还是双发射指令,这使得微处理器的编程复杂度大大增加。 Since the single emitter / dual emission is not dynamic switching between instruction, but need to use two different sets of such logic to handle a single emission and dual emission command by modifying the state of the microprocessor, it is necessary to explicitly tell the microprocessor a instruction is a single instruction or a dual emission emission instruction, which makes the microprocessor programming complexity is greatly increased. 而且因为单发射指令和双发射指令都是全集,即分别实现微处理器的全部功能,导致两条流水线都要实现全部指令,也就是说所有的操作都要重复两遍。 And because the single and dual emission instruction Complete instructions are emitted, i.e. to achieve full functionality of the microprocessor, resulting in two lines have to implement all of the instructions, that is to say all the operations must be repeated twice. 并且,由于指令数量巨大,导致指令编码(操作码)字段很长,压缩了地址字段、立即数字段等其他字段的空间,这就限制了微处理器在其他方面的性能。 Further, due to the large number of instructions, instructions that cause code (opcode) field is very long, the compressed address field, a field space of other immediate fields, etc., which limits the performance of the microprocessor in other areas. 例如典型的ARM微处理器由于指令字段占用较大空间,导致寄存器字段减小,使得寄存器深度只能支持16位。 Since the ARM microprocessor such as a typical instruction field occupies a large space, resulting in reduced register fields, such that only 16-bit registers deep.

[0007] 由此可见,在性能和成本/功耗之间难以兼得,是传统微处理器的关键局限性。 [0007] Thus, it is difficult to have both between performance and cost / power consumption, a key limitation of the conventional microprocessor. 尤其是在图形处理或多媒体处理等特定应用场合,需要一种高性能、低成本、低功耗、低应用复杂度的新型的微处理器的指令处理系统和方法。 Especially in a graphics processing or multimedia processing for a particular application, a need for a high performance, low cost, low power, low application instruction complexity of the new microprocessor processing systems and methods.

发明内容 SUMMARY

[0008] 本发明提出了一种基于混合单发射/双发射指令集的微处理器指令处理系统,解决了现有技术中存在的问题,通过非对称式单发射/双发射指令集设置减小了指令字段空间,通过静态切换简化了单发射/双发射指令切换机制,大大降低了硬件成本以及编程复杂度。 [0008] The present invention proposes a microprocessor instruction processing system based on a hybrid single emitter / dual emission instruction set, to solve the problems in the prior art, the emission by the asymmetric single / dual emission reduced instruction set provided the instruction field space, the static switch simplifies single transmit / dual emission instruction to switch mechanisms, greatly reduces the cost of hardware and programming complexity.

[0009] 利用本发明的微处理器指令处理方法和装置设计的微处理器,具有低成本,低功耗,高处理效率的优点,在40nm工艺下,以小于0.03mm2的芯片面积,可实现超过IGhz的工作频率以及约1.5Mips/Mhz的指令执行速度。 [0009] The present invention utilizing a microprocessor instruction processing method and apparatus of a microprocessor design has the advantage of low cost, low power, high efficiency, and in the 40nm process, the chip area of ​​less than 0.03mm2 can be achieved IGhz than the operating frequency and about 1.5Mips / Mhz instruction execution speed.

[0010] 根据本发明的一方面,提出了一种微处理器指令处理方法,包括: [0010] According to an aspect of the present invention, there is proposed a method for processing microprocessor instructions, comprising:

[0011] 指令读取步骤,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; [0011] Step reading instruction, the address of the instruction, an instruction is read from memory, wherein said command comprises indicating said instruction is a single instruction, or transmitting identification bits dual emission instruction;

[0012] 指令译码步骤,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; [0012] The instruction decoding step for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction, or transmitting dual emission instruction;

[0013] 运算步骤:如果确定该指令为单发射指令,则在第一流水线中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线和第二流水线以相同的方式并行运行; [0013] calculating step: if it is determined that the instruction is a single emission instruction, the operation is completed in a single first emission instruction pipeline, the instruction determines if the instruction is a double emission is completed in the first instruction pipeline in the dual emission a second operation of the first operation, completing the dual emission in the second instruction pipeline, the first pipeline and the second pipeline running in parallel in the same manner;

[0014] 写回步骤:将所述第一流水线的运算结果和所述第二流水线的运算结果写回到寄存器。 [0014] Write the steps of: calculating the result of the first pipeline and the second pipeline operation result is written back to the register.

[0015] 优选地,由所述单发射指令构成的单发射指令集和由所述双发射指令构成的双发射指令集分别实现微处理器的部分功能。 [0015] Preferably, a single emitter emitting said single instruction set consisting of a set of instructions and dual emission constituted by the dual emission instruction respectively, to achieve part of the functions of the microprocessor.

[0016] 优选地,将频繁使用的常规指令设置为既由单发射指令集实现,又由双发射指令集实现;将非频繁使用的非常规指令设置为仅由单发射指令集实现,或仅由双发射指令集实现。 [0016] Preferably, the conventional instruction frequently used to either set implemented by a single emission instruction, and set to achieve a dual emission instruction; non-frequently used unconventional instruction to set to achieve only a single emission instruction, or only a dual emission instruction set implemented.

[0017] 优选地,所述第一流水线和第二流水线可分别包括读取第一操作数的第一级、读取第二操作数的第二级、以及对第一操作数和第二操作数进行运算的第三级。 [0017] Preferably, the first pipeline and the second pipeline stage may include a first reading the first operand, reads the second stage of the second operand, and the first operand and a second operation It calculates the number of the third stage.

[0018] 优选地,如果第一流水线的运算结果的地址和第二流水线的运算结果的地址发生冲突,则将两个运算结果进行“或”运算。 [0018] Preferably, if the address for calculation result of the address calculation result of the first pipeline and the second pipeline conflict, the operation result will be two "or" operation.

[0019] 根据本发明的另一方面,提出了一种微处理器指令处理系统,包括: [0019] According to another aspect of the present invention there is provided a microprocessor instruction processing system, comprising:

[0020] 寄存器,存储包括指令,操作数,运算结果的数据; [0020] register, a memory comprising instructions, operands, the operation result data;

[0021] 指令读取装置,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; [0021] The instruction reading means, the address of the instruction, an instruction is read from memory, wherein said command comprises indicating said instruction is a single instruction, or transmitting identification bits dual emission instruction;

[0022] 指令译码装置,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; [0022] The instruction decoding means for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction, or transmitting dual emission instruction;

[0023] 指令流水线装置,包括第一流水线装置和第二流水线装置,其中如果确定该指令为单发射指令,则在该第一流水线装置中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线装置和第二流水线装置以完全相同的方式并行运行; [0023] The instruction pipeline means, means comprising a first pipeline and the second pipeline means, wherein if it is determined that the instruction is a single emission instruction, the operation is completed in a single instruction transmitting the first pipeline means, if it is determined that the instruction is a double instructions are transmitted, the completion of the first operation of the dual emission instruction in the first pipeline, to complete the second dual emission instruction pipeline in a second operation, the first pipeline means and the second pipeline means in parallel exactly the same manner run;

[0024] 写回装置,将所述第一流水线的运算结果和所述第二流水线的运算结果写回到寄存器。 [0024] The write back means, the calculation result of the first pipeline and the second pipeline operation result is written back to the register.

[0025] 优选地,所述指令读取装置由程序计数器、地址寄存器和指令寄存器来实现。 [0025] Preferably, the instruction means is realized by reading the program counter, an instruction register and address register.

[0026] 优选地,所述第一流水线装置包括由第一暂存器构成的第一级,由第二暂存器构成的第二级和由第一运算器构成的第三级;所述第二流水线包括由第三暂存器构成的第一级,由第四暂存器构成的第二级和由第二运算器构成的第三级。 [0026] Preferably, the first means comprises a first pipeline stage, second stage and third stage constituted by a first arithmetic unit constituted by the first register constituted by a second register; the the second pipeline stage includes a first, second and third stages composed of the second arithmetic unit constituted by the third register constituted by the fourth register.

[0027] 优选地,如果确定所述指令为单发射指令,则在所述第一暂存器中读取指令的第一操作数,在所述第二暂存器中读取指令的第二操作数,在所述第一运算器中对第一操作数和第二操作数进行运算;如果确定所述指令为双发射指令,则在所述第一暂存器中读取指令的第一操作的第一操作数,在所述第二暂存器中读取指令的第一操作的第二操作数,在第一运算器中对第一操作的第一操作数和第一操作的第二操作数进行运算;在所述第三暂存器中读取指令的第二操作的第一操作数,在所述第四暂存器中读取指令的第二操作的第二操作数,在第二运算器中对第二操作的第一操作数和第二操作的第二操作数进行运笪 [0027] Preferably, if determined that the instruction is a single emission instruction, the first register is read in the first operand in the instruction, the second instruction to read the second register transmitting a first instruction if said instruction is determined to be double, then the read command in the first register; operands, first operand and second operand of the operation in first operator in operating a first operand, the second operand of the first instruction in the operation of the second read register, the first operand of the first operation, the first operation in a first computing unit computes two operands; first operand of the second instruction in the operation of reading the third register, the second operand of the second instruction in the read operation in the fourth register, Da for transport of the second operand of the first operand and the second operation in the second operation in second operator

[0028] 优选地,所述写回装置包括连接于第一运算器的第一结果暂存器和连接于第二运算器的第二结果暂存器,分别存储两个运算器的运算结果,并通过总线写回到寄存器中的相应地址。 [0028] Preferably, said write-back means includes a first register and a result register connected to the second result of the second arithmetic unit connected to the first arithmetic unit, store two arithmetic operation result, by bus and written back to the corresponding address register.

附图说明 BRIEF DESCRIPTION

[0029] 图1是本发明的微处理器指令处理方法的流程图; [0029] FIG. 1 is a flowchart of the microprocessor instruction processing method of the present invention;

[0030] 图2a和图2b是根据本发明的一个实施例的一条单发射指令和一条双发射指令的指令码结构示例; [0030] Figures 2a and 2b is a single emission instruction exemplary embodiment of the structure of the instruction code and a dual-emission instruction according to a embodiment of the present invention;

[0031] 图3是本发明的一种微处理器指令处理系统的结构图; [0031] FIG. 3 is a configuration diagram of a microprocessor according to the present invention, a processing system instructions;

[0032] 图4是本发明的指令处理系统的一个优选实施例的结构图; [0032] FIG. 4 is a block diagram of a preferred embodiment of the instruction processing system of the present invention;

[0033] 图5是根据本发明的一个优选实施例的流水线装置的结构图。 [0033] FIG 5 is a configuration diagram of a pipeline apparatus according to one preferred embodiment of the present invention.

具体实施方式 Detailed ways

[0034] 本发明提出了一种基于混合单发射/双发射指令集的新的微处理器指令处理方法和系统。 [0034] The present invention proposes a new microprocessor instructions based mixed single emitter / dual emission instruction set of the processing method and system.

[0035] 图1是本发明的微处理器指令处理方法的流程图,主要包括: [0035] FIG. 1 is a flow chart of the microprocessor instruction processing method of the present invention, including:

[0036] 指令读取步骤,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; [0036] The instruction reading step, the address of the instruction, an instruction is read from memory, wherein said command comprises indicating said instruction is a single instruction, or transmitting identification bits dual emission instruction;

[0037] 指令译码步骤,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; [0037] The instruction decoding step for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction, or transmitting dual emission instruction;

[0038] 运算步骤:如果确定该指令为单发射指令,则在第一流水线中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线和第二流水线以完全相同的方式并行运行;[0039] 写回步骤:将所述第一流水线的运算结果和所述第二流水线的运算结果写回到寄存器。 [0038] calculating step: if it is determined that the instruction is a single emission instruction, the operation is completed in a single first emission instruction pipeline, the instruction determines if the instruction is a double emission is completed in the first instruction pipeline in the dual emission a second operation of the first operation, completing the dual emission in the second instruction pipeline, the first pipeline and the second pipeline in parallel run in exactly the same way; [0039] write the steps of: the first pipeline operation results of the second pipeline operation result is written back to the register.

[0040] 不同于传统的混合单发射/双发射指令集方式,本发明的指令处理方法中所涉及的单发射指令集和双发射指令集采取了非对称的设计,也就是说,单发射指令集和双发射指令集并非分别完成微处理器的所有功能,而是分别实现微处理器的部分功能,由单发射指令集和双发射指令集的功能总和来完成微处理器的所有功能。 [0040] Unlike conventional mixing single emitter / dual emission instruction set mode, transmit a single instruction set in the processing method of the present invention relates dual emission instruction set and taken asymmetrical design, i.e., a single transmit instruction dual emission current and complete set of instructions are not all the features of a microprocessor, but part of the functions are implemented in the microprocessor, the sum of the function of a single emitter dual emission instruction set and instruction set of the microprocessor to perform all functions. 在本发明的一个优选实施例中,可将微处理器的指令按照这样的原则进行划分: In a preferred embodiment of the present invention, instructions of a microprocessor may be divided according to the principle:

[0041]-频繁使用的常规指令,例如常用算数运算指令、逻辑运算指令、读写内存指令、位操作指令等,既由单发射指令集支持,又由双发射指令集支持; [0041] - regular instruction frequently used, such as conventional arithmetic instructions, logical operation instructions, memory read and write instructions, bit manipulation instructions and the like, both supported by a single set of instructions are transmitted, and transmitting the instruction set supported by the two;

[0042]-使用频率低但必要的非常规指令,例如跳转指令等,仅在单发射指令集中支持,或仅在双发射指令集中支持。 [0042] - low frequency but necessary to use unconventional instructions, such as jump instructions and the like, only a single emission instruction set support, or concentrated only supports dual emission instruction.

[0043] 这样的分配原则,使得双发射指令的数量相对较少,因此在支持双发射的前提下,减小了操作码字段的长度,使得根据本发明的指令处理系统在提高了处理效率的同时,仍能支持很大的寄存器阵列,提高了综合性能。 [0043] Such allocation principle so that the dual emission of a relatively small number of instructions, and therefore support the premise dual emission, reducing the length of the operating code field, so that the processing according to the instruction in the system of the invention improves the processing efficiency At the same time, still supports a large register array to improve the overall performance.

[0044] 在本发明中,并非如现有技术那样通过计算来组合相邻的单发射指令来形成双发射指令,也不是在编程过程中通过额外的状态变量来区分这两种指令,相反地,在本发明的指令处理方法中,使得每条指令都是独立事件,在每条指令中设置一个标识位(例如次高位),根据每条指令的独立译码结果识别该标识位,从而决定其为单发射指令还是双发射指令。 [0044] In the present invention, not as in the prior art by calculating a combination of adjacent single emitting instruction to form a double emission instruction, nor is it to distinguish these two instructions by an additional state variable in the programming process, conversely in the command processing method of the present invention, such instructions are independent of each event, set a flag (e.g., high times) in each instruction, identifying the flag according to the independent decoding result of each instruction to determine an emission instruction is a single or double emission instruction.

[0045] 图2a和图2b是根据本发明的一个实施例的一条单发射指令和一条双发射指令的指令码结构示例,在图2a中,给出了单发射指令的指令码结构,其从左至右由标识位、操作码、操作数1、操作数2、其他可选字段等部分构成,其中标识位为“O”指示该指令为单发射指令,图2b中,给出了双发射指令的指令码结构,其从左至右标识位、第一操作码、操作数 [0045] Figures 2a and 2b is a single emission instruction exemplary embodiment of the structure of the instruction code and a dual-emission instruction according to a embodiment of the present invention, in Figure 2a, shows the structure of a single script command transmitting, from which composed left to right flag, opcodes, operand 1, operand 2, other optional fields like portion, wherein the flag is "O" indicates that the instruction is a single instruction transmitter, Figure 2b illustrates a dual emission script command structure that flag from left to right, the first operation code, operand

1、操作数2、第二操作码、操作数3,操作数4,其他可选字段等部分构成,其中标识位为“I”指示该指令为双发射指令。 1, operand 2, a second operation code, operand 3, 4 operand, other optional fields like parts, in which the identification bit is "I" indicates that the instruction is a double emission instruction. 该双发射指令可同时完成所包含的第一操作和第二操作。 The dual emission instruction may be completed first and second operations simultaneously contained.

[0046] 从硬件的角度来讲,由于本发明没有引入动态分配到两个或多个流水线中的机制,而是根据译码结果静态地分配单发射指令和双发射指令,这种方法避免了额外的硬件负担,使得硬件成本大大下降,从上层应用的角度来讲,本发明的方法使得程序空间完全一致,上层编程中不需特别定义何时为单发射指令或双发射指令,单发射指令和双发射指令之间的切换对于上层软件来说是完全透明的,这就大大降低了应用中的编程复杂度。 [0046] From a hardware point of view, since the present invention is incorporated is not dynamically allocated to two or more pipeline mechanism, but a single statically allocated transmit instructions and dual emission instruction according to the decoding result, this method avoids the burden of additional hardware, such hardware costs greatly reduced, from the viewpoint of the upper application terms, the method of the present invention makes exactly the same program space, the upper layer without specific programming when a single instruction defined emission or dual emission instruction, single emission instruction and switching between the dual emission instruction for the upper layer is completely transparent to the software, which greatly reduces the complexity of the application programming.

[0047] 下面以跳转指令为例,说明本发明的非对称机制在降低硬件成本方面的贡献。 [0047] In the following the jump instruction as an example, the contribution of the present invention are asymmetric in the mechanism of reducing hardware costs. 在执行跳转程序时,需要根据标志FLAG来决定是否跳转,例如实现“当a > b时则跳转”的程序时,按照传统处理方式,在两条对称的流水线中都引入FLAG,为了区分两条流水线上同时产生的FLAG,就必须记录历史条件来决定后续的状态转移,逻辑十分复杂,这种情况在微处理器的运行过程中十分罕见,但为了解决这一罕见的问题,必须引入很大的硬件开销。 When the program execution jumps need to decide whether to jump according to the flag FLAG, implemented, for example, "When a> b jump" procedure, according to the traditional approach, in two symmetric pipelines are incorporated FLAG, for FLAG distinguish between the two lines simultaneously generated, it is necessary to record the follow-up to determine the historical conditions of the state transition logic is very complicated, this is very rare during the operation of the microprocessor, but in order to solve this rare issue that must be introduce significant hardware overhead. 相比之下,本发明仅在其中一条流水线中对FLAG进行更新,不再需要进行两条流水线上的FLAG的区分,这使得流水线设计独立简单,降低了硬件成本。 In contrast, the present invention in which only one of the pipeline FLAG update, no need to distinguish the two lines of FLAG, which makes independent pipeline design is simple, reducing hardware costs.

[0048] 如果经过指令译码之后,得到的标识位指示该指令为单发射指令,则在第一流水线中完成该单发射指令的操作,例如在典型的微处理器体系结构中,第一流水线可包括第一级:读取第一操作数;第二级:读取第二操作数;和第三级:运算,得到运算结果。 [0048] If the flag after the instruction decoding, obtained indicates that the instruction is a single emission instruction, the operation is completed in a single instruction transmitting a first pipeline, for example, in a typical microprocessor architecture, the first pipeline a first stage may include: reading a first operand; second stage: reading a second operand; and third stages: acquire a computed result.

[0049] 如果经过指令译码之后,得到的标识位指示该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线和第二流水线以完全相同的方式并行运行。 [0049] If the flag after the instruction decoding, the instruction is obtained indicating a dual emission instruction, the completion of the first operation of the dual emission instruction in the first pipeline, to complete the second dual emission instruction pipeline a second operation, the first pipeline and the second pipeline runs in parallel exactly the same way.

[0050] 在微处理器工作的绝大多数情况中,两条流水线中的两个运算器ALU产生的结果的写回地址是不同的,因此可以简单地将两个运算结果同时写回各自的寄存器地址中。 [0050] In most cases, the work of the microprocessor, the result of the write back address two pipeline arithmetic unit ALU generates two are different, it can simply be written simultaneously two operation results back to their register addresses. 在本发明的一个优选实施例中,考虑到在极特殊情况下,两个运算结果的地址如果发生冲突,则把两个结果进行“或” OR运算,通过这种简单的逻辑处理,使得两条流水线中的操作都部分生效。 In a preferred embodiment of the present invention, in consideration of in extreme cases, two address calculation results in case of conflict, the results put the two "or" OR operation by this simple logic, such that two the operation of the pipeline are part of the effect.

[0051] 图3是本发明的一种微处理器指令处理系统的结构图,主要包括: [0051] FIG. 3 is a configuration diagram of a microprocessor of the instruction processing system of the present invention, including:

[0052] 寄存器301,存储包括指令,操作数,运算结果的数据; [0052] register 301, a memory comprising instructions, operands, the operation result data;

[0053] 指令读取装置302,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; [0053] The instruction reading unit 302, the address of the instruction, an instruction is read from memory, wherein said command comprises indicating said instruction is a single instruction, or transmitting identification bits dual emission instruction;

[0054] 指令译码装置303,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; [0054] The instruction decoding means 303 for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction emission or a dual emission instruction;

[0055] 指令流水线装置304,包括第一流水线装置3041和第二流水线装置3042,其中如果确定该指令为单发射指令,则在该第一流水线装置中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线装置和第二流水线装置以完全相同的方式并行运行; [0055] 304 instruction pipeline means, means 3041 comprises a first pipeline and the second pipeline means 3042, which determines if the instruction is a single emission instruction, the operation is completed in a single instruction transmitting the first pipeline means, if it is determined that dual emission instruction is an instruction, the completion of the first operation of the dual emission instruction in the first pipeline, the instruction to complete the second dual emission operation in the second pipeline, the first pipeline and the second pipeline means identical means run in parallel manner;

[0056] 写回装置305:将所述第一流水线的运算结果和所述第二流水线的运算结果写回到寄存器。 [0056] The write back means 305: the calculation result of the first pipeline and the second pipeline operation result is written back to the register.

[0057] 图4是本发明的指令处理系统的一个优选实施例的结构图,该优选实施例基于典型的微处理器架构,其中指令读取装置可由程序计数器PC、地址寄存器ITCM和指令寄存器INS来实现,程序计数器PC用于存放和指示要执行的指令的地址,地址寄存器用于保存PC中的地址,指令寄存器用于暂时存放根据地址取出的指令,等待译码。 A configuration diagram of an embodiment [0057] FIG. 4 is an instruction processing system of the present invention a preferred embodiment of the preferred embodiment based on a typical microprocessor architecture, instruction read means wherein the PC by a program counter, an instruction register and an address register INS ITCM is achieved, the program counter PC indicates the address and store instructions to be executed, the address register for holding the address in the PC, according to the instruction register for temporarily storing an instruction address fetched, decoded wait.

[0058] 指令译码装置可由指令译码器IND实现,其将指令码转变成执行此指令所需要的电信号,在本发明中,译码结果中包含指示该指令为单发射指令还是双发射指令的标识位。 [0058] The instruction decoding unit by the instruction decoder IND implemented, which will execute the script into electrical signals required for this instruction, in the present invention, the decoding result contains an indication that the instruction is a single instruction or a dual emission emission flag instruction.

[0059] 图5是根据本发明的一个优选实施例的流水线装置的结构图,第一流水线装置V-PIPE和第二流水线装置U-PIPE可分别包括由暂存器VR1/UR1构成的第一级SI,用于读取第一操作数;由暂存器VR2/UR2构成的第二级S2,用于读取第二操作数,以及由运算器ALU1/AUL2构成的第三级S3,用于完成运算。 [0059] FIG 5 is a configuration diagram of a pipeline apparatus according to a preferred embodiment according to the present invention, the first pipeline means and the second line V-PIPE means may comprise a first U-PIPE consisting register VR1 / UR1 respectively level the SI, for reading a first operand; second stage S2 consisting register VR2 / UR2, for reading the second operand, and a third stage S3 is constituted by the arithmetic unit ALU1 / AUL2, with to complete the operation. 可根据需要设计流水线的级数而不局限于本实施例给出的方式。 It can not limited to the embodiment examples given embodiment of the pipeline stages depending on design requirements. 在本发明中,如果确定该指令为单发射指令,则在该第一流水线装置中完成该单发射指令的操作,即读取指令的第一操作数至第一暂存器VR1,读取指令的第二操作数至第二暂存器VR2,并在第一运算器中对第一和第二操作数进行计算,得到运算结果。 In the present invention, if it is determined that the instruction is a single emission instruction, the operation is completed in a single instruction transmitting the first pipeline means, i.e., a first read command to the first operand register VRl, read command second operand to the second register VR2, and calculates the first and second operands of the first arithmetic unit, the operation result obtained. 如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,即读取第一操作的第一操作数至暂存器VR1,读取第一操作的第二操作数至暂存器VR2,并在第一运算器ALUl中对这两个操作数进行运算;在第二流水线中完成该双发射指令的第二操作,即读取第二操作的第一操作数至暂存器UR1,读取第二操作的第二操作数至暂存器UR2,并在第二运算器ALU2中对这两个操作数进行运算;第一流水线装置和第二流水线装置以完全相同的方式并行运行。 If it is determined that the instruction is a double emission instruction, the completion of the first operation of the dual emission instruction in the first pipeline, i.e., a first read operation to a first operand register VRl, the read operation of the first two operands to register VR2, and calculates the two operands in the first operator ALUl; dual emission completing the second instruction pipeline in a second operation, i.e., the second read operation of the first the second operand to the operand register UR1, a second read operation to the register UR2, and calculates the two operands in the second operation unit ALU2; first pipeline means and the second pipeline means run in parallel exactly the same way.

[0060] 写回装置可包括分别连接于第一运算器和第二运算器的两个暂存器,其分别存储两个运算器的结果,并通过总线写回到寄存器中的相应地址。 [0060] The write back means may comprise two result registers are connected to a first operator and a second operator, the operator are stored in two, and written back to the bus through respective address registers.

[0061] 上述实施例是用于例示性说明本发明的原理及其功效,而非用于限制本发明。 [0061] The embodiment examples are intended to illustrate the principles and effect of the present invention, the present invention is not intended to be limiting. 任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。 Anyone skilled in the art may be made without departing from the spirit and scope of the present invention, the above-described embodiments can be modified. 因此本发明的保护范围,应如本发明的权利要求书所列。 Therefore, the scope of the present invention, the invention as claimed should the requirements listed book.

Claims (10)

1.一种微处理器指令处理方法,包括: 指令读取步骤,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; 指令译码步骤,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; 运算步骤:如果确定该指令为单发射指令,则在第一流水线中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线和第二流水线以相同的方式并行运行; 写回步骤:将所述第一流水线的运算结果和所述第二流水线的运算结果写回到寄存器。 CLAIMS 1. A method for processing microprocessor instructions, comprising: instructions for reading step, the address of the instruction, an instruction is read from memory, wherein said command comprises indicating said instruction is a single instruction or a dual emission transmitting instructions flag; instruction decoding step for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction, or transmitting dual emission instruction; calculating steps of: determining if the instruction is a single instruction transmitter, the operation is completed in a single first emission instruction pipeline, if it is determined that the instruction is a double emission instruction, the dual emission is completed in the first instruction pipeline a second operation of the first operation, completing the dual emission in the second instruction pipeline, the first pipeline and the second pipeline running in parallel in the same manner; write back steps of: calculating the result of the first pipeline and the the operation result is written back to said second pipeline register.
2.根据权利要求1所述的微处理器指令处理方法,其中由所述单发射指令构成的单发射指令集和由所述双发射指令构成的双发射指令集分别实现微处理器的部分功能。 The microprocessor instruction processing method according to claim 1, wherein the emitting portion of the single functional unit configured transmit instruction set and instruction set of the dual emission dual emission instructions are configured to achieve a microprocessor .
3.根据权利要求2所述的微处理器指令处理方法,其中, 将频繁使用的常规指令设置为既由单发射指令集实现,又由双发射指令集实现; 将非频繁使用的非常规指令设置为仅由单发射指令集实现,或仅由双发射指令集实现。 The microprocessor instruction processing method according to claim 2, wherein the conventional frequently used instructions to be implemented by either a single set of emission instruction, and the instruction set implemented by dual emission; non-frequently used instructions unconventional is set only by a single set of instructions are transmitted to achieve, or a dual emission instruction set implemented only.
4.根据权利要求1所述的微处理器指令处理方法,所述第一流水线和第二流水线可分别包括读取第一操作数的第一级、读取第二操作数的第二级、以及对第一操作数和第二操作数进行运算的第三级。 The microprocessor according to claim 1, said instruction processing method, the first pipeline and the second pipeline may include reading a first operand of the first stage, second stage reads the second operand, respectively, and a first operand and a second operand for calculating a third stage.
5.根据权利要求1所述的微处理器指令处理方法,如果第一流水线的运算结果的地址和第二流水线的运算结果的地址发生冲突,则将两个运算结果进行“或”运算。 The microprocessor instruction processing method according to claim 1, if the address for calculation result of the address calculation result of the first pipeline and the second pipeline conflict, the operation result will be two "or" operation.
6.一种微处理器指令处理系统,包括: 寄存器,存储包括指令,操作数,运算结果的数据; 指令读取装置,根据指令的地址,从存储器中读取一条指令,其中所述指令中包含指示所述指令为单发射指令或双发射指令的标识位; 指令译码装置,对所读取的指令进行译码,获得包括所述标识位、操作码、操作数的译码结果,根据所述标识位,确定所述指令为单发射指令或双发射指令; 指令流水线装置,包括第一流水线装置和第二流水线装置,其中如果确定该指令为单发射指令,则在该第一流水线装置中完成该单发射指令的操作,如果确定该指令为双发射指令,则在第一流水线中完成该双发射指令中的第一操作,在第二流水线中完成该双发射指令的第二操作,第一流水线装置和第二流水线装置以完全相同的方式并行运行; 写回装置,将所述第一流水线的 A microprocessor instruction processing system, comprising: a register storing data including instructions, operands, computation of results; instruction reading means, the address of the instruction, an instruction is read from memory, wherein the instruction comprising instructing the instruction is a single instruction, or transmitting identification bits dual emission instruction; instruction decoding means for decoding the read instruction, the obtaining comprises identifying bit opcode, operand decoding result, according to the identification bit, determines the instruction is a single instruction or a dual emission emission instruction; instruction pipeline means, means comprising a first pipeline and the second pipeline means, wherein if it is determined that the instruction is a single emission instruction, the first pipeline means in the finished single emission instruction, if it is determined that the instruction is a double emission instruction, the completion of the first operation of the dual emission instruction in the first pipeline, the completion of the second operation of the dual emission in the second instruction pipeline, the first pipeline means and the second pipeline means run in parallel exactly the same way; write back means, the first pipeline 算结果和所述第二流水线的运算结果写回到寄存器。 Results of the calculation and calculation result is written back to the second pipeline register.
7.根据权利要求6所述的微处理器指令处理装置,所述指令读取装置由程序计数器、地址寄存器和指令寄存器来实现。 7. The processing means, said reading means to implement the instruction by the program counter, an instruction register and an address register according to claim 6, said microprocessor instructions.
8.根据权利要求6所述的微处理器指令处理装置,所述第一流水线装置包括由第一暂存器构成的第一级,由第二暂存器构成的第二级和由第一运算器构成的第三级;所述第二流水线包括由第三暂存器构成的第一级,由第四暂存器构成的第二级和由第二运算器构成的第三级。 The microprocessor according to claim 6, said instruction processing means, said first means comprising a first pipeline stage, a second stage composed of the second register from the first register and constituted by a first the third stage operational constituted; the second pipeline stage includes a first, second and third stage constituted by a third register constituted by the fourth register constituted by a second operator.
9.根据权利要求8所述的微处理器指令处理装置,其中, 如果确定所述指令为单发射指令,则在所述第一暂存器中读取指令的第一操作数,在所述第二暂存器中读取指令的第二操作数,在所述第一运算器中对第一操作数和第二操作数进行运算; 如果确定所述指令为双发射指令,则在所述第一暂存器中读取指令的第一操作的第一操作数,在所述第二暂存器中读取指令的第一操作的第二操作数,在第一运算器中对第一操作的第一操作数和第一操作的第二操作数进行运算;在所述第三暂存器中读取指令的第二操作的第一操作数,在所述第四暂存器中读取指令的第二操作的第二操作数,在第二运算器中对第二操作的第一操作数和第二操作的第二操作数进行运算。 The microprocessor according to claim 8, said instruction processing means, wherein if determined that the instruction is a single emission instruction, the first operand is read in the first instruction register, the said a second register in the second operand of the read instruction, the first operator in the first operand and a second operand operation; if determined that the instruction is a double emission instruction, the a first operand of the first operation in a first reading instruction register, the second operand of the first instruction in the operation of the second read register, the first operator of the first a first operand and a second operand of the first operation performed arithmetic operations; first operand of the second instruction in the operation of reading the third register, the fourth register in said read a second operand of the second operand fetch, calculates a second operand of the first operand and the second operation in the second operation in second operator.
10.根据权利要求6所述的微处理器指令处理装置,所述写回装置包括连接于第一运算器的第一结果暂存器和连接于第二运算器的第二结果暂存器,分别存储两个运算器的运算结果,并通过总线写回到寄存器中的相应地址。 The microprocessor according to claim 6, said command processing means, the write register and the first result register is connected to the second result of the second arithmetic unit is connected to a first operator comprises a return means, respectively stored operation results of the two operator, and written back to the bus through respective address registers.
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