CN103218024B - A kind of automatically reset method and device based on system synchronization Yu system clock - Google Patents
A kind of automatically reset method and device based on system synchronization Yu system clock Download PDFInfo
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- CN103218024B CN103218024B CN201310096243.5A CN201310096243A CN103218024B CN 103218024 B CN103218024 B CN 103218024B CN 201310096243 A CN201310096243 A CN 201310096243A CN 103218024 B CN103218024 B CN 103218024B
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Abstract
The present invention relates to digital communicating field, refer more particularly to a kind of automatically reset method and device based on system synchronization Yu system clock.The present invention directly utilizes system synchronization signal and produces internal reset signal with system clock, saves resource；Without hand-reset, when synchronizing that system synchronization period is stablized first after system electrification, when system synchronization period changes or when recovering normal after system clock loss can automatically generating internal reset signal so that other unit of this synchronization system can synchronous reset.
Description
Technical field
The present invention relates to digital communicating field, refer more particularly to a kind of automatically reset method and device based on system synchronization Yu system clock.
Background technology
After synchronizing system electrification work, if none of reset signal, synchronization system is resetted, very likely resulting in each several part in synchronization system is not to start simultaneously at work, thus cause logical miss, therefore, after synchronizing system electrification work, need to be reset to an effective original state.
When synchronizing system generation logic function mistake or disorder, it is also desirable to reset to an effective original state.
Therefore, effectively and reliably resetting is an important problem inside digital communicating field, is the important guarantee of synchronization system reliably working.
The most existing resetting technique be described below:
In various synchronization systems, resetting means is set, when this synchronization system is resetted by needs, inputting external reset signal to this resetting means, this resetting means produces the internal reset signal for controlling other module in this synchronization system according to external reset signal.
Prior art one, resetting means is for carrying out synchronization process to external reset signal and master clock signal, specifically, this resetting means is made up of one or more DFF, as a example by including a DFF, the clock end input master clock signal of DFF, the input input external reset signal of DFF, the outfan output internal reset signal of DFF.
Prior art two, Chinese invention patent " resetting means " (Application No.: 201180000668.0) discloses a kind of resetting means, including synchronous processing module, clock detection module and signal generator module.Synchronous processing module carries out synchronization process to external reset signal and the master clock signal of acquisition, generates synchronous reset signal and also sends signal generator module to；Clock detection module uses the auxiliary clock signal obtained to detect the master clock signal obtained, and when master clock signal exception, generates master clock abnormal indication signal and sends signal generator module to.Signal generator module, according to described synchronous reset signal and described master clock abnormal indication signal, generates internal reset signal and exports.The resetting means using the present invention to provide, when master clock is lost, remains able to correctly produce internal reset signal, so that this electronic equipment can proper reset.
The shortcoming of existing resetting technique is: 1, adds an external reset passage, wastes resource；2, place one's entire reliance upon external reset signal, when external reset signal is lost, then will cause the whole synchronization system cannot proper reset.
Summary of the invention
Deficiency for background technology, the technical problem to be solved in the present invention is to provide a kind of automatically reset method and device based on system synchronization Yu system clock, utilize system synchronization signal and clock signal of system that synchronization system self had, change according to them automatically generates internal reset signal, to reduce by an external reset passage.
In order to solve above-mentioned technical problem, the invention provides a kind of automatically reset method based on system synchronization Yu system clock, comprise the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is scanned for by step 2, employing system clock, and when the inner synchronousing signal cycle stablizes first, synchronous indicating signal level changes；
Inner synchronousing signal is monitored by step 3, employing system clock, and when the inner synchronousing signal cycle changes, step-out indication signal level changes；
Step 4, system clock is carried out phase-locked process, generate latch signal；
Latch signal is detected by step 5, employing system clock with inner synchronousing signal, and when latch signal changes, clock abnormal indication signal level changes；
Step 6, according to synchronous indicating signal, step-out indication signal or clock abnormal indication signal, generate internal reset signal and also export.
It provides the benefit that: need not take a designated lane and transmits reset signal, directly utilizes system synchronization signal and produce internal reset signal with system clock, save resource；Without hand-reset, when synchronizing that system synchronization period is stablized first after system electrification, when system synchronization period changes or when recovering normal after system clock loss can automatically generating internal reset signal so that other unit of this synchronization system can synchronous reset.
Auto-reset method based on system synchronization Yu system clock as above, it is characterised in that: described step 2 includes: after synchronizing system electrification work, scanning for inner synchronousing signal, in synchronizing search procedure, synchronous indicating signal is high level；After system enters synchronous regime, synchronous indicating signal becomes low level at the rising edge of inner synchronousing signal, hereafter, no longer performs to synchronize search work, and synchronous indicating signal keeps low level constant.It provides the benefit that: when the inner synchronousing signal cycle from instability to when stablizing transition first, synchronous indicating signal automatically generates a level change from high to low.
Auto-reset method based on system synchronization Yu system clock as above, it is characterised in that: described step 3 includes: when inner synchronousing signal cycle stability, and step-out indication signal is low level；When the inner synchronousing signal cycle changes, step-out indication signal exports a high level pulse at the rising edge of inner synchronousing signal, and the pulsewidth of this high level pulse is the positive integer times of system clock cycle.It provides the benefit that: when the inner synchronousing signal cycle changes, and step-out indication signal level can change automatically.
Auto-reset method based on system synchronization Yu system clock as above, it is characterized in that: described step 5 includes: latch signal is detected by system clock with inner synchronousing signal, when latch signal is low level, clock abnormal indication signal is high level；When latch signal is high level, clock abnormal indication signal becomes low level at the rising edge of inner synchronousing signal.It provides the benefit that: detect system clock without auxiliary clock, and when system clock recovers normal after the loss., clock abnormal indication signal level can change automatically.
In order to solve above-mentioned technical problem, present invention also offers a kind of automatically reset device based on system synchronization Yu system clock, including:
Synchronous processing module: system synchronization signal and clock signal of system carry out synchronization process, generates inner synchronousing signal and sends synchronization search module, synchronous protection module to and latch detection module；
Synchronize search module: use system clock that inner synchronousing signal is scanned for, when the inner synchronousing signal cycle stablizes first, change the output level of synchronous indicating signal, and synchronous indicating signal is sent to reset signal generation module；
Synchronous protection module: use system clock to be monitored inner synchronousing signal, when inner synchronousing signal mechanical periodicity, changes the output level of step-out indication signal, and sends step-out indication signal to reset signal generation module；
Clock phase-locked loop module: system clock carries out phase-locked process, generates latch signal and sends latch detection module to；
Latch detection module: use system clock that latch signal is detected with inner synchronousing signal, when latch signal changes, change the output level of clock abnormal indication signal, and send clock abnormal indication signal to reset signal generation module；
Reset signal generation module: according to synchronous indicating signal, step-out indication signal or clock abnormal indication signal, generates internal reset signal and exports.
Automatic reset device based on system synchronization Yu system clock as above, it is characterised in that: described synchronization search module, when only after working on power, system first enters into synchronous regime, synchronous indicating signal automatically generates a level change from high to low.It provides the benefit that: after synchronizing system electrification work, can produce an effective internal reset, it is ensured that other unit synchronizing system starts simultaneously at work.
Automatic reset device based on system synchronization Yu system clock as above, it is characterised in that: described synchronous protection module, when the inner synchronousing signal cycle changes, step-out indication signal exports a high level pulse at the rising edge of inner synchronousing signal.It provides the benefit that: when synchronizing the synchronizing signal disorder of system, can produce an effective internal reset.
Automatic reset device based on system synchronization Yu system clock as above, it is characterized in that: described latch detection module, when the latch signal level of system clock changes from low to high, clock abnormal indication signal automatically generates a level change from high to low at the rising edge of inner synchronousing signal.It provides the benefit that: when the system clock of the system of synchronization recovers normal after the loss., can produce an effective internal reset.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the automatic reset device of the present invention；
Fig. 2 is the flow chart of the auto-reset method of the embodiment of the present invention；
Fig. 3 is the schematic diagram of the synchronous processing module of the embodiment of the present invention；
Fig. 4 is the schematic diagram synchronizing search module of the embodiment of the present invention；
Fig. 5 is the schematic diagram of the synchronous protection module of the embodiment of the present invention；
Fig. 6 is the schematic diagram of the clock phase-locked loop module of the embodiment of the present invention；
Fig. 7 is the schematic diagram latching detection module of the embodiment of the present invention；
Fig. 8 is the schematic diagram of the reset signal generation module of the embodiment of the present invention.
Detailed description of the invention
Explanation of nouns: DFF as herein described is d type flip flop.
Below in conjunction with accompanying drawing, the present invention is described further.
Fig. 1 is the schematic diagram of the automatic reset device of the present invention.As shown in fig. 1, the device of the present embodiment includes:
Synchronous processing module: system synchronization signal and clock signal of system carry out synchronization process, generates inner synchronousing signal and sends synchronization search module, synchronous protection module to and latch detection module；
Synchronize search module: use system clock that inner synchronousing signal is scanned for, when the inner synchronousing signal cycle stablizes first, change the output level of synchronous indicating signal, and synchronous indicating signal is sent to reset signal generation module；
Synchronous protection module: use system clock to be monitored inner synchronousing signal, when inner synchronousing signal mechanical periodicity, changes the output level of step-out indication signal, and sends step-out indication signal to reset signal generation module；
Clock phase-locked loop module: system clock carries out phase-locked process, generates latch signal and sends latch detection module to；
Latch detection module: use system clock that latch signal is detected with inner synchronousing signal, when latch signal changes, change the output level of clock abnormal indication signal, and send clock abnormal indication signal to reset signal generation module；
Reset signal generation module: according to synchronous indicating signal, step-out indication signal or clock abnormal indication signal, generates internal reset signal and exports.
Fig. 2 is the flow chart of the auto-reset method of the embodiment of the present invention, as in figure 2 it is shown, as a example by internal reset signal high level is effective, the auto-reset method of the present embodiment comprises the following steps:
1, system synchronization signal and clock signal of system are carried out synchronization process, generate inner synchronousing signal
This step is completed by synchronous processing module, and Fig. 3 is the schematic diagram of the synchronous processing module of the embodiment of the present invention, and this synchronous processing module comprises a DFF.The clock end input system clock signal of this DFF, the input input system synchronizing signal of DFF, the outfan output inner synchronousing signal of DFF.By this DFF, system synchronization signal and clock signal of system are carried out synchronization process, obtain inner synchronousing signal.
2, using system clock to scan for inner synchronousing signal, when the inner synchronousing signal cycle stablizes first, synchronous indicating signal level changes
This step is completed by synchronizing search module, Fig. 4 is the schematic diagram synchronizing search module of the embodiment of the present invention, the clock end input system clock signal of this synchronization search module, synchronize the DIN input input inner synchronousing signal of search module, synchronize the SYN outfan output synchronous indicating signal of search module.When synchronization system just works on power, by synchronizing search module, inner synchronousing signal is scanned for, in synchronizing search procedure, synchronous indicating signal is high level, after finding first internal synchronizing pulse, in the moment of regulation, (moment of described regulation is and is finding that first internal synchronizing pulse moment rises, moment every a whole frame), whether conveyorized inspection also has internal synchronizing pulse to occur, if found 3 times continuously, just confirm to enter synchronous regime, synchronous indicating signal becomes low level at the rising edge of inner synchronousing signal, hereafter, synchronize search module and no longer perform search work, synchronous indicating signal keeps low level constant.
3, using system clock to be monitored inner synchronousing signal, when the inner synchronousing signal cycle changes, step-out indication signal level changes
This step is completed by synchronous protection module; Fig. 5 is the schematic diagram of the synchronous protection module of the embodiment of the present invention; the clock end input system clock signal of this synchronous protection module; the DIN input input inner synchronousing signal of synchronous protection module, the NONSYN outfan output step-out indication signal of synchronous protection module.Being monitored inner synchronousing signal by synchronous protection module, when inner synchronousing signal cycle stability, step-out indication signal is low level；When the inner synchronousing signal cycle changes, step-out indication signal exports a high level pulse at the rising edge of inner synchronousing signal.
Wherein, the pulsewidth of the high level pulse of step-out indication signal is the positive integer times of system clock cycle.
4, system clock is carried out phase-locked process, generate latch signal
This step is completed by clock phase-locked loop module, the schematic diagram for clock phase-locked loop module of Fig. 6 embodiment of the present invention, and this clock phase-locked loop module comprises the Clock management module within the FPGA that the PLL described in a PLL(is ALTERA company).The clock end input system clock signal of this PLL, the latch output output latch signal of PLL.By this PLL, system clock being carried out phase-locked process, stablize several all after date latch signals when system clock and become high level, when system clock is lost, latch signal becomes low level.
Clock phase-locked loop module can be realized by corresponding Clock management module inside the FPGA of other companies, it is also possible to is realized by software programming.
5, using system clock to detect latch signal with inner synchronousing signal, when latch signal changes, clock abnormal indication signal level changes
This step is completed by latching detection module, Fig. 7 is the schematic diagram latching detection module of the embodiment of the present invention, the clock end input system clock signal of this latch detection module, latch the LOKIN input input and latch signal of detection module, latch the DIN input input inner synchronousing signal of detection module, latch the ABNFLAG outfan output clock abnormal indication signal of detection module.Detecting latch signal with inner synchronousing signal by latching detection module, when latch signal is low level, clock abnormal indication signal is high level；When latch signal is high level, clock abnormal indication signal becomes low level at the rising edge of inner synchronousing signal.
6, according to synchronous indicating signal, step-out indication signal or clock abnormal indication signal, generate internal reset signal and export
This step is completed by reset signal generation module, and Fig. 8 is the schematic diagram of the reset signal generation module of the embodiment of the present invention, and this reset signal generation module comprises three inputs or door.Three inputs of this three input or door input synchronous indicating signal, step-out indication signal and clock abnormal indication signal, outfan output internal reset signal respectively.When any one road of three inputs or Men tri-tunnel input signal is high level, the output signal of three inputs or door is high level, therefore, and the outfan output effective internal reset signal of high level of three inputs or door.
On the basis of technique scheme, further, synchronous processing module can be realized by more than one DFF cascade.Specifically, the clock end equal input system clock signal of the above DFF of said one.The input input system synchronizing signal of first order DFF, the outfan of first order DFF connects the input of second level DFF, the outfan of second level DFF connects the input of third level DFF, by that analogy, it may be assumed that the outfan of previous stage DFF connects the input of next stage.Thus by said one above DFF, system synchronization signal and clock signal of system are carried out synchronization process, the outfan output inner synchronousing signal of afterbody DFF.
On the basis of technique scheme, further, in other embodiments, if as a example by internal reset signal Low level effective, reset signal generation module includes the most in the case: three input nor gates.Specifically, three inputs of three input nor gates input synchronous indicating signal, step-out indication signal and clock abnormal indication signal respectively, the outfan output internal reset signal of three input nor gates.When any one road of three tunnel input signals of three input nor gates is high level, the output signal of three input nor gates is low level, therefore, and the effective internal reset signal of outfan output low level of three input nor gates.
On the basis of technique scheme, further, in other embodiments, if as a example by internal reset signal Low level effective, reset signal generation module may include that three not gates and three inputs and door the most in the case.Specifically, synchronous indicating signal, step-out indication signal and clock abnormal indication signal connect the input of three not gates respectively, and the outfan of three not gates connects the input of three inputs and door respectively, and three inputs export internal reset signal with the outfan of door.When synchronous indicating signal, step-out indication signal, any one road of clock abnormal indication signal are high level, i.e. any one road through non-three road signals behind the door is low level, three inputs are low level with the output signal of door, therefore, three inputs and the effective internal reset signal of outfan output low level of door.
On the basis of technique scheme, further, in other embodiments, produce internal reset signal, the most automatically reset method when stablizing first iff the needs system synchronization signal cycle after the power-up, comprise the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is scanned for by step 2, employing system clock, and when the inner synchronousing signal cycle stablizes first, synchronous indicating signal level changes；
Step 3, generate internal reset signal exporting according to synchronous indicating signal.
On the basis of technique scheme, further, in other embodiments, produce internal reset signal, the most automatically reset method when the system synchronization signal cycle changes iff needs, comprise the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is monitored by step 2, employing system clock, and when the inner synchronousing signal cycle changes, step-out indication signal level changes；
Step 3, generate internal reset signal exporting according to step-out indication signal.
On the basis of technique scheme, further, in other embodiments, produce internal reset signal, the most automatically reset method when recovering normal iff needs after system clock is lost, comprise the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Step 2, system clock is carried out phase-locked process, generate latch signal；
Latch signal is detected by step 3, employing system clock with inner synchronousing signal, and when latch signal changes, clock abnormal indication signal level changes；
Step 4, generate internal reset signal exporting according to clock abnormal indication signal.
On the basis of technique scheme, further, in other embodiments, if the cycle needing system synchronization signal after the power-up stablizes first, or internal reset signal is produced when the system synchronization signal cycle changes, the most automatically reset method, comprises the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is scanned for by step 2, employing system clock, and when the inner synchronousing signal cycle stablizes first, synchronous indicating signal level changes；
Inner synchronousing signal is monitored by step 3, employing system clock, and when the inner synchronousing signal cycle changes, step-out indication signal level changes；
Step 4, generate internal reset signal according to synchronous indicating signal or step-out indication signal and export.
On the basis of technique scheme, further, in other embodiments, if the cycle needing system synchronization signal after the power-up stablizes first, or produce internal reset signal when recovering normal after system clock is lost, the most automatically reset method, comprises the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is scanned for by step 2, employing system clock, and when the inner synchronousing signal cycle stablizes first, synchronous indicating signal level changes；
Step 3, system clock is carried out phase-locked process, generate latch signal；
Latch signal is detected by step 4, employing system clock with inner synchronousing signal, and when latch signal changes, clock abnormal indication signal level changes；
Step 5, generate internal reset signal according to synchronous indicating signal or clock abnormal indication signal and export.
On the basis of technique scheme, further, in other embodiments, if needed when the system synchronization signal cycle changes, or produce internal reset signal, the most automatically reset method when recovering normal after system clock is lost, comprise the following steps:
Step one, the synchronization process that carries out system synchronization signal and clock signal of system, generate inner synchronousing signal；
Inner synchronousing signal is monitored by step 2, employing system clock, and when the inner synchronousing signal cycle changes, step-out indication signal level changes；
Step 3, system clock is carried out phase-locked process, generate latch signal；
Latch signal is detected by step 4, employing system clock with inner synchronousing signal, and when latch signal changes, clock abnormal indication signal level changes；
Step 5, generate internal reset signal according to step-out indication signal or clock abnormal indication signal and export.
The automatic reset device of the present invention is in synchronization system, this automatic reset device need not input external reset signal, can be according to the change of system synchronization signal or the change of clock signal of system, automatically generate the internal reset signal for controlling other unit in this synchronization system, so can ensure that other unit of synchronization system is all synchronous reset.Other unit of this synchronization system can be other board, it is also possible to be other chip, it is also possible to be other program module in this chip.
Certainly; the present invention can also have other various embodiments; in the case of without departing substantially from present invention spirit and essence thereof; those of ordinary skill in the art are when making change accordingly and deformation according to the present invention, but these change accordingly and deform the protection domain that all should belong to appended claims of the invention.
Claims (4)
1. an automatically reset device based on system synchronization Yu system clock, including:
Synchronous processing module: system synchronization signal and clock signal of system carry out synchronization process, generates internal
Synchronizing signal also sends synchronization search module, synchronous protection module to and latches detection module；Described inside
Synchronizing signal is: the outfan of previous stage DFF connects the input of next stage, will by more than one DFF
System synchronization signal and clock signal of system carry out synchronization process, and the outfan output of afterbody DFF is internal
Synchronizing signal；
Synchronize search module: use system clock that inner synchronousing signal is scanned for, inner synchronousing signal week
When phase stablizes first, change the output level of synchronous indicating signal, and synchronous indicating signal is passed
Give reset signal generation module；
Synchronous protection module: use system clock that inner synchronousing signal is monitored, work as inner synchronousing signal
During mechanical periodicity, change the output level of step-out indication signal, and step-out indication signal is sent to reset letter
Number generation module；
Clock phase-locked loop module: system clock carries out phase-locked process, generates latch signal and sends latch inspection to
Survey module；
Latch detection module: use system clock that latch signal is detected with inner synchronousing signal, work as lock
Deposit signal when changing, change the output level of clock abnormal indication signal, and by abnormal for clock instruction letter
Number send reset signal generation module to；
Reset signal generation module: according to synchronous indicating signal, step-out indication signal or clock abnormal instruction letter
Number, generate internal reset signal and export.
2. automatic reset device based on system synchronization Yu system clock as claimed in claim 1, its feature
It is: described synchronization search module, when only system first enters into synchronous regime after working on power, synchronizes
Indication signal automatically generates a level change from high to low.
3. automatic reset device based on system synchronization Yu system clock as claimed in claim 1, its feature
Being: described synchronous protection module, when the inner synchronousing signal cycle changes, step-out indication signal exists
Rising edge one high level pulse of output of inner synchronousing signal.
4. the automatic reset device based on system synchronization Yu system clock as described in claim 1,2 or 3,
It is characterized in that: described latch detection module, when the latch signal level of system clock changes from low to high,
Clock abnormal indication signal automatically generates a level change from high to low at the rising edge of inner synchronousing signal
Change.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489723A (en) * | 2001-07-24 | 2004-04-14 | 皇家菲利浦电子有限公司 | Method and system using common reset and slower reset clock |
| CN101258682A (en) * | 2005-07-07 | 2008-09-03 | 德克萨斯仪器股份有限公司 | Automatic input error recovery circuit and method for recursive digital filters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489723A (en) * | 2001-07-24 | 2004-04-14 | 皇家菲利浦电子有限公司 | Method and system using common reset and slower reset clock |
| CN101258682A (en) * | 2005-07-07 | 2008-09-03 | 德克萨斯仪器股份有限公司 | Automatic input error recovery circuit and method for recursive digital filters |
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