CN103200379A - Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm - Google Patents
Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm Download PDFInfo
- Publication number
- CN103200379A CN103200379A CN2013100601653A CN201310060165A CN103200379A CN 103200379 A CN103200379 A CN 103200379A CN 2013100601653 A CN2013100601653 A CN 2013100601653A CN 201310060165 A CN201310060165 A CN 201310060165A CN 103200379 A CN103200379 A CN 103200379A
- Authority
- CN
- China
- Prior art keywords
- lvds
- error diffusion
- integrated circuit
- pixel
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention provides a low voltage differential signaling (LVDS) interface integrated circuit realizing method based on the error diffusion algorithm. The method comprises the steps of educing the error diffusion algorithm to each path of RGB (red, green and blue) image data before input of LVDS, and reducing image quality reduction due to direct elimination of low-position signals. Line storage used at time of the error diffusion algorithm is designed by utilization of first in first out (FIFO), and a one-in four-out random-access memory (RAM) is set up at time of coding the LVDS interface, and therefore the condition that four RAMs (one in one out) are needed in the prior art is avoided. The LVDS interface integrated circuit realizing method finishes the very large scale integrated circuit (VLSI) design for a raised method, and conducts deep research on key points of the VLSI, and finishes code writing of Verilog-hardware description language (HDL) and function achievement.
Description
Technical field
The invention belongs to Digital Television, digital video image processing and Display Technique field, be specifically related to a kind of error diffusion algorithm and LVDS interface coding, realized satisfying to the effect that reduces error when isotopic number LVDS interface supplies number, improved the effect that video image shows.
Background technology
The core of LVDS technology is to adopt extremely low voltage swing high speed differential transmission data, can realize point-to-point or a bit to link of multiple spot, has that electromagnetic interference is little, the amplitude of oscillation is little, power consumption is little, for characteristics such as the immunity of noise are good.
Because above-mentioned advantage LVDS interface becomes a kind of panel TV main flow interface that high speed data transfer can be provided, the screen of corresponding different bit wides has different LVDS interfaces.For example 8 screen needs 8 LVDS interface, and 4 pairs of differential pairs transmit R, G, B three tunnel each 8 effective view data.If last screen image data are 10 bit wides, the method that adopts directly intercepting to fall rgb pixel data low level is in the prior art handled and is gone up the needs that screen image satisfies distinct interface, can affect greatly picture quality when reducing data bit width.
Summary of the invention
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of lvds interface integrated circuit implementation method based on error diffusion algorithm is provided, this method is gone into error diffusion algorithm to each pass of the rgb image data of input before the LVDS, reduce and directly cast out the image quality decrease that the low level signal causes, can finish the code of Verilog-HDL writes and the function realization, be implemented in to satisfy not give when isotopic number LVDS interface is for number and reduce the effect of error, thereby effectively improve the effect that video image shows.
The objective of the invention is to solve by the following technical programs:
This lvds interface integrated circuit implementation method based on error diffusion algorithm may further comprise the steps:
1) before the lvds coding, R, G, B three tunnel are carried out error diffusion respectively handle, at first go low level to handle to the signal of importing 10 bit wides, be divided into most-significant byte and low 2 two parts data or high 6 and low 4 two parts data;
2) low data of separating is sent in the delay circuit, delegation is upper left above the acquisition current pixel, just goes up low data eB, the eC of upper right three pixels, eD; Obtain the low data eA of current pixel leftmost pixel by register delay;
3) with contiguous four pixels of current pixel cast out low data eA, eB, eC, eD are diffused on this pixel, namely pass through adder, according to the diffusion ratio with present input data and eA, eB, eC, eD addition, after the error diffusion and require truncation to send into the lvds coding according to bit wide again.
Further, above lvds coding is the characteristic according to screen, for satisfying different refresh rates, resolution needs adjustment picture point clock; For the physical points clock that satisfies high field frequency, high-resolution input picture adopts the mode that reduces the input picture Dot Clock and improve the data multiple, select multichannel lvds for use.Further, by advancing four and go out ram of building, the data multiple is increased to satisfy coding requirement.
Further, when error diffusion was handled, the diffusion ratio all was set at 1/4, is equivalent to move to right two on the circuit.
Above-mentioned at image pixel processing sequence characteristics, controller judges that to the image border first row, first row and last row pixel adopt straight-through the processing.
Further, adopt pipelining, produce the sum of errors of three neighborhood pixels under rising edge clock triggers, sum of errors inserts parallel adder as an input, reduces the input port number of parallel adder, reduces circuit complexity.
The present invention has following beneficial effect:
The present invention adopts error diffusion algorithm that the pixel that enters before the interface is handled respectively.Error diffusion algorithm is based on integral characteristic and the low-pass characteristic of eyes, and human eye is to the total gray scale in this cell area or the impression of color always to the impression of a less cell area gray scale or color outside certain distance.If on the pixel of closing on around the error that will cast out is diffused into according to a certain percentage, with regard to a pixel group, error is not cast out.But see the gamma error minimum of original image and demonstration image after the error diffusion on the whole.
Description of drawings
Fig. 1 flows to schematic diagram for vision signal of the present invention;
Fig. 2 will give up the low level signal for error diffusion algorithm and be diffused into other pixel schematic diagrames;
Fig. 3 accepts to be diffused into error signal schematic diagram on it for the error diffusion algorithm current pixel;
Fig. 4 handles and conveying flow for signal errors;
Fig. 5 is the error diffusion circuit block diagram;
Fig. 6 is the delay circuit block diagram;
Fig. 7 is lvds interface schematic diagram;
Fig. 8 carries out the vesa coding schematic diagram of lvds for rgb signal;
Fig. 9 shields circuit block diagram for the 120hz1080p image adopts on 4 road LVDS interfaces.
Embodiment
Referring to Fig. 1, the present invention is based on the lvds interface integrated circuit implementation method of error diffusion algorithm, specifically may further comprise the steps:
1) before the lvds coding, R, G, B three tunnel to be carried out error diffusion respectively handle, the diffusion ratio all is set at 1/4, is equivalent to move to right two on the circuit.At first go low level to handle to the signal of importing 10 bit wides, be divided into most-significant byte and low 2 two parts data or high 6 and low 4 two parts data; At image pixel processing sequence characteristics, controller judges that to the image border first row, first row and last row pixel adopt straight-through the processing.
Lvds coding of the present invention is the characteristic according to screen, for satisfying different refresh rates, resolution needs adjustment picture point clock; For the physical points clock that satisfies high field frequency, high-resolution input picture adopts the mode that reduces the input picture Dot Clock and improve the data multiple, select multichannel lvds for use.It increases to satisfy coding requirement by advancing four and go out ram of building with the data multiple.
2) low data of separating is sent in the delay circuit, delegation is upper left above the acquisition current pixel, just goes up low data eB, the eC of upper right three pixels, eD; Obtain the low data eA of current pixel leftmost pixel by register delay;
3) with contiguous four pixels of current pixel cast out low data eA, eB, eC, eD are diffused on this pixel, namely pass through adder, according to the diffusion ratio with present input data and eA, eB, eC, eD addition, after the error diffusion and require truncation to send into the lvds coding according to bit wide again.
More than adopt pipelining, produce the sum of errors of three neighborhood pixels under rising edge clock triggers, sum of errors inserts parallel adder as an input, reduces the input port number of parallel adder, reduces circuit complexity.
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Error diffusion algorithm
Error diffusion algorithm is based on integral characteristic and the low-pass characteristic of eyes, and human eye is to the total gray scale in this cell area or the impression of color always to the impression of a less cell area gray scale or color outside certain distance.When watching television image, not to watch to pixel one by one, but watch a pixel group that what eyes were experienced is the total gray scale of this pixel group or total color.
The vision signal that interface circuit is sent here all is to transmit by pixel ground line by line, according to from top to bottom, from left to right order carries out, when carrying out all can causing error when the low level of data is cast out in the bit wide adjustment to picture signal, if directly cast out these errors, the quality of image will be had a strong impact on.If be diffused into this error on the pixel of closing on every side according to certain ratio, with regard to current pixel, this error is cast out, gray scale or the color of the pixel group that but the gray scale that human eye is experienced or color are current pixel and surrounding pixel thereof to be formed, with regard to this pixel group, error is not cast out.Therefore, as a whole, the gamma error minimum of original image and demonstration image after the introducing error diffusion technique.
More than comprehensive, error diffusion algorithm of the present invention is that the truncation error with current pixel is diffused on the contiguous pixel by a certain percentage, local error is near at hand and has obtained compensation on the pixel, through pursuing the processing of pixel line by line, both can finish the processing to entire image, the method of this contiguous diffusion makes system have the ability of self-correction, becomes a degeneration factor.
Fig. 2 is the schematic diagram of error diffusion algorithm, the pixel that modest circle representative is being handled, filled circles representative not have processing and with just in the relevant pixel of processed pixels, open circles represents other pixel, (i, j) the capable j row of expression i pixel, (i j) represents the error of the quantification of this pixel, E(i to E, j) be diffused on four contiguous untreated pixels according to the direction among the figure and ratio, error diffusion can only be diffused on the untreated pixel.As can be seen from the figure, the ratio of horizontal direction and vertical direction is heavier, is respectively 7/16 and 5/16, the lower left to the lower right to ratio lighter, be respectively 3/16 and 1/16.
The method of calculating the current pixel gray value from the angle of " error reception " has been described among Fig. 3, current pixel P(i j) receives four treated neighborhood pixels A(i, j-1), B(i-1, j-1), C(i-1, j), D(i-1, j+1) ratio is respectively 7/16,1/16,5/16,3/16, and both gray scales of current pixel is given the LVDS interface after adding these four parts of errors earlier again.Its model subtracts each other to obtain encoding error by subtracter with encoder input and output as shown in Figure 4, and among Fig. 4,1D represents to postpone 1 pixel, and 1H represents to postpone 1 row, and 1H+1D represents to postpone 1 row and adds 1 pixel, and 1H-1D represents to postpone 1 row and subtracts 1 pixel.EA, eB, eC, eD are respectively the errors that A, B, C and D pixel are diffused into current pixel.
In error diffusion algorithm, first row, the pixel in first row and last row does not exist A, B, four neighborhood pixels of C, D simultaneously, needs special processing.The present invention adopts " leading directly to " mode, and both adder was ignored four tunnel error signals, and the output of adder and input " are led directly to ", realizes easily on this mode circuit.
The error diffusion algorithm circuit is realized
The digital video signal that interface circuit is sent here is red (R), green (G) of 3 tunnel 10 bit wides, blue (B) primary colour signal, is example with one road signal wherein, and the method for designing of other two paths of signals is just the same.
For suitable 6 bit wides and 8 bit wide signals being provided for the LVDS interface, need go low level to handle to 10 bit wide data, if directly cast out, gray scale significantly reduces, and picture quality is very poor, for this reason, introduce error diffusion technique, will hang down 4 and low 2 respectively and be diffused into neighborhood pixels.
Fig. 5 is the realization block diagram of error diffusion circuit.Formed by adder, controller and three modules of delay circuit.Controller is according to Vsync, blank signal, and at rising edge generation bypass and the work signal of clk, controller outputs a control signal to adder, and whether bypass control adder " leads directly to ", and whether work control lag circuit works.When current pixel belongs to first row, first row or last row, bypass=1, otherwise, bypass=0.Work is to delay circuit for controller output control signal, effectively distinguish and postpone the time zone of a clock in the data of each row, work=1, other time zone (blanking interval of picture signal) work=0, postpone a clock and be because the output of adder with respect to input delay a clock, like this, the FIFO in the delay circuit could correct error signal of storing adder output.
Be convenient to the hardware realization in order to simplify circuit, the diffusion ratio among the figure all is set at 1/4, is equivalent to move to right two on the circuit.In the delay cell, postpone 1 pixel and postpone 1 data clock exactly, postponing 1 row is exactly to postpone the sum of all pixels that N(N is delegation) individual data clock, can utilize FIFO stack FIFO to realize.
Among Fig. 5, road signal in the input representative image rgb signal.Clk is the data clock of input, at the clk rising edge, adder to former pixel input and through the neighborhood pixels data eA that delay and (eB+eC+eD) totally three tunnel inputs handle, implementation algorithm bit=input+[eA+(eB+eC+eD)]/4, its arithmetic speed is had relatively high expectations, and adopts parallel adder here.When bypass=1, adder is ignored all errors, and input and output " are led directly to ", i.e. bit=input.As input during near maximum 1024, adding that error signal might produce overflows, and makes output bit become very little, makes the mistake, so need overflow saturated processing to adder, has both produced when overflowing, and forcing bit is maximum 1024.10 signal bit[9:0 of adder output], get high 6 bit[9:4] and most-significant byte bit[9:2] respectively as the error diffusion signal of current demand signal.
Error signal in the adder will be divided by 4, and then with the input addition, be example to be output as 8 bit wides, its algorithm can be rewritten as: bit=[inputx4+eA+(eB+eC+eD)]/4, namely expansion input hangs down 2 earlier, and is taken as " 00 ", is equivalent to input and multiply by 4, and then with all error additions, high 10 that extract addition result get final product.Adder part verilog is described below:
Fig. 6 is the specific implementation of delay circuit, and it is made up of FIFO, two d type flip flop DFF1 and DFF2, two adder ADD1 and ADD2, a comparator and some gate circuits.The adder among Fig. 5 is given in the output of delay circuit, and the task of delay circuit is three neighborhood pixels B, C, the sum of errors of D: the eB+eC+eD that correctly produces the current pixel lastrow.When having only work=1, trigger, adder and FIFO could work; Otherwise trigger, adder and FIFO keep original data constant.
Received image signal input be by from left to right, from top to bottom order transmits, after adder is exported the error signal of first pixel, working signal work=1, work inserts the written request signal wrreq of FIFO, ensuing clk rising edge, FIFO begins to store the error signal bit[3:0 of all pixels of the din that inserts input] or bit[1:0], along with the storage of the error signal of FIFO, unit number uesdw of its storage data increases progressively.Constant is set at the sum of all pixels that N-5(N is delegation among Fig. 6), when usedw equals constant, comparator just is output as 1, the reading request signal rdreq that makes FIFO is 1, FIFO output dout begin output delay error signal, later rising edge clock, wrreq and rdreq are 1 simultaneously, data of the every storage of FIFO, also export simultaneously data that postponed, make usedw always equal constant value, comparator output remains 1, the degree of depth that rdreq also remains 1, FIFO can be taken as the sum of all pixels N of delegation.Adopt pipelining to obtain sum of errors eB+eC+eD, bring sum of errors into Fig. 5 adder.
After introducing error diffusion algorithm, by the space integral of human eye, visually improved display gray scale, eliminated profile, image quality has clear improvement.
3, LVDS principle and realization
The figure place of screen has corresponding relation with LVDS differential pair (differential path), and the output channel of 10 LVDS has 5 pairs of differential pairs, and 8 LVDS is 4 pairs, and 6 LVDS is 3 pairs, 7 the RGB data of all encoding on their each road differential pair.It is the differential pair of 7 bit data that rgb signal after the error diffusion all will be compiled, as shown in Figure 7.The pixel data of 10 each route error diffusion module outputs of LVDS, row synchronous hs, field synchronization vs, a row effective de form: 30+hs+vs+de+0+0=35=5x7, each road of 8: 24+hs+vs+de+0=28=4x7, each road of 6: 18+hs+vs+de=21=3x7.Coded system as shown in Figure 8.
Refresh rate (field frequency) and the Dot Clock of screen, resolution has close relationship, will finally show and need adjust the input picture Dot Clock according to the physical points clock of screen, the physical points clock of general screen is 74.25Mhz, must reduce the Dot Clock of input picture during greater than this value.For 1366x768(1280x720) screen of resolution, the demand of Dot Clock is 74.25Mhz, just the physical points clock with screen is the same, so single channel LVDS gets final product.For the screen of 1920x1080 resolution, the Dot Clock frequency of input picture is 148.5Mhz, and the physical points clock of screen is 74.25Mhz, so the method for taking is: with the Dot Clock frequency halving of input picture, data double, and therefore needs to adopt dual-channel LVDS.More than be to analyze by 60Hz, if the input picture of common 120Hz1920x1080 is to the TV of 120Hz, Dot Clock will reach 297Mhz, thus when mixing down to 74.25Mhz, the input point clock data need be turned over 4 times, so need select 4 road LVDS for use.Be example with the Changhong TV, the corresponding a pair of differential pair of each road LVDS, thus 2 pairs of differential pairs of 60Hz1080p TV, 4 pairs of differential pairs of 120Hz1080p TV.For circuit, in order not allow the input point clock increase, LVDS can be become 4 road LVDS.Circuit structure is wherein built 1 one with trigger and is advanced four and go out ram as shown in Figure 9, avoids directly adopting one-in-and-one-out ram to need 4, has saved resource.
Claims (6)
1. the lvds interface integrated circuit implementation method based on error diffusion algorithm is characterized in that, may further comprise the steps:
1) before the lvds coding, R, G, B three tunnel are carried out error diffusion respectively handle, at first go low level to handle to the signal of importing 10 bit wides, be divided into most-significant byte and low 2 two parts data or high 6 and low 4 two parts data;
2) low data of separating is sent in the delay circuit, delegation is upper left above the acquisition current pixel, just goes up low data eB, the eC of upper right three pixels, eD; Obtain the low data eA of current pixel leftmost pixel by register delay;
3) with contiguous four pixels of current pixel cast out low data eA, eB, eC, eD are diffused on this pixel, namely pass through adder, according to the diffusion ratio with present input data and eA, eB, eC, eD addition, after the error diffusion and require truncation to send into the lvds coding according to bit wide again.
2. the lvds interface integrated circuit implementation method based on error diffusion algorithm according to claim 1 is characterized in that, the lvds coding is the characteristic according to screen, for satisfying different refresh rates, resolution needs adjustment picture point clock; For the physical points clock that satisfies high field frequency, high-resolution input picture adopts the mode that reduces the input picture Dot Clock and improve the data multiple, select multichannel lvds for use.
3. the lvds interface integrated circuit implementation method based on error diffusion algorithm according to claim 2 is characterized in that, by advancing four and go out ram of building, the data multiple is increased to satisfy coding requirement.
4. the lvds interface integrated circuit implementation method based on error diffusion algorithm according to claim 1 is characterized in that the diffusion ratio all is set at 1/4, is equivalent to move to right two on the circuit.
5. the lvds interface integrated circuit implementation method based on error diffusion algorithm according to claim 1, it is characterized in that, at image pixel processing sequence characteristics, controller judges that to the image border first row, first row and last row pixel adopt straight-through the processing.
6. the lvds interface integrated circuit implementation method based on error diffusion algorithm according to claim 1, it is characterized in that, adopt pipelining, under triggering, rising edge clock produces the sum of errors of three neighborhood pixels, sum of errors inserts parallel adder as an input, reduce the input port number of parallel adder, reduce circuit complexity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100601653A CN103200379A (en) | 2013-02-26 | 2013-02-26 | Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100601653A CN103200379A (en) | 2013-02-26 | 2013-02-26 | Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103200379A true CN103200379A (en) | 2013-07-10 |
Family
ID=48722721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100601653A Pending CN103200379A (en) | 2013-02-26 | 2013-02-26 | Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103200379A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257566A (en) * | 2018-01-23 | 2018-07-06 | 深圳市华星光电技术有限公司 | Source electrode drive circuit and liquid crystal display drive circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW508941B (en) * | 2001-04-20 | 2002-11-01 | Chunghwa Picture Tubes Ltd | Error diffusion implementation method applied on plasma display panel |
| CN2624337Y (en) * | 2003-06-10 | 2004-07-07 | 海信集团有限公司 | Error diffusion jitter processing circuit for color digital signal of lattice driven display |
| CN1700750A (en) * | 2005-06-09 | 2005-11-23 | 海信集团有限公司 | Circuit for implementing compatibility of multiple display modules using MAP network |
| JP3785922B2 (en) * | 2000-10-25 | 2006-06-14 | 日本ビクター株式会社 | Error diffusion processing method for display device |
| CN1801279A (en) * | 2006-01-13 | 2006-07-12 | 彩虹集团电子股份有限公司 | Method for improving gray scale grade of plasma display panel |
| CN201773567U (en) * | 2010-04-26 | 2011-03-23 | 苏州长风有限责任公司 | LVDS signal encoding circuit for display |
-
2013
- 2013-02-26 CN CN2013100601653A patent/CN103200379A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3785922B2 (en) * | 2000-10-25 | 2006-06-14 | 日本ビクター株式会社 | Error diffusion processing method for display device |
| TW508941B (en) * | 2001-04-20 | 2002-11-01 | Chunghwa Picture Tubes Ltd | Error diffusion implementation method applied on plasma display panel |
| CN2624337Y (en) * | 2003-06-10 | 2004-07-07 | 海信集团有限公司 | Error diffusion jitter processing circuit for color digital signal of lattice driven display |
| CN1700750A (en) * | 2005-06-09 | 2005-11-23 | 海信集团有限公司 | Circuit for implementing compatibility of multiple display modules using MAP network |
| CN1801279A (en) * | 2006-01-13 | 2006-07-12 | 彩虹集团电子股份有限公司 | Method for improving gray scale grade of plasma display panel |
| CN201773567U (en) * | 2010-04-26 | 2011-03-23 | 苏州长风有限责任公司 | LVDS signal encoding circuit for display |
Non-Patent Citations (1)
| Title |
|---|
| 梁宁、沈思宽、孙鉴: ""用于彩色PDP中的误差扩散电路"", 《现代显示》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257566A (en) * | 2018-01-23 | 2018-07-06 | 深圳市华星光电技术有限公司 | Source electrode drive circuit and liquid crystal display drive circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103475842B (en) | LVDS video signal is converted to MIPI video signal method | |
| CN105354809B (en) | A kind of pre-distortion method and device based on output image location of pixels index | |
| CN105047140A (en) | Self-adapting dynamic backlight control system and method based on image content | |
| CN105491373B (en) | A kind of LVDS vision signals single channel turns the device and method of multichannel | |
| CN103269425A (en) | Multifunctional intelligent image conversion system | |
| CN105721818A (en) | Signal conversion method and device | |
| US9697795B2 (en) | Video processing device and method | |
| CN103813107A (en) | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) | |
| CN102402918A (en) | Method for improving picture quality and liquid crystal display (LCD) | |
| CN105304053B (en) | Initial signal control method, chip and display panel in timing controller | |
| CN104732497A (en) | Image defogging method, FPGA and defogging system including FPGA | |
| CN101814269A (en) | Method and device for simultaneously displaying multiple images in real time on full color LED dot matrix | |
| CN105208246A (en) | Display screen parameter adaptive type display screen assembly and control method | |
| CN103200379A (en) | Low voltage differential signaling (LVDS) interface integrated circuit realizing method based on error diffusion algorithm | |
| CN103414907B (en) | Method capable of improving 3D displayer crosstalk | |
| CN102932661A (en) | Median filtering matching error correction method for disparity map, and circuit for implementing method | |
| CN105023250B (en) | A kind of realtime graphic system for adaptive enhancement and method based on FPGA | |
| CN108121522B (en) | Inverse sampling method for pre-distorted flat display picture based on edge direction correlation | |
| CN102158670B (en) | Digital video image contrast adaptive-stretching method and system | |
| TW200504618A (en) | Method and apparatus for image frame synchronization | |
| US11115623B2 (en) | Systems and methods for asymmetric image splitter with line mark memory | |
| CN109978787B (en) | Image processing method based on biological visual computing model | |
| CN105516633B (en) | A kind of image processing system | |
| CN107147890B (en) | A kind of more video scaling modules and concurrent working method of compatible different resolution and breadth length ratio | |
| CN102946502B (en) | A kind of high-speed data multichannel splits transmission processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130710 |