CN103199889B - Field programmable gata array (FPGA) implementation method of iteration frequency domain anti-interference algorithm - Google Patents

Abstract

The invention provides a field programmable gata array (FPGA) implementation method of an iteration frequency domain anti-interference algorithm. The FPGA implementation method of the iteration frequency domain anti-interference algorithm includes the steps: conducting windowing operation after AD sample is conducted to satellite signals which are converted down into intermediate frequency; selecting appropriate threshold optimal coefficients after a fast Fourier transform (FFT) algorithm is conducted; deducing a self-adaptive iteration threshold and reducing the value of frequency points with frequency domain amplitudes larger than the threshold to threshold value; and finally conducting inverse fast Fourier transform (IFFT) and merging and outputting the results after the IFFT. By means of the FPGA implementation method of the iteration frequency domain anti-interference algorithm, an interference detection threshold is set self-adaptively, dynamic interference rejection capability is good, the phenomenon that hardware resources are occupied due to the fact that middle process data need to be stored in repeated judgments, the FPGA, namely the technology of exchanging time for resources, is fully used, and hardware resource consumption is reduced greatly.

Description

The FPGA implementation method of the anti-interference algorithm of a kind of iterative frequency-domain

Technical field

The hardware that the present invention relates to a kind of anti-interference algorithm is realized, and particularly a kind of FPGA of the anti-interference algorithm of frequency domain based on iteration thresholding realizes technology, the judgement of disturbing for spread spectrum radio communications system and inhibition.

Background technology

Wireless communication technology plays an increasingly important role in modern communication field, but because wireless signal is extremely faint, easily be subject to various natural or artificial interference and cannot use, therefore, need to introduce interference mitigation technology and improve the antijamming capability of wireless communication system.Disturb because artificial disturbance mostly is arrowband, effectively Narrow Band Interference Suppression Technique, can greatly improve the performance of communication system.

In anti-interference algorithm, the judgement of interference and inhibition are the cores of whole algorithm.Wherein wave trap method is one of conventional algorithm.So-called wave trap method, exactly by signal from time domain is transformed into frequency domain, the amplitude of frequency domain and thresholding are made comparisons, sagging the signal frequency point amplitude that is greater than thresholding, complete interference inhibition work.

Document 1 " Suppression of Multiple Narrowband Interference in a Spread Spectrum Communication System[IEEE J; 2000; SAC-18 (8); 1347-1356] " discloses several conventional thresholding computational algorithms, particularly single order is apart from threshold algorithm TH=K μ, wherein K is thresholding optimized coefficients, and μ is for receiving signal average.But the method adopts fixed threshold, under dynamic interference environment, can not effectively suppress to disturb.

Document 2 " the Suppression of narrow band interference research [electronic information countermeasure techniques; pp; 51-53; 2009] based on adaptive threshold under low signal-to-noise ratio " proposes spread-spectrum signal under noiseless condition and after DFT, is approximately narrowband Gaussian signal, its envelope Rayleigh distributed, square obeys index distribution of envelope.By the derivation of exponential distribution probability density formula, propose at single order, apart from thresholding optimized coefficients K >=8 o'clock in threshold algorithm, under the condition of noiseless existence, can not cause damage to useful signal.Meanwhile, disclose a kind of segmentation interference suppression algorithm, chosen different thresholdings by the power that calculates current demand signal.But this algorithm complex is high, and expense is large.

Document 3 " a kind of overlapping windowing frequency domain suppresses arrowband algorithm of interference and research [modern defense technology, pp, 4-6,2010] " proposes a kind of overlapping windowing arrowband frequency domain interference Restrainable algorithms.Wherein use the conclusion of document 2, according to the feature of narrowband Gaussian signal envelope square obeys index distribution, choose thresholding optimized coefficients K=5, using the first moment thresholding obtaining as iteration thresholding, the judgement of disturbing and inhibition.But this algorithm is in the process of inhibition disturbing, the signal amplitude that is greater than thresholding is sunk to zero, this kind of method can cause damage to useful signal under the higher Narrowband Jamming of jamming-to-signal ratio, can only be applicable to single-tone or multitone and disturb, and in this document, not provide the particular hardware realization of algorithm.

In sum, existing document has much been used narrowband Gaussian model for the anti-interference algorithm of frequency domain, and choose decision threshold according to this characteristic of square obeys index distribution of its envelope, but find in the time of specific implementation, because of square numerical value of envelope often very large, can take very many storage resources, this is to be reluctant to see in specific implementation, and existing document fails to provide the jamproof FPGA realization of the iterative frequency-domain of disturbing for arrowband.

Summary of the invention

In order to overcome the deficiencies in the prior art, the present invention proposes a kind ofly to realize technology based on single order apart from the jamproof FPGA of frequency domain of iteration self-adapting thresholding.From this angle of narrowband Gaussian signal envelope Rayleigh distributed, choose suitable thresholding optimized coefficients, derive adaptive iteration thresholding, the frequency that frequency domain amplitude is greater than to thresholding sink to threshold value, can ensure that useful signal can all pass through, the storage resources that can greatly reduce hardware simultaneously, completes the inhibition work of interference.

The technical solution adopted for the present invention to solve the technical problems comprises the following steps:

(1) by under change to intermediate frequency satellite-signal carry out AD sampling, the data that obtain are output as two-way, 1/2 window length delay is carried out on a road, and two paths of data is input to respectively to windowing module;

(2) windowing module is that the data of input are carried out windowing operation, and window function adopts broad sense hamming window, and window length is L, adopts the quantification of 8 bit data bit wides; After windowing has operated, data input FFT module;

(3) RAM that is L in degree of depth of FFT module use checks the data of input and stores, and reading out data is transported to FFT core afterwards, carries out FFT computing.FFT is set to Pipelined, Streaming I/O pattern, and operating frequency is f _in, f _inidentical with AD sampling clock, the output of its computing has real part Re and imaginary part Im two parts, and the mould value R jointly calculating by these two parts with by real part imaginary part in the present invention merges into a road signal according to senior middle school's low level, i.e. { Re, Im, R}, is transported to and disturbs identification and suppress module;

(4) each interference identification is as follows with the course of work that suppresses module:

A. set up two-port RAM core RAM1 and RAM2 that two degree of depth are L=512, RAM1 work is selected in data input selection unit, and the data of FFT output are with clock f _instore in RAM1, calculate the L point cumulative sum of mould value R in stored data simultaneously and threshold value k is thresholding optimized coefficients;

B. after RAM1 is filled with, RAM2 work is selected in data input selection unit, and the data of FFT output are deposited in RAM2, calculates L point cumulative sum SUM and the threshold value TH of stored data mould value R in repeating step a simultaneously ₁work;

C. in the process of RAM2 data storage, to the data in RAM1 with clock f _sread f _s=N*f _in, N is iterations; Can obtain, can read 3 times the data in RAM1 in this following period of time of RAM2 data storage; A flag register that bit wide is identical with the RAM1 degree of depth is set, in the process that RAM1 first pass is read, will in the data that read, represents a part of R of mould value _jwith TH ₁compare, j=1,2,3...L, if be greater than TH ₁the corresponding position of flag register puts 1, i.e. flag[j-1]=1 (because the bit wide of flag is since 0, therefore need to use j-1 to represent the response position of flag), SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged; Read the complete moment at first pass, calculate thresholding TH by up-to-date SUM ₂, start RAM1 to read for second time; By the data R reading _jwith TH ₂relatively, if R _jbe greater than thresholding TH ₂, now check whether the relevant position of flag is 1, if 1, flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jbe less than thresholding TH ₂, flag corresponding positions and SUM remain unchanged; Read the complete moment at second time, calculate thresholding TH according to up-to-date SUM value ₃, start the 3rd time read; The 3rd time to N-1; All over reading done operation and to read done operation for second time identical, a to the last reading out data, N, all over reading out data, can obtain threshold T H by N-1 time read operation _nif, the data R now reading _jbe greater than TH _n, by the real part Re reading _jbe set to TH _n, imaginary part Im _jbe set to 0 output, i.e. Re _j=TH _n, Im _j=; Otherwise by the real part Re reading _jwith imaginary part Im _jdata are in statu quo exported;

D. in the time that the data decision of RAM1 is complete, the data in RAM2 are also stored end, and now the work to the Data duplication step c in RAM2, starts to store new data to RAM1;

(5) will disturb the data of identification and the output of inhibition module with clock f _sbe input to IFFT module, store by two-port RAM in this module and with clock f _inread, complete the conversion of data rate.The data input IFFT core reading, carries out inverse transformation output;

(6) output of two-way IFFT module is directly added to merging, flows to external interface, anti-interference end-of-job.

The invention has the beneficial effects as follows: the FPGA of the anti-interference algorithm based on iteration thresholding that the present invention proposes realizes, can adaptive setting interference detection threshold on algorithm, there is good dynamic disturbance and suppress ability.Realizing technical employing high-frequency clock realization reading data, judgement and inhibition, avoid, because repeatedly adjudicating and need to take the storage of hardware resource to middle process data, taking full advantage of the technology that the FPGA time exchanges resource for, greatly reduced the consumption to hardware resource.

Brief description of the drawings

Fig. 1 is the FPGA realization flow figure of the anti-interference algorithm based on iteration thresholding;

Fig. 2 disturbs to suppress and judging module flow chart;

Fig. 3 is frequency spectrum and the correlation schematic diagram that does not add the spread-spectrum signal while interference;

Fig. 4 is frequency spectrum and the correlation schematic diagram that adds the spread-spectrum signal after interference;

Fig. 5 is thresholding iterative process Modelsim analogous diagram;

Fig. 6 is frequency spectrum and the correlation schematic diagram of the spread-spectrum signal after anti-interference;

Fig. 7 is the RTL figure that FPGA realizes.

Embodiment

Below in conjunction with drawings and Examples, the present invention is further described.

The present invention proposes a kind of FPGA based on the anti-interference algorithm of iterative frequency-domain and realizes technology.In the algorithmic derivation of adaptive threshold, make improvement, can greatly reduce the consumption of storage resources.In its nucleus module (disturb identification with suppress module), adopt ping-pong operation to receive data, prevent data from overflow processing, and use high-frequency clock to complete that RAM data read and follow-up thresholding iterative computation and interference decision operation.

(I) first moment iteration threshold algorithm is theoretical derives:

Under glitch-free condition, signal can be expressed as S (k)+N (k), and wherein S (k) represents useful signal, and N (k) represents noise signal.After N point DFT conversion, becoming S (n)+N (n), is a narrowband Gaussian signal.The envelope of S (n)+N (n) | S (n)+N (n) | Rayleigh distributed, and envelope square | S (n)+N (n) | ²obeys index distribution.A lot of documents are all to start to derive from the probability distribution of envelope square, provide iteration thresholding, and the present invention is from its envelope | S (n)+N (n) | distribution situation derive.

Suppose signal | S (n)+N (n) | the rayleigh distributed that obedience parameter is σ, its desired value is probability density function is choose first moment threshold value wherein thresholding optimized coefficients K=1,2,3,4,5.| S (n)+N (n) | the probability of < TH

$P\left(\right|S\left(n\right)+N\left(n\right)|<\mathrm{TH})={\&Integral;}_0^{\mathrm{TH}}\frac{\mathrm{xexp}\left(\frac{-x^2}{2{\mathrm{\&sigma;}}^2}\right)}{{\mathrm{\&sigma;}}^2}\mathrm{dx}=1-\exp \left(\frac{-x^2}{2{\mathrm{\&sigma;}}^2}\right){|}_{x=\mathrm{TH}}$

Can obtain the probability of different K values, as shown in the table:

The probability distribution situation of table 1 different K values

K=1	K=2	K=3	K=4	K=5
					0.5441	0.9568	0.9991	1.0000	1.0000

The present invention finally chooses K=4, can ensure that useful signal can all pass through, and the parameter of simultaneously selecting is applicable to hardware and realizes, and multiply operation only can realize with displacement.

When DFT counts (N>256) when more, desired value can use the average statistical of signal to substitute, $\frac{1}{N}\underset{n=1}{\overset{n=N}{\mathrm{\&Sigma;}}}|S\left(n\right)+N\left(n\right)|=\mathrm{\&sigma;}\sqrt{\frac{\mathrm{\&pi;}}{2}},$ Thresholding is chosen work and is completed.

Adaptive threshold is the average statistical by repeatedly calculating signal, with threshold value corresponding to adaptively changing, makes signal pass through the judgement of iteration thresholding, reaches and disturbs the effect suppressing.Concrete grammar can, referring to performing step below, repeat no more here.

(II) a kind of FPGA of the anti-interference algorithm based on iteration thresholding realizes, and as shown in Figure 1, characterization step is as follows for principle:

(1) AD is sampled data that obtain are divided into two-way, and 1/2 window length delay (the present invention postpones 256 points) is carried out on a road, and two paths of data is input to respectively to windowing module.

(2) windowing module is that the data of input are carried out windowing operation, and window function adopts broad sense hamming window, and window length is 512 points, adopts the quantification of 8 bit data bit wides.After windowing has operated, data input FFT module.

(3) using a degree of depth in FFT module is L(L=512) the RAM data of checking input store, reading out data is transported to FFT core afterwards, carries out FFT computing.FFT is set to flowing water type base 2 mode of operations, and operating frequency is f _in, the output of its computing has real part Re and imaginary part Im two parts, in the present invention, this two paths of signals and Qi Mo value R is merged into a road signal according to senior middle school's low level, and { R}, is transported to and disturbs identification and suppress module for Re, Im.

(4) disturbing identification is Key Implementation part of the present invention with suppressing module, and as shown in Figure 2, detailed process is as follows for its flow process:

A. setting up two degree of depth is such as L=512 of L() two-port RAM core RAM1 and RAM2, RAM1 work is selected in data input selection unit, the data of FFT output are with clock f _instore in RAM1, calculate L point cumulative sum SUM and the threshold value TH of mould value R in stored data simultaneously ₁.

B. after RAM1 is filled with, data input cell is selected RAM2 work, and the data of FFT output are deposited in RAM2, calculates L point cumulative sum SUM and the threshold value TH of stored data mould value R in repeating step 1 simultaneously ₁work.

C. in the process of RAM2 data storage, to the data in RAM1 with clock f _sread.F _scan determine according to required iterations, for example iterations is 3 times, f _s=3*f _in.Can obtain, can read 3 times the data in RAM1 in this following period of time of RAM2 data storage.A bit wide and RAM1(RAM2 are set) flag register (for example [511:0] flag) that the degree of depth is identical, in the process that RAM1 first pass is read, will in the data that read, represent a part of R of mould value _j(j=0,1 ... 511) and TH ₁compare, if be greater than TH ₁the corresponding position of flag register puts 1, i.e. flag[j]=1, SUM=SUM-(R _j-TH ₁).Otherwise flag[j]=0, SUM remains unchanged.Read the complete moment at first pass, calculate thresholding TH by up-to-date SUM ₂, start RAM1 to read for second time.By the data R reading _jwith TH ₂relatively, if R _jbe greater than thresholding TH ₂, now check whether the relevant position of flag is 1, if 1, flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts relevant position 1, SUM=SUM-(R _j-TH ₂).If R _jbe less than thresholding TH ₂, flag corresponding positions and SUM remain unchanged.Read the complete moment at second time, calculate thresholding TH according to up-to-date SUM value ₃, start the 3rd time read.If the data R reading _jbe greater than TH ₃, by the real part Re reading _jbe set to TH ₃, imaginary part Im _jbe set to 0 output, i.e. Re _j=TH ₃, Im _j=0; Otherwise by the real part Re reading _jwith imaginary part Im _jdata are in statu quo exported.

D. in the time that the data decision of RAM1 is complete, the data in RAM2 are also stored end, and the now work to the Data duplication step 3 in RAM2, starts to store new data to RAM1.

(5) will disturb the data of identification and the output of inhibition module with clock f _sbe input to IFFT module, store by two-port RAM in this module and with clock f _inread, complete the conversion of data rate.The data input IFFT core reading, carries out inverse transformation output.

(6) output of two-way IFFT module is merged and flows to external interface, anti-interference end-of-job.

Now in conjunction with certain actual wireless band spread receiver, the present invention is described further:

The hardware platform that algorithm is realized: the fpga chip of Xilinx x5v1x155 model.

Exploitation and simulated environment: ISE10.1 and Modelsim SE6.5c.

The spread-spectrum signal bandwidth using is 2MHz, and interference signal is 0.2MHz, and jamming-to-signal ratio is 45dB.

The global clock of receiver system is 32MHz and 96MHz.Specific implementation adopts three iteration.The data bit width of AD input is 4.The IP kernel that carries out FFT and IFFT computing all adopts fixing bit wide (scaled) pattern, and inputting bit wide is 8, and the real part of output and imaginary part bit wide are 8.RAM core in realization all adopts 512 storage depth, and wherein in FFT module, RAM core bit wide is 4; Disturb suppress and judging module in RAM bit wide be 25, the real part data of most-significant byte storage FFT output, in 8 imaginary data that storage FFT exports, store mould values for low 9; RAM core bit wide in IFFT module is 20, high 12 storage real part data, least-significant byte storage imaginary data.

The concrete steps that realize are as follows:

(1) by under change to intermediate frequency the satellite-signal AD data that obtain of sampling be output as two-way, 1/2 window length delay (the present invention postpones 256 points) is carried out on a road, and two paths of data is input to respectively to windowing module.

(2) windowing module is that the data of input are carried out windowing operation, and window function adopts broad sense hamming window, and window length is 512 points, adopts the quantification of 8 bit data bit wides.After windowing has operated, data input FFT module.

(3) RAM that is 512 in degree of depth of FFT module use checks the data of input and stores, and reading out data is transported to FFT core afterwards, carries out FFT computing.FFT is set to Pipelined, Streaming I/O pattern, and its operating frequency is f _in=32MHz(f _inidentical with AD sampling clock), the output of its computing has real part Re and imaginary part Im two parts, the mould value jointly calculating by these two parts with by real part imaginary part in the present invention merge into a road signal according to senior middle school's low level, { R}, is transported to and disturbs identification and suppress module for Re, Im.

(4) each interference identification is as follows with the course of work that suppresses module:

A. set up two-port RAM core RAM1 and RAM2 that two degree of depth are 512, RAM1 work is selected in data input selection unit, and the data of FFT output are with clock f _in=32MHz stores in RAM1, calculates 512 cumulative sums of mould value R in stored data simultaneously $\mathrm{SUM}(\mathrm{SUM}=\underset{j=1}{\overset{512}{\mathrm{\&Sigma;}}}{R}_j)$ And threshold value ${\mathrm{TH}}_1({\mathrm{TH}}_1=4*\frac{\mathrm{SUM}}{512}).$

B. after RAM1 is filled with, RAM2 work is selected in data input selection unit, and the data of FFT output are deposited in RAM2, calculates 512 cumulative sum SUM and the threshold value TH of stored data mould value R in repeating step a simultaneously ₁work.

C. in the process of RAM2 data storage, to the data in RAM1 with clock f _s=3*32=96MHz reads.The flag register that a bit wide is 512 is set, in the process that RAM1 first pass is read, will in the data that read, represents a part of R of mould value _j, j=1,2,3...512, with TH ₁compare, if be greater than TH ₁the corresponding position of flag register puts 1, i.e. flag[j-1]=1 (because the bit wide of flag is since 0, therefore need to use j-1 to represent the relevant position of flag bit wide), SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged.Read the complete moment at first pass, calculate thresholding TH by up-to-date SUM ₂(computing formula is as shown in step a), starts RAM1 to read for second time.By the data R reading _jwith TH ₂relatively, if R _jbe greater than thresholding TH ₂, now check whether the relevant position of flag is 1, if 1, flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jbe less than thresholding TH ₂, flag corresponding positions and SUM remain unchanged.Read the complete moment at second time, calculate thresholding TH according to up-to-date SUM value ₃, start the 3rd time read.If the data R now reading _jbe greater than TH ₃, by the real part Re reading _jbe set to TH ₃, imaginary part Im _jbe set to 0 output, i.e. Re _j=TH ₃, Im _j=0; Otherwise by the real part Re reading _jwith imaginary part Im _jdata are in statu quo exported

D. in the time that the data decision of RAM1 is complete, the data in RAM2 are also stored end, and now the work to the Data duplication step c in RAM2, starts to store new data to RAM1.

(5) by the data of the inhibition of disturbing and judging module output with clock f _s=96MHz is input to IFFT module, stores and with clock f in this module by two-port RAM _in=32MHz reduction of speed rate reads, and completes the conversion of data rate.The data input IFFT core reading, carries out inverse transformation output.

(6) output of two-way IFFT module is directly added to merging, flows to external interface, anti-interference end-of-job.

According to the characteristic of spread-spectrum signal, can judge the degree that interference signal is suppressed by the correlation peak of spread-spectrum signal and local code signal.

The frequency spectrum of the spread-spectrum signal while not adding interference and correlation are as shown in Figure 3.

Add the frequency spectrum of spread-spectrum signal after the interference signal that bandwidth 2MHz jamming-to-signal ratio is 40dB and correlation as shown in Figure 4.

When FPGA realizes, the Modelsim analogous diagram of thresholding iterative process as shown in Figure 5.

Threshold1 in signal shown in Fig. 5, threshold2, threshold3 distinguishes corresponding iteration for the first time, threshold value for the second time and for the third time.

From overall procedure, every after the judgement of 512 data, each threshold value (as threshold1) can be upgraded according to the statistics of the data of new input, and threshold value can be according to according to the difference of input data and dynamic change.From the once complete judging process of 512 data, through sentencing for the first time iteration, threshold value drops to threshold2 by threshold1, through iteration for the second time, threshold value drops to threshold3 by threshold2, in the process of iteration for the third time, by data decision output, complete the interference judgement work of 512 data.Specific implementation conforms to theory.

The interference that signal is realized by FPGA is suppressed after module, and the frequency spectrum of spread-spectrum signal and correlation are as shown in Figure 6.

According to result shown in Fig. 4, Fig. 5 and Fig. 6, can find out after adding interference signal and can not get obvious correlation peak, receiver cannot be worked.Through after disturbing and suppressing, correlation peak is obvious, and position is with not add interference signal identical, and interference suppresses successfully.

Through ISE, after comprehensive and placement-and-routing, the RTL of FPGA realization schemes as shown in Figure 7.

Shown in concrete resource consumption information slip 2.

Table 2 resource consumption figure

Claims (1)

1. a FPGA implementation method for the anti-interference algorithm of iterative frequency-domain, is characterized in that comprising the steps:

(1) by under change to intermediate frequency satellite-signal carry out AD sampling, the data that obtain are output as two-way, 1/2 window length delay is carried out on a road, and two paths of data is input to respectively to windowing module;

(2) windowing module is that the data of input are carried out windowing operation, and window function adopts broad sense hamming window, and window length is L, adopts the quantification of 8 bit data bit wides; After windowing has operated, data input FFT module;

(3) RAM that is L in degree of depth of FFT module use checks the data of input and stores, and reading out data is transported to FFT core afterwards, carries out FFT computing; FFT is set to Pipelined, Streaming I/O pattern, and operating frequency is f _in, f _inidentical with AD sampling clock, the output of its computing has real part Re and imaginary part Im two parts, and the mould value R jointly calculating by these two parts with by real part imaginary part in the present invention merges into one dimension matrix according to senior middle school's low level, i.e. { Re, Im, R}, is transported to and disturbs identification and suppress module;

(4) each interference identification is as follows with the course of work that suppresses module:

A. set up two-port RAM core RAM1 and RAM2 that two degree of depth are L=512, RAM1 work is selected in data input selection unit, and the data of FFT output are with clock f _instore in RAM1, calculate the L point cumulative sum of mould value R in stored data simultaneously and threshold value k is thresholding optimized coefficients;

B. after RAM1 is filled with, RAM2 work is selected in data input selection unit, and the data of FFT output are deposited in RAM2, calculates L point cumulative sum SUM and the threshold value TH of stored data mould value R in repeating step a simultaneously ₁work;

C. in the process of RAM2 data storage, to the data in RAM1 with clock f _sread f _s=N*f _in, N is iterations; Can obtain, can read N time to the data in RAM1 in this following period of time of RAM2 data storage; A flag register that bit wide is identical with the RAM1 degree of depth is set, in the process that RAM1 first pass is read, will in the data that read, represents a part of R of mould value _jwith TH ₁compare, j=1,2,3...L, if be greater than TH ₁the corresponding position j-i of flag register puts 1, i.e. flag[j-1]=1, SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged; Read the complete moment at first pass, calculate thresholding TH by up-to-date SUM ₂, start RAM1 to read for second time; By the data R reading _jwith TH ₂relatively, if R _jbe greater than thresholding TH ₂, now check whether the relevant position of flag is 1, if 1, flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jbe less than thresholding TH ₂, flag corresponding positions and SUM remain unchanged; Read the complete moment at second time, calculate thresholding TH according to up-to-date SUM value ₃, start the 3rd time read; The 3rd time to N-1 all over reading done operation and to read done operation for second time identical, a to the last reading out data, N, all over reading out data, can obtain threshold T H by N-1 time read operation _nif, the data R now reading _jbe greater than TH _n, by the real part Re reading _jbe set to TH _n, imaginary part Im _jbe set to 0 output, i.e. Re _j=TH _n, Im _j=0; Otherwise by the real part Re reading _jwith imaginary part Im _jdata are in statu quo exported;

D. in the time that the data decision of RAM1 is complete, the data in RAM2 are also stored end, and now the work to the Data duplication step c in RAM2, starts to store new data to RAM1;

(5) will disturb the data of identification and the output of inhibition module with clock f _sbe input to IFFT module, store by two-port RAM in this module and with clock f _inread, complete the conversion of data rate; The data input IFFT core reading, carries out inverse transformation output;

(6) output of two-way IFFT module is directly added to merging, flows to external interface, anti-interference end-of-job.