CN103188042B - A kind of matching process of IP packet and coupling accelerator - Google Patents
A kind of matching process of IP packet and coupling accelerator Download PDFInfo
- Publication number
- CN103188042B CN103188042B CN201110459754.XA CN201110459754A CN103188042B CN 103188042 B CN103188042 B CN 103188042B CN 201110459754 A CN201110459754 A CN 201110459754A CN 103188042 B CN103188042 B CN 103188042B
- Authority
- CN
- China
- Prior art keywords
- packet
- cache blocks
- header parameter
- packet filter
- preserved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 230000008569 process Effects 0.000 title claims abstract description 43
- 230000008878 coupling Effects 0.000 title claims abstract description 41
- 238000010168 coupling process Methods 0.000 title claims abstract description 41
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 41
- 230000001960 triggered effect Effects 0.000 claims description 19
- 239000000284 extract Substances 0.000 claims description 11
- 230000013011 mating Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- 238000010295 mobile communication Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012772 sequence design Methods 0.000 description 2
- 102100027266 Ubiquitin-like protein ISG15 Human genes 0.000 description 1
- 101710087750 Ubiquitin-like protein ISG15 Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001314 paroxysmal effect Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The embodiment of the invention discloses a kind of matching process and coupling accelerator of IP packet, for improving the matching efficiency of IP packet and packet filter.In the method that the embodiment of the present invention provides, i-th packet filter is after the header parameter value of having mated the IP packet preserved in a kth cache blocks, just can mate the header parameter value of the IP packet preserved in (k+1) individual cache blocks again, and do not need that m packet filter in by the time matching module is all data packet matched with the IP that preserves in a kth cache blocks completely to carry out afterwards again, that is, in the embodiment of the present invention, each packet filter in matching module can parallel processing to the coupling of the IP packet preserved in each cache blocks in IP header parameter buffer, the matching efficiency of IP packet and packet filter can be improved.
Description
Technical field
The present invention relates to mobile communication system field, particularly relate to matching process and the coupling accelerator of a kind of IP packet in traffic flow template.
Background technology
Along with wireless communication technology and network interconnection agreement (IP, InternetProtocol) the combining closely of technology, mobile communications network is from global system for mobile communications (GSM, GlobalSystemofMobilecommunication) Circuit Switching Network of system develops into the packet switching network of GPRS (GPRS, GeneralPacketRadioService).In order to meet the new demand of user to high speed wireless data business, GPRS experiences enhanced data rates for gsm evolution technology (EDGE, EnhancedDataRateforGSMEvolution) to G mobile communication (3G, the evolution of 3rd-generation)/universal mobile telecommunications system (UMTS, UniversalMobileTelecommunicationsSystem).
Although 3G mobile communication system has had significant improvement compared with 2G, but still cannot meet the requirement of user, be proposed again evolution UMTS technology and evolved packet system (EPS further, EvolvedPacketSystem), target be in real time and non-real-time service a kind of unified architecture is provided, and provide the packet radio access technology of high data rate, low time delay and optimization for user.
This target is by two important component parts of EPS: wave point Long Term Evolution (LTE, LongTermEvolution) and system architecture evolution (SAE, SystemArchitectureEvolution) have been come.Simultaneously for service quality (QoS, QualityofService), for Future Data business, there is paroxysmal feature, introduce the concept of EPS dedicated bearer and default bearing, effectively reduce the setup delay of service bearer, really achieve " always online " of user.Default bearing is that a kind meets the data of acquiescence QoS and user's carrying of signaling.Dedicated bearer is the SAE carrying used some specific transactions.Generally special SAE carrying QoS is higher than the requirement of acquiescence QoS.Dedicated bearer is at subscriber equipment (UE, UserEquipment) traffic flow template (TFT that association one is up, TrafficFlowTemplate), at public data network gateway (PDNGW, PublicDataNetworkGateway) TFT that association one is descending, comprise the packet filter (PF, PacketPilter) of business data flow in TFT, only have IP packet and PF the match is successful and could transmit.
In EPS, all business data flows in same carrying ensure obtaining same QoS, and different bearer types provides different QoS to ensure.An EPS carries the logical circuit can regarded as between subscriber equipment and public data network gateway (PDNGW, PublicDataNetworkGateway), the corresponding EPS carrying of each grouping IP filter (PF) in traffic flow template.By the PF corresponding with carrying, the business data flow under PDN is carried out classifying and is distributed in different EPS carryings and transmit.
In EPS, APN (APN, AccessPointName) connects may exist multiple dedicated bearer (containing multiple PF).If the IP data packet header parameter received is mated entirely with the property value of combinations of attributes effective in certain PF, then the match is successful for IP packet and PF, and the radio bearer that IP packet can map at this PF simultaneously transmits.
The software simulating matching process of existing IP packet and PF, as shown in Figure 1, in the Ti moment, first extract an IP packet (being IP1 Fig. 1) from IP traffic, then from this IP packet, header parameter is extracted and PF carries out matching ratio comparatively one by one from PF0 to PF255 according to the priority, the match is successful to be continued until IP packet and wherein certain PF, again by this IP packet and EPS bearing identification (EBI, EPSBearerIdentity) protocol stack process is sent to after binding, then extract next IP packet (IP2) again in (Ti+1) moment and carry out similar matching treatment, that is, when the match is successful for a upper IP packet and PF, next IP wraps and must wait for, as shown in Figure 1, when IP1 is when mating, IP2 must wait for, only have IP2 after the match is successful as IP1 and PF could start from the highest PF0 to PF255 of priority one by one coupling, the process of a serial that Here it is, and for requiring now more and more higher speed uplink, the match time that the implementation procedure of this serial needs is longer.
Summary of the invention
Embodiments provide a kind of matching process and coupling accelerator of IP packet, for improving the matching efficiency of IP packet and packet filter.
On the one hand, the matching process of the IP packet that the embodiment of the present invention provides, comprising:
IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from n IP packet of IP traffic, and be then saved to respectively in x cache blocks of described IP header parameter buffer, wherein n, x are positive integers;
The header parameter value of the match attribute value of described i-th packet filter with the IP packet preserved in a described kth cache blocks is mated by i-th packet filter of matching module, wherein, described matching module comprises m packet filter, wherein, 1≤i < (i+1) < m, i, k, m are positive integers;
If the match is successful for the header parameter value of the IP packet preserved in the match attribute value of described i-th packet filter and a kth cache blocks, the evolved packet system of described i-th packet filter carrying index EBI writes in the structure of IP packet corresponding to a described kth cache blocks by main control module, described main control module by the structure address of IP packet of preserving in a described kth cache blocks stored in transmit buffer;
If it fails to match for the header parameter value of the IP packet preserved in the match attribute value of described i-th packet filter and a described kth cache blocks, the header parameter value of the match attribute value of described (i+1) individual packet filter with the IP packet preserved in a described kth cache blocks is mated by (i+1) individual packet filter of described matching module;
After the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks by i-th packet filter of described matching module, the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by described i-th packet filter.
On the other hand, the coupling accelerator that the embodiment of the present invention provides, comprising:
IP header parameter buffer, main control module, matching module, transmit buffer, wherein,
Described IP header parameter buffer comprises: x cache blocks, and wherein x is positive integer;
Described IP header parameter buffer, for extracting header parameter value and the structure address of each IP packet from n IP packet of IP traffic respectively, then be saved to respectively in x cache blocks of described IP header parameter buffer, wherein, n is positive integer;
Described matching module comprises m packet filter, wherein, 1≤i < (i+1) < m, i, m are positive integers;
I-th packet filter of described matching module, for the header parameter value of the match attribute value of described i-th packet filter with the IP packet preserved in a kth cache blocks being mated, wherein, k is positive integer;
Described main control module, if for the header parameter value of IP packet of preserving in the match attribute value of described i-th packet filter and a described kth cache blocks, the match is successful, the evolved packet system of described i-th packet filter carrying index EBI is write in the structure of IP packet corresponding to a described kth cache blocks, by the structure address of the IP packet in a described kth cache blocks stored in described transmit buffer;
Described transmit buffer, for preserve described main control module stored in a kth cache blocks in the structure address of IP packet of preserving;
(i+1) individual packet filter of described matching module, if for the header parameter value of IP packet of preserving in the match attribute value of described i-th packet filter and a described kth cache blocks, it fails to match, the header parameter value of the match attribute value of described (i+1) individual packet filter with the IP packet preserved in a described kth cache blocks mated;
I-th packet filter of described matching module, after the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks, the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages:
In embodiments of the present invention, first IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from the n of IP traffic IP packet, then be saved in x cache blocks in IP header parameter buffer respectively, the header parameter value of the match attribute value of the i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter of matching module, then the match attribute value of i-th packet filter is entered to mate with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter, visible, in embodiments of the present invention, i-th packet filter is after the header parameter value of having mated the IP packet preserved in a kth cache blocks, just can mate the header parameter value of the IP packet preserved in (k+1) individual cache blocks again, and do not need that m packet filter in by the time matching module is all data packet matched with the IP that preserves in a kth cache blocks completely to carry out afterwards again, that is, in the embodiment of the present invention, each packet filter in matching module can parallel processing to the coupling of the IP packet preserved in each cache blocks in IP header parameter buffer, the matching efficiency of IP packet and packet filter can be improved.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, to those skilled in the art, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of the matching process of IP packet and the PF existed in prior art;
The schematic diagram of the matching process of the IP packet that Fig. 2 provides for the embodiment of the present invention;
A kind of composition structural representation mating accelerator that Fig. 3 provides for the embodiment of the present invention;
The composition structural representation of the another kind coupling accelerator that Fig. 4 provides for the embodiment of the present invention;
The schematic diagram that an IP packet carried out to matching treatment of Fig. 5 for providing in the embodiment of the present invention;
Multiple IP Data-Links that Fig. 6 (a) provides for the embodiment of the present invention carry out the schematic diagram of matching treatment in the Ti moment;
Multiple IP Data-Links that Fig. 6 (b) provides for the embodiment of the present invention carry out the schematic diagram of matching treatment in the Ti+1 moment;
Multiple IP Data-Links that Fig. 6 (c) provides for the embodiment of the present invention carry out the schematic diagram of matching treatment in the Ti+2 moment.
Embodiment
Embodiments provide a kind of matching process and coupling accelerator of IP packet, for improving the matching efficiency of IP packet and packet filter.
For making goal of the invention of the present invention, feature, advantage can be more obvious and understandable, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, the embodiments described below are only the present invention's part embodiments, and not all embodiments.Based on the embodiment in the present invention, the every other embodiment that those skilled in the art obtains, all belongs to the scope of protection of the invention.
The matching process of the IP packet that the embodiment of the present invention provides, as shown in Figure 2, comprising:
201, IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from n IP packet of IP traffic, is then saved to respectively in x cache blocks of IP header parameter buffer.
Wherein n, x is positive integer, n refers to the number of the IP packet comprised in IP traffic, x refers to the number of the cache blocks comprised in IP header parameter buffer, it should be noted that, the n occurred in the embodiment of the present invention, what the m of x and follow-up appearance referred to is all quantity, and can be the applied environment according to reality and the quantitative value changed, n, x, m not refers to n, x, of these letters of m itself, can certainly replace with other arbitrary letter or numeral, just show packet herein, cache blocks, the number of packet filter, herein for illustrative purposes only, do not limit.
It should be noted that, in the embodiment of the present invention, n and x does not have corresponding relation, n is likely less than x, n is likely greater than x, not necessarily all cache blocks in IP header parameter buffer are filled up when initially starting buffer memory IP packet and go coupling again, likely buffer memory packet or several packet just start the process of coupling, do not limit herein for illustrative purposes only.
In embodiments of the present invention, mate accelerator to comprise: IP header parameter buffer, main control module, matching module, transmit buffer, wherein, IP header parameter buffer comprises: x cache blocks, and matching module comprises m packet filter.Explanation about x, m refers to aforementioned description, repeats no more herein.
In embodiments of the present invention, IP header parameter buffer, for depositing header parameter value and the structure address of IP packet, is supplied to matching module and carries out PF coupling.It should be noted that, the IP header parameter buffer now described includes x cache blocks, a kth cache blocks and (k+1) individual cache blocks is only described in subsequent step, workflow and implementation just in order to each cache blocks clearly can be described, certain IP header parameter buffer also can comprise multiple cache blocks, but the implementation of multiple cache blocks remains the workflow of a kth cache blocks that the repetition embodiment of the present invention provides and (k+1) cache blocks, is still just included among the embodiment of the present invention.In actual applications, IP header parameter buffer can comprise x cache blocks, x is positive integer, because IP header parameter buffer is when carrying out IP header parameter and extracting, matching module in the embodiment of the present invention also carries out matching treatment at the same time, the speed extracted when IP header parameter is less than PF rate matched in matching module, the situation that buffer memory is not enough would not be there is in IP header parameter buffer, in order to reduce hardware resource cost, cache blocks herein in IP header parameter buffer is specifically as follows 16, namely the cache blocks that IP header parameter buffer comprises is the 1st cache blocks, 2nd cache blocks, 16th cache blocks.
In embodiments of the present invention, IP traffic comprises n IP packet, but usually can comprise multiple IP packet in an IP traffic (also can be an IP Data-Link) in actual applications, it should be noted that, the IP traffic now described comprises n IP packet just in order to clearly describe processed workflow and the implementation of each IP packet, certain IP traffic also can comprise multiple IP packet, but the processed flow process to the IP packet preserved in the IP packet preserved in a kth cache blocks and (k+1) individual cache blocks that the repetition embodiment of the present invention provides is remained to the implementation of multiple IP packet, still just be included among the embodiment of the present invention.Header parameter value and the IP packet structure body address of IP packet is included in each IP packet, a such as IP packet just includes an IP data packet header parameter value and an IP packet structure body address, and the 2nd IP packet just includes the 2nd IP data packet header parameter value and the 2nd IP packet structure body address.
In embodiments of the present invention, IP header parameter buffer extracts header parameter value and structure address respectively and is saved to x cache blocks of IP header parameter buffer respectively from n IP packet of IP traffic, if IP header parameter buffer includes multiple cache blocks, multiple IP data packet header parameter value and structure address can be kept in idle cache blocks herein.
202, the header parameter value of the match attribute value of i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter of matching module, if the match is successful, triggered step 203 performs, if mate unsuccessful, triggered step 204 performs.
Wherein, matching module comprises m packet filter, and wherein, 1≤i < (i+1) < m, i, k, m are positive integers.I, k, (i+1) be all positive integer, i, (i+1) satisfy condition 1≤i < (i+1) < m, wherein i refers to i-th packet filter in matching module, (i+1) (i+1) individual packet filter in matching module is referred to, k refers to a kth cache blocks in IP header parameter buffer, it should be noted that, the i occurred in the embodiment of the present invention, k, and (k+1) of follow-up appearance refer to is all some packet filters or cache blocks (i+1), if such as i value is 3, what then refer to is the 3rd packet filter in matching module, k value is 1, that then refer to is the 1st cache blocks, in addition i in IP header parameter register, k, (i+1) and (k+1) of follow-up appearance can be applied environment according to reality and the quantitative value changed, i, k, (i+1), (k+1) not i is referred to, k, (i+1), (k+1) these letters is own, can certainly replace, just show which packet filter herein with other arbitrary letter or numeral, which cache blocks, does not limit herein for illustrative purposes only.
In embodiments of the present invention, main control module is used for the control to IP header parameter buffer, matching module, transmit buffer, whether enable such as main control module control matching module, IP header parameter buffer, transmit buffer, only when enable, its excess-three module could normal work.
In embodiments of the present invention, matching module comprises m packet filter, the implementation method of i-th packet filter is only described in step 202, it should be noted that, i-th packet filter in the matching module now described is just in order to can the workflow of a packet filter clearly in profile matching module and implementation, certain matching module also can comprise multiple packet filter, but the multiple points of implementations making filter remain the workflow of i-th packet filter that the repetition embodiment of the present invention provides, still just be included among the embodiment of the present invention.
In embodiments of the present invention, matching module is main functional module, matching ratio is carried out comparatively for IP packet and network being joined the effective packet filter given, and EPS bearing identification (EBI, EPSBearerIdentity) corresponding for the packet filter that the match is successful is write in the structure of IP packet.Wherein, the matching principle of IP packet can mate according to priority is high to Low, therefore the design of packet filtering device also can be mated according to the order high to Low from priority.
It should be noted that, in the invention process, priority index (the EPI of i-th packet filter, EvaluationPrecedenceIndex) can higher than the EPI of (i+1) individual packet filter, each packet filter is identified by unique packet filter identifier (PFID), each packet filter includes a priority index simultaneously, the match attribute principle that the packet filter that each EPI is different adopts may be different, the value of EPI is only under the same direction (specifically referring to up direction or down direction) of all EPS carryings using identical ip addresses and APN, the priority span of priority index is 0 ~ 255, wherein 0 representative is that priority is the highest, 255 representative be that priority is minimum.
In embodiments of the present invention, the header parameter value of the match attribute value of i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter, wherein, match attribute value comprises at least one of following property value: far-end address and subnet mask property value, Security Parameter Index property value, flow label property value, local port scope attribute value, remote port scope attribute value, Internet protocol the 4th edition (IPv4, InternetProtocolversion4) COS or Internet protocol sixth version (IPv6 in, InternetProtocolversion6) grade of service property value in, next property value in protocol number or IPV6 in IPV4.
All packet filters and EPS can be carried by EBI and mutually map, each EPS carries corresponding EBI parameter and TFT.Corresponding packet filter can not had in each TFT, but PDN can only have at most in a TFT in connecting and not have packet filter, if that is default bearing does not have packet filter so PDN connect all must packet filter in corresponding all coupling accelerators.
In view of packet filter in the embodiment of the present invention is to the matching process of IP packet, the advantage increasing IP header parameter buffer is:
(1), the header parameter value of other IP packets in IP traffic can be extracted at matching module while Match IP packet, thus improve matching efficiency;
(2), can reduce the hardware spending of matching module and matching ratio compared with time IP data packet header parameter copy number of times, were it not for the IP header parameter buffer that the embodiment of the present invention proposes, need in each PF so in matching module to open up another memory space for depositing IP data packet header parameter for each matching ratio comparatively, each like this PF needs to increase large space same with property value register again, for 256 PF, whole matching module just needs extra increase by 256 registers, adds hardware spending; Secondly, when IP packet in previous PF, fail that the match is successful need be sent to next PF mate, there are two kinds of methods, one again from IP packet, takes out IP data packet header parameter, but because relate to the parameter of two not fixed positions in these header parameter, so the expense of again peeking is larger than copying from the register of the header parameter of previous PF storing IP packet; Another kind copies from a upper PF, considers limiting case, then need copy 256 times.More both can reduce hardware spending also can reduce copy number of times so the match attribute value in the IP header parameter buffer directly using the embodiment of the present invention to provide and PF carries out matching ratio, improve matching efficiency.
It should be noted that in addition, for a kth cache blocks and i-th packet filter in step 202, the effective cache blocks all referred to and the packet filter of enable free time (namely can carry out the cache blocks read and the packet filter that can carry out mating), comprise the packet filter that (i+1) individual packet filter of occurring in subsequent step and (k+1) individual cache blocks also refer to effective cache blocks and enable free time, also be the packet filter for the enable free time, (i+1) individual packet filter might not be that packet filter adjacent with i-th packet filter, same (k+1) individual cache blocks also might not be that cache blocks adjacent with a kth cache blocks.In brief, for cache blocks: idle expression can write header parameter value and the structure address of IP packet inside, effectively represent that the header parameter value that can read in cache blocks is mated with PF; For matching module, the enable free time represents can mate with the header parameter value in next valid cache block.
If the match is successful for the header parameter value of the IP packet preserved in the match attribute value of 203 i-th packet filters and a kth cache blocks, the evolved packet system of i-th packet filter carrying index EBI writes in the structure of IP packet corresponding to a kth cache blocks by main control module, main control module by the structure address of IP packet of preserving in a kth cache blocks stored in transmit buffer.
In embodiments of the present invention, if the match is successful for the header parameter value of the IP packet preserved in the match attribute value of i-th packet filter and a kth cache blocks, the EBI of i-th packet filter writes in the structure of the IP packet preserved in a kth cache blocks by main control module, main control module by the structure address of IP packet of preserving in a kth cache blocks stored in transmit buffer, wherein, transmit buffer is for depositing the IP packet structure body address after the match is successful, the design of transmit buffer should be noted: it is excessive that buffer space does not need to open up, to reduce hardware spending.
It should be noted that, in embodiments of the present invention, one must be comprised in order to store the member of corresponding EBI value in IP packet structure body, as IP packet and PF, the match is successful or unsuccessfully need corresponding EBI value to write wherein, namely the EBI of packet filter is write in member corresponding to IP packet structure body when the match is successful, all packet filters all data packet matched with IP failed time the EBI in main control module is write in member corresponding to IP packet structure body.
It should be noted that, in actual applications, main control module by the structure address of IP packet of preserving in the kth cache blocks that the match is successful stored in after in transmit buffer, step can also be comprised: whether master control module judges meets preset down trigger condition, if meet, main control module triggered interrupts, protocol stack is exported in the structure address of the IP packet preserved in transmit buffer by transmit buffer, to make the structure address of protocol stack to IP packet process, if do not meet, main control module is triggered interrupts not.Such as, main control module is that transmit buffer arranges down trigger condition, when interrupting trigger condition and meeting, main control module triggered interrupts, protocol stack is exported in the IP packet structure body address of preserving in transmit buffer by transmit buffer, to meet in IP traffic the IP packet structure body address priority treatment that the match is successful.
In actual applications, the down trigger condition that main control module is preset specifically can comprise: the number of the IP packet structure body address of preserving in transmit buffer is not less than preset number; Or, meet the condition of idle triggered interrupts, wherein, the condition of idle triggered interrupts comprises: the number that in IP header parameter buffer, all cache blocks all m packet filters that are idle, matching module are all in the structure address of the IP packet preserved in enable idle condition, transmit buffer is greater than zero.
If it fails to match for the header parameter value of the IP packet preserved in the match attribute value of 204 i-th packet filters and a kth cache blocks, the header parameter value of the match attribute value of (i+1) individual packet filter with the IP packet preserved in a kth cache blocks is mated by (i+1) individual packet filter of matching module.
In embodiments of the present invention, when it fails to match for the header parameter value of the IP packet preserved in i-th packet filter and a kth cache blocks, continued to mate with the IP data packet header parameter value preserved in a kth cache blocks by (i+1) individual packet filter.This is a process constantly continuing to carry out, if containing multiple packet filter in matching module, then when it fails to match for previous packet filter, needs to proceed coupling by follow-up packet filter.
It should be noted that, in embodiments of the present invention, a kind of attainable situation is, after the match attribute value of (i+1) individual packet filter is mated with the header parameter value of the IP packet preserved in a kth cache blocks by (i+1) individual packet filter of matching module, can also comprise the steps:
As (i+1)=m, if it fails to match for the header parameter value of the IP packet preserved in the match attribute value of (i+1) individual packet filter and a kth cache blocks, evolved packet system carrying index EBI in main control module writes in the structure of IP packet corresponding to a kth cache blocks by main control module, main control module by the structure address of IP packet of preserving in a kth cache blocks stored in transmit buffer.
That is, if the m that matching module a comprises packet filter is when all it fails to match, then the EBI in main control module writes in the IP packet preserved in a kth cache blocks by main control module, main control module by the structure address of IP packet of preserving in a kth cache blocks stored in transmit buffer.
Below citing is described, in actual applications, the priority span of priority index is 0 ~ 255, matching module specifically can comprise 256 packet filter PF, according to PF priority sequence design from high to low, namely PF0 corresponds to the PF that priority is 0, PFk deposits and preferentially corresponds to the PF that priority is k, first mated by PF0, if it fails to match, mated by PF1, if it fails to match for PF1, continue to be mated by PF2, until mated by PF255, if it fails to match for PF255, then the EBI of main control module writes in the structure of the IP packet preserved in a kth cache blocks by main control module, main control module by the structure address of the IP packet in a kth cache blocks stored in transmit buffer.
205, after the match attribute value of i-th packet filter is mated with the header parameter value of the IP packet preserved in a kth cache blocks by i-th packet filter of matching module, the match attribute value of i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter.
In embodiments of the present invention, after the match attribute value of i-th packet filter is mated with the header parameter value of the IP packet preserved in a kth cache blocks by i-th packet filter of matching module, the match attribute value of i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter, due to i-th packet filter enable idle time just can proceed coupling work, and do not need m packet filter in by the time matching module all mated after just can mate, therefore the matching way that walks abreast can be realized, improve matching efficiency.
It should be noted that, in embodiments of the present invention, step 205 can also comprise the steps: before performing
(i+1) individual packet filter whether enable free time of master control module judges matching module, if so, main control module triggers (i+1) individual packet filter and performs the function of carrying out with the header parameter value of the IP packet preserved in a kth cache blocks mating.Namely, before (i+1) individual packet filter starts to mate, the state of master control module judges once (i+1) individual packet filter, if (i+1) individual packet filter is effective, main control module triggers (i+1) individual packet filter again to start to mate work.
It should be noted that, in the embodiment of the present invention, before the match attribute value of i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter of matching module, also comprise: in master control module judges IP header parameter buffer, whether (k+1) individual cache blocks is effective, if so, main control module triggers i-th packet filter and mates with the header parameter value of the IP packet preserved in (k+1) individual cache blocks.
In embodiments of the present invention, first IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from the n of IP traffic IP packet, then be saved in x cache blocks in IP header parameter buffer respectively, the header parameter value of the match attribute value of the i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter of matching module, then the match attribute value of i-th packet filter is entered to mate with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter, visible, in embodiments of the present invention, i-th packet filter is after the header parameter value of having mated the IP packet preserved in a kth cache blocks, just can mate the header parameter value of the IP packet preserved in (k+1) individual cache blocks again, and do not need that m packet filter in by the time matching module is all data packet matched with the IP that preserves in a kth cache blocks completely to carry out afterwards again, that is, in the embodiment of the present invention, each packet filter in matching module can parallel processing to the coupling of the IP packet preserved in each cache blocks in IP header parameter buffer, the matching efficiency of IP packet and packet filter can be improved.
Above embodiment describes the matching process of the IP packet that the embodiment of the present invention provides, next the device that method that the embodiment of the present invention provides is corresponding is introduced: coupling accelerator, as shown in Figure 3, a kind of coupling accelerator 300, comprise: IP header parameter buffer 301, main control module 302, matching module 303, transmit buffer 304, wherein
IP header parameter buffer 301 comprises: x cache blocks, and wherein x is positive integer;
IP header parameter buffer 301, for extracting header parameter value and the structure address of each IP packet from n IP packet of IP traffic respectively, then be saved to respectively in x cache blocks of described IP header parameter buffer, wherein, n is positive integer;
Matching module 303 comprises m packet filter, wherein, 1≤i < (i+1) < m, i, m are positive integers;
I-th packet filter 3031 of matching module, for the header parameter value of the match attribute value of i-th packet filter 3031 with the IP packet preserved in a kth cache blocks 3011 being mated, wherein, k is positive integer;
Main control module 302, if for the header parameter value of IP packet of preserving in the match attribute value of i-th packet filter 3031 and a kth cache blocks 3011, the match is successful, the evolved packet system of i-th packet filter 3031 carrying index EBI is write in the structure of the IP packet of a kth cache blocks 3011 correspondence, by the structure address of the IP packet in a kth cache blocks 3011 stored in transmit buffer 304;
Transmit buffer 304, for preserve main control module 302 stored in a kth cache blocks in the structure address of IP packet of preserving;
(i+1) individual packet filter 3032 of matching module, if for the header parameter value of IP packet of preserving in the match attribute value of i-th packet filter 3031 and a kth cache blocks, it fails to match, the match attribute value of individual to (i+1) packet filter 3032 mated with the IP data packet header parameter value preserved in a kth cache blocks;
I-th packet filter 3031 of matching module, after the match attribute value of i-th packet filter 3031 is mated with the header parameter value of the IP packet preserved in a kth cache blocks 3011, the header parameter value of the match attribute value of i-th packet filter 3031 with the IP packet preserved in (k+1) individual cache blocks 3012 is mated.
It should be noted that, for main control module 302 and (i+1) individual packet filter 3032, in actual applications, main control module 302, also for working as (i+1)=m, if it fails to match for the header parameter value of the IP packet preserved in the match attribute value of (i+1) individual packet filter 3032 and a kth cache blocks 3011, evolved packet system carrying index EBI in main control module 302 is write in the structure of the IP packet of a kth cache blocks 3011 correspondence, by the structure address of the IP packet of preservation in a kth cache blocks 3011 stored in transmit buffer 304.
It should be noted that, for main control module 302 and transmit buffer 304, in actual applications, main control module 302, also meets preset down trigger condition for judging whether, if meet, triggered interrupts;
Transmit buffer 304, also for protocol stack is exported in the structure address of the IP packet preserved in transmit buffer 304, processes to make the structure address of protocol stack to the IP packet preserved in transmit buffer 304.
It should be noted that, for main control module 302 and IP header parameter buffer 301, in actual applications, main control module 302, also for the structure address of IP packet that will preserve in a kth cache blocks 3011 stored in after in transmit buffer 304, a kth cache blocks 3011 of IP header parameter register 301 is reset;
IP header parameter buffer 301, also for extracting the header parameter value of the IP packet do not preserved and structure address and be saved to the kth cache blocks 3011 of IP header parameter buffer from IP traffic.
It should be noted that, for main control module 302, in actual applications, main control module 302, also before performing at (i+1) individual packet filter 3032, carry out judging (i+1) individual packet filter 3032 whether enable free time, if so, trigger (i+1) individual packet filter 3032 to perform.
What needs were said is, main control module 302, also before performing at i-th packet filter, judge that whether (i+1) individual cache blocks is effective, if so, trigger i-th packet filter 3031 to mate with the header parameter value of the IP packet preserved in (k+1) individual cache blocks 3012.
It should be noted that, the content such as information interaction, implementation between each module/unit of said apparatus, due to the inventive method embodiment based on same design, its technique effect brought is identical with the inventive method embodiment, particular content see describing in the present invention's embodiment of the method as shown in Figure 1, can repeat no more herein.
In the embodiment of the present invention, first IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from the n of IP traffic IP packet, then be saved in x cache blocks in IP header parameter buffer respectively, the header parameter value of the match attribute value of the i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter of matching module, then the match attribute value of i-th packet filter is entered to mate with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter, visible, in embodiments of the present invention, i-th packet filter is after the header parameter value of having mated the IP packet preserved in a kth cache blocks, just can mate the header parameter value of the IP packet preserved in (k+1) individual cache blocks again, and do not need that m packet filter in by the time matching module is all data packet matched with the IP that preserves in a kth cache blocks completely to carry out afterwards again, that is, in the embodiment of the present invention, each packet filter in matching module can parallel processing to the coupling of the IP packet preserved in each cache blocks in IP header parameter buffer, the matching efficiency of IP packet and packet filter can be improved.
Next, be described in detail to the coupling accelerator that the embodiment of the present invention proposes with an actual application scenarios, as shown in Figure 4, coupling accelerator comprises: IP header parameter buffer, main control module, matching module, transmit buffer, wherein,
IP header parameter buffer comprises: cache blocks 1, cache blocks 2, cache blocks n, this IP header parameter buffer comprises n cache blocks, in order to the enable work of all PF in matching module can be made, so n value should be 256, because IP header parameter buffer is when carrying out IP header parameter and extracting, matching module also matching treatment at the same time, the speed extracted when IP header parameter is less than PF rate matched in matching module, the inadequate situation of buffer memory would not be there is in IP header parameter buffer, in order to reduce hardware resource cost, herein in IP header parameter buffer cache blocks for 16.Wherein, each cache blocks in IP header parameter buffer at least should comprise three parts, as shown in Figure 4, only depict in Fig. 4 in cache blocks 1 and include IP packet structure body address register, match attribute value register, status register, other cache blocks as cache blocks 2 ..., cache blocks n includes this 3 parts, specifically comprise in each cache blocks: one for depositing the structure address register including IP packet information; Another is for depositing the match attribute value register of the header parameter extracted from IP packet, also has one to be used to indicate the whether effective status register of current cache block.Wherein the read-write of cache blocks operates successively according to the operating state of cache blocks, for writing cache blocks when preserving header parameter value and the structure address of IP packet in the cache blocks in IP header parameter buffer, the free buffer block writing cache blocks nearest backward from last time in existing free buffer block carries out write operation; For reading cache blocks when IP header parameter is mated with matching module, the valid cache block reading cache blocks nearest backward from last time in existing valid cache block carries out read operation.
Main control module comprises: trigger register, length register, EBI register, configuration register, status register, next introduces one by one respectively.
Trigger register: in conjunction with the space size of transmit buffer, configure interrupt produces trigger condition;
Length register: when interrupting producing for storing, the number of the IP packet structure body address of extracting from transmit buffer.
EBI register: for storing EBI corresponding to EBI when all it fails to match (namely all PF) that do not have PF, under same PDN connects, if all carryings (comprising default bearing and dedicated bearer) are all assigned PF, then this EBI register is set to an invalid value;
Configuration register: for storing the configuration informations such as coupling accelerator is enable, matching module is enable and trigger register is enable;
Status register: the work state informations such as interrupt status, IP header parameter buffer, matching module;
It should be noted that, if there are other functional requirements, register number can be increased for different control.
Matching module comprises 256 PF, according to PF priority sequence design from high to low, be respectively PF0, PF1, PF2 ..., PF255, namely PF0 corresponds to the PF that priority is 0, and PFk deposits and preferentially corresponds to the PF that priority is k, and PFk refers to a kth PF.At least there are five parts in each PF:
Comparator: compare with the match attribute value of PF for IP data packet header parameter value;
Status register: the state informations such as record PF operating state;
EBI register: deposit the EPS bearing identification (EBI) that PF is corresponding;
Configuration register: the enable control bit depositing PF match attribute principle and matching module, PF match attribute principle is wherein according to bitmap (bitmap) design, and each bit represents a kind of validity of PF match attribute;
Property value register: the match attribute value depositing corresponding PF, can as in following table 1 design:
Wherein far-end address and far-end address subnet mask belong to same match attribute, therefore a shared bit represents.
Only depict PF0 in the diagram and include comparator, status register, EBI register, configuration register, property value register, but other PF also includes this five part, is omitted in the diagram.
Transmit buffer: for depositing the IP pack arrangement body address after the match is successful.Data buffer area design should be noted: it is excessive that buffer space does not advise opening up, to reduce hardware spending;
The workflow of following introduction coupling accelerator as shown in Figure 4.
Down trigger creation of condition can according to trigger condition or idle triggered interrupts creation of condition, trigger condition is: just produce interruption when the IP packet stored in transmit buffer reaches trigger condition, this interrupt notification mode can avoid that often the match is successful, and an IP packet just produces an inefficient situation of interrupting, interrupt processing too frequently can be reduced, save system resource, improve system effectiveness.Idle triggered interrupts condition is: in actual use, the number of the IP packet of last transmission does not probably reach the number of the IP packet producing triggered interrupts, for solving the situation of this tail effect, gone out by last part IP Packet Generation by idle triggered interrupts, the Production conditions of idle triggered interrupts is that following three conditions are set up simultaneously: the number that in IP header parameter buffer, all cache blocks free time, all enable PF of matching module are in IP packet in enable free time, transmit buffer is greater than 0.
It should be noted that, herein following four conditions of hypothesis in application scenarios: in (1) this example, the node number of each IP Data-Link is 10, and namely 10 IP packets form an IP Data-Link; (2) cache blocks of IP header parameter buffer has 16 pieces; (3) suppose that the trigger condition in trigger register is set to 12; (4) one must be comprised in IP Data-Link in IP packet structure body in order to store the member of corresponding EBI value, when the match is successful or it fails to match with whole PF for IP packet and PF, corresponding EBI is written in member corresponding to IP packet, this can reduce the treating capacity interrupting producing rear protocol stack, and saves data buffer space.Next the workflow of coupling accelerator is introduced in detail:
First, initial phase
1, matching module: according to receive PDN connect in the match attribute value of all upstream packet filter PF carry out in configurations match module configuration register, comprise the match attribute principle of each PF and enable configuration, configure the corresponding EBI register of each PF.
2, main control module:
A), configuration EBI register: store the EBI without the carrying correspondence of PF, under same PDN connects, if all carryings (comprising default bearing and dedicated bearer) are all assigned PF, then this EBI register is set to an invalid value.
B), configuration register and trigger register configuration: configure interrupt is enable, matching module is enable, and trigger condition is arranged.
C), status register resets.
D), enable coupling accelerator.
Then, matching stage
1, the handling process of single IP packet in coupling accelerator is first simply introduced, as shown in Figure 5:
1.1, IP packet enters coupling accelerator, and first check that whether the coupling accelerator enable bit in main control module in configuration register is effective, be namely confirmed whether to set up default bearing, if not enable, coupling end is exited; If just enter next step enable, the cache blocks of IP header parameter buffer is put in extraction IP data packet header parameter and IP packet structure body address, enters 1.2;
1.2, in the configuration register in main control module, whether matching module enable bit is effective, if not enable, then transmit buffer is put in IP packet structure body address, simultaneously by the corresponding member of EBI value write IP packet structure body in main control module, coupling end is exited; If enable, then IP packet sent into matching module and mate, enter 1.3;
1.3, from IP header parameter buffer, IP data packet header parameter value is extracted, matching treatment is carried out in matching module, judge that whether PF0 is enable, not enable, enter PF1 module coupling, until there is enable PF module, if PF0 is enable, IP data packet header parameter value is mated with the match attribute value in PF0 and carries out, enter 1.4;
If 1.4 the match is successful, by IP packet structure body address stored in transmit buffer, main control module is by corresponding member in corresponding for PF0 EBI value write IP packet structure body simultaneously, and the cache blocks state storing this IP data packet header parameter in cache blocks 1 in IP header parameter buffer is reset, represent that this cache blocks 1 is idle, new IP data packet header parameter can be stored, and the PF0 state in matching module is reset, represent the PF0 enable free time, now PF0 can mate next IP packet, and matching process terminates; If it fails to match, enter next PF and mate, each PF afterwards does the process identical with PF0, enters 1.5;
1.5, suppose to match PF254 still unsuccessful, it is different from PF above to enter PF255 process, judges that whether PF255 enable, if not enable with 1.2 process identical, if enable, IP data packet header parameter value is mated with the matching principle property value in PF255, the match is successful then by IP packet structure body address stored in transmit buffer, simultaneously by corresponding member in corresponding for PF255 EBI value write IP packet structure body, and the cache blocks state storing this IP data packet header parameter in the cache blocks 1 in IP header parameter buffer is reset, represent that this cache blocks 1 is idle, new IP data packet header parameter can be stored, and PF255 state is reset, represent the PF0 enable free time, now PF255 can mate next IP packet, coupling end is exited, if it fails to match still do to process with 1.2 identical.
2, multiple IP Data-Link carries out the workflow that processes simultaneously, as shown in Fig. 6 (a), Fig. 6 (b), Fig. 6 (c), wherein, Fig. 6 (a) to carry out the schematic diagram of matching treatment for multiple IP Data-Link in the Ti moment, Fig. 6 (b) to carry out the schematic diagram of matching treatment for multiple IP Data-Link in the Ti+1 moment, Fig. 6 (c) to carry out the schematic diagram of matching treatment for multiple IP Data-Link in the Ti+2 moment, wherein
2.1, when IP Data-Link 1 is come, first by all IP data packet header parameter values in IP Data-Link 1 and IP packet structure body address extraction out and be stored in each cache blocks of IP header parameter buffer together, when being checked through IP header parameter buffer and there is IP header parameter information, matching module extracts the match attribute value matching ratio of IP data packet header parameter value in cache blocks 1 and PF0 comparatively from IP header parameter buffer;
If 2.2 at this moment IP Data-Link 2 arrive, IP header parameter buffer is checked through available free cache blocks, continues by the IP data packet header parameter value in IP Data-Link 2 and IP packet structure body address extraction out and to be stored in cache blocks idle in IP header parameter buffer until all IP data packet header parameter values and structure address extraction terminate in IP Data-Link 2 together;
2.3, as shown in Fig. 6 (a), in the Ti moment, IP1 starts to mate with PF0, if it fails to match, sends in next effectively PF and PF1 and mates; Otherwise the match is successful then stores IP1 packet structure body address stored in transmit buffer, EBIx corresponding for PF0 is write corresponding member in IP1 packet structure body simultaneously; Suppose IP1 and PFO herein the match is successful and be sent in transmit buffer and store; Cache blocks 1 state depositing in IP1 data packet header parameter value in IP header parameter buffer is reset simultaneously, represent that cache blocks 1 is idle, next IP data packet header parameter value can be stored, and read the IP data packet header parameter value of IP17 in IP Data-Link 2 and IP packet structure body address is left in IP header parameter buffer.As long as PF0 module is in enable idle condition, matching module continues to compare with the matching principle property value of the PF0 in matching module mate leaving in IP header parameter buffer next IP2 data packet header parameter value in; Make IP data packet header parameter extraction and Data Matching parallel running;
2.4, the matching treatment of IP packet in other PF is undertaken by the handling process of IP1 packet in PF0, parameter extraction and Data Matching walk abreast and carry out simultaneously, this IP packet is just present in the structure address write transmit buffer of IP header parameter buffer by the data packet matched success of any one PF and IP, simultaneously by corresponding member in this IP of EBI value corresponding for this PF write packet structure body; Cache blocks corresponding in IP header parameter buffer is reset simultaneously and identify into the enable free time with corresponding PF in matching module.
2.5, as shown in Fig. 6 (b), in the Ti+1 moment, the match is successful deposits in transmit buffer for the IP12 of IP8, IP2 and IP Data-Link 2 of IP Data-Link 1, the cache blocks state depositing in the packet header parameter value depositing IP8, IP2, IP12 in IP header parameter buffer is reset simultaneously, represent that this three cache blocks is idle, can storing IP data packet header parameter value and IP packet structure body address, and will the data packet matched successful PF state of three IP reset therewith, represent this three PF enable free time; Suppose IP2 the match is successful yet in PF255 then the EBI value simultaneously read in main control module in IP packet structure body address write transmit buffer to be write corresponding member in IP packet structure body;
2.6, as shown in Fig. 6 (c), in the Ti+2 moment, the number of the IP packet structure body address stored in transmit buffer meets trigger condition, is namely filled with 12 IP packet structure body addresses and produces an interrupt notification protocol stack deal with data; The IP packet structure body now read out from transmit buffer is dispersion, after protocol stack process, the IP packet in transmit buffer is formed a new IP Data-Link and transmits.By this kind of interrupt mode process, meet in IP Data-Link the PF high priority demand that first the match is successful sends;
2.7, in addition, there is a tail effect here, namely in IP Data-Link, the number of the IP packet of last transmission does not probably reach the IP packet number producing triggered interrupts, in IP header parameter buffer, in idle, the matching module of all cache blocks, all PF are in IP packet number in enable free time, transmit buffer and are greater than 0 these three conditions and set up simultaneously, produce idle triggered interrupts, just can avoid this tail effect.
One of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.
Above the matching process of a kind of IP packet provided by the present invention is described in detail with coupling accelerator, for one of ordinary skill in the art, according to the thought of the embodiment of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (15)
1. a matching process for IP packet, is characterized in that, comprising:
IP header parameter buffer extracts header parameter value and the structure address of each IP packet respectively from n IP packet of IP traffic, and be then saved to respectively in x cache blocks of described IP header parameter buffer, wherein n, x are positive integers;
The header parameter value of the match attribute value of described i-th packet filter with the IP packet preserved in a kth cache blocks is mated by i-th packet filter of matching module, described matching module comprises m packet filter, wherein, 1≤i < (i+1) < m, i, k, m are positive integers;
If the match is successful for the header parameter value of the IP packet preserved in the match attribute value of described i-th packet filter and a described kth cache blocks, the evolved packet system of described i-th packet filter carrying index EBI writes in the structure of IP packet corresponding to a described kth cache blocks by main control module, described main control module by the structure address of IP packet of preserving in a described kth cache blocks stored in transmit buffer;
If it fails to match for the header parameter value of the IP packet preserved in the match attribute value of described i-th packet filter and a described kth cache blocks, the header parameter value of the match attribute value of described (i+1) individual packet filter with the IP packet preserved in a described kth cache blocks is mated by (i+1) individual packet filter of described matching module;
After the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks by i-th packet filter of described matching module, the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by described i-th packet filter.
2. the matching process of IP packet according to claim 1, it is characterized in that, after the match attribute value of described (i+1) individual packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks by (i+1) individual packet filter of described matching module, also comprise:
As (i+1)=m, if it fails to match for the header parameter value of the IP packet preserved in the match attribute value of described (i+1) individual packet filter and a described kth cache blocks, evolved packet system carrying index EBI in described main control module writes in the structure of IP packet corresponding to a described kth cache blocks by described main control module, described main control module by the structure address of IP packet of preserving in a described kth cache blocks stored in transmit buffer.
3. the matching process of IP packet according to claim 1, is characterized in that, described method also comprises:
Whether described master control module judges meets preset down trigger condition, if meet, described main control module triggered interrupts, protocol stack is exported in the structure address of the IP packet preserved in described transmit buffer by described transmit buffer, processes to make the structure address of described protocol stack to the IP packet preserved in described transmit buffer.
4. the matching process of IP packet according to claim 3, is characterized in that, described preset down trigger condition comprises:
The number of the structure address of the IP packet preserved in described transmit buffer is not less than preset number;
Or, meet the condition of idle triggered interrupts, the condition of described idle triggered interrupts comprises: the number that in described IP header parameter buffer, all cache blocks m packet filter that be idle, described matching module is all in the structure address of the IP packet preserved in enable idle condition, described transmit buffer is greater than zero.
5. the matching process of IP packet according to claim 1, is characterized in that, the structure address of IP packet of preserving in a described kth cache blocks stored in after in transmit buffer, also comprises by described main control module:
The kth of a described IP header parameter register cache blocks resets by described main control module;
Described IP header parameter buffer extracts the header parameter value of the IP packet do not preserved and structure address and is saved to a kth cache blocks of described IP header parameter buffer from IP traffic.
6. the matching process of IP packet according to claim 1, is characterized in that, the priority index EPI of described i-th packet filter is higher than the EPI of described (i+1) individual packet filter.
7. the matching process of IP packet according to claim 1, is characterized in that, described match attribute value comprises at least one of following property value:
Next property value in protocol number or IPv6 in grade of service property value, IPv4 in COS or Internet protocol sixth version IPv6 in far-end address and far-end address subnet mask property value, Security Parameter Index property value, flow label property value, local port scope attribute value, remote port scope attribute value, Internet protocol the 4th edition IPv4.
8. the matching process of IP packet according to claim 1, it is characterized in that, before the match attribute value of described (i+1) individual packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks by (i+1) individual packet filter of described matching module, also comprise:
(i+1) individual packet filter whether enable free time of matching module described in described master control module judges, if so, described main control module triggers described (i+1) individual packet filter and performs the function of carrying out with the header parameter value of the IP packet preserved in a described kth cache blocks mating.
9. the matching process of IP packet according to claim 1, it is characterized in that, before the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks by i-th packet filter of matching module, also comprise:
In IP header parameter buffer described in described master control module judges, whether (k+1) individual cache blocks is effective, if so, described i-th packet filter of described main control module triggering mates with the header parameter value of the IP packet preserved in described (k+1) individual cache blocks.
10. a coupling accelerator, is characterized in that, comprising: IP header parameter buffer, main control module, matching module, transmit buffer, wherein,
Described IP header parameter buffer comprises: x cache blocks, and wherein x is positive integer;
Described IP header parameter buffer, for extracting header parameter value and the structure address of each IP packet from n IP packet of IP traffic respectively, then be saved to respectively in x cache blocks of described IP header parameter buffer, wherein, n is positive integer;
Described matching module comprises m packet filter, wherein, 1≤i < (i+1) < m, i, m are positive integers;
I-th packet filter of described matching module, for the header parameter value of the match attribute value of described i-th packet filter with the IP packet preserved in a kth cache blocks being mated, wherein, k is positive integer;
Described main control module, if for the header parameter value of IP packet of preserving in the match attribute value of described i-th packet filter and a described kth cache blocks, the match is successful, the evolved packet system of described i-th packet filter carrying index EBI is write in the structure of IP packet corresponding to a described kth cache blocks, by the structure address of the IP packet in a described kth cache blocks stored in described transmit buffer;
Described transmit buffer, for preserve described main control module stored in a kth cache blocks in the structure address of IP packet of preserving;
(i+1) individual packet filter of described matching module, if for the header parameter value of IP packet of preserving in the match attribute value of described i-th packet filter and a described kth cache blocks, it fails to match, the header parameter value of the match attribute value of described (i+1) individual packet filter with the IP packet preserved in a described kth cache blocks mated;
I-th packet filter of described matching module, after the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in a described kth cache blocks, the match attribute value of described i-th packet filter is mated with the header parameter value of the IP packet preserved in (k+1) individual cache blocks.
11. coupling accelerators according to claim 10, it is characterized in that, described main control module, also for working as (i+1)=m, if it fails to match for the header parameter value of the IP packet preserved in the match attribute value of described (i+1) individual packet filter and a described kth cache blocks, evolved packet system carrying index EBI in described main control module is write in the structure of IP packet corresponding to a described kth cache blocks, by the structure address of IP packet of preserving in a described kth cache blocks stored in transmit buffer.
12. coupling accelerators according to claim 10, is characterized in that,
Described main control module, also meets preset down trigger condition for judging whether, if meet, triggered interrupts;
Described transmit buffer, also for protocol stack is exported in the structure address of the IP preserved in described transmit buffer packet, processes to make the structure address of described protocol stack to the IP packet preserved in described transmit buffer.
13. coupling accelerators according to claim 10, is characterized in that,
Described main control module, also for the structure address of IP packet of will preserve in a described kth cache blocks stored in after in transmit buffer, the kth of a described IP header parameter register cache blocks is reset;
Described IP header parameter buffer, also for extracting the header parameter value of the IP packet do not preserved and structure address and be saved to the kth cache blocks of described IP header parameter buffer from IP traffic.
14. coupling accelerators according to claim 10, it is characterized in that, described main control module, also before performing at described (i+1) individual packet filter, judge described (i+1) individual packet filter whether enable free time, if so, trigger described (i+1) individual packet filter to perform.
15. coupling accelerators according to claim 10, it is characterized in that, described main control module, also before performing at described i-th packet filter, judge that whether described (i+1) individual cache blocks is effective, if so, trigger described i-th packet filter to mate with the header parameter value of the IP packet preserved in described (k+1) individual cache blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110459754.XA CN103188042B (en) | 2011-12-31 | 2011-12-31 | A kind of matching process of IP packet and coupling accelerator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110459754.XA CN103188042B (en) | 2011-12-31 | 2011-12-31 | A kind of matching process of IP packet and coupling accelerator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103188042A CN103188042A (en) | 2013-07-03 |
| CN103188042B true CN103188042B (en) | 2016-03-30 |
Family
ID=48679020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110459754.XA Active CN103188042B (en) | 2011-12-31 | 2011-12-31 | A kind of matching process of IP packet and coupling accelerator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103188042B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103491008B (en) * | 2013-09-22 | 2016-08-24 | 福建星网锐捷网络有限公司 | MAC Address matching treatment device and method |
| CN104113554B (en) * | 2014-07-30 | 2017-06-16 | 中国联合网络通信集团有限公司 | A kind of processing method and processing device of filter |
| CN106717051A (en) * | 2014-09-24 | 2017-05-24 | 瑞典爱立信有限公司 | A method and user equipment for uplink traffic mapping |
| CN105916176B (en) * | 2016-04-18 | 2021-09-03 | 全球能源互联网研究院 | Power service bearing mapping method based on LTE system |
| CN109376546B (en) * | 2018-09-28 | 2022-04-29 | 深信服科技股份有限公司 | Data packet auditing method, system, device and storage medium based on global rule |
| CN109857359B (en) * | 2019-02-14 | 2023-12-26 | 深圳前海骁客影像科技设计有限公司 | MIPI data processing method, device and circuit |
| CN110324326B (en) * | 2019-06-20 | 2020-12-22 | 中国科学院信息工程研究所 | Network data transmission control method and device based on service security marker |
| CN113438097B (en) * | 2021-05-21 | 2022-08-23 | 翱捷科技股份有限公司 | Method and device for realizing network acceleration |
| CN113369173A (en) * | 2021-06-29 | 2021-09-10 | 上海希翎智能科技有限公司 | Full-automatic plastic bottle color sorting equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1585375A (en) * | 2003-08-22 | 2005-02-23 | 中国科学院研究生院 | Dispatching method for virtual destination queuing exchanging system |
| CN1674557A (en) * | 2005-04-01 | 2005-09-28 | 清华大学 | Parallel IP packet sorter matched with settling range based on TCAM and method thereof |
| CN101035131A (en) * | 2007-02-16 | 2007-09-12 | 杭州华为三康技术有限公司 | Protocol recognition method and device |
| CN101499875A (en) * | 2008-02-02 | 2009-08-05 | 三星电子株式会社 | Variant processing rate supporting apparatus for LTE rate de-matching and de-interleaving |
| CN101610587A (en) * | 2009-07-13 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of data transmission method and device based on the TDD standard |
| CN102761393A (en) * | 2012-07-05 | 2012-10-31 | 中兴通讯股份有限公司 | Method and device for processing data message |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7424468B2 (en) * | 2002-07-02 | 2008-09-09 | Samsung Electronics Co., Ltd. | Internet protocol address look-up device |
| US7134143B2 (en) * | 2003-02-04 | 2006-11-07 | Stellenberg Gerald S | Method and apparatus for data packet pattern matching |
| KR100953453B1 (en) * | 2007-11-27 | 2010-04-20 | 한국전자통신연구원 | Method of uplink IP packet filtering control in mobile terminal |
-
2011
- 2011-12-31 CN CN201110459754.XA patent/CN103188042B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1585375A (en) * | 2003-08-22 | 2005-02-23 | 中国科学院研究生院 | Dispatching method for virtual destination queuing exchanging system |
| CN1674557A (en) * | 2005-04-01 | 2005-09-28 | 清华大学 | Parallel IP packet sorter matched with settling range based on TCAM and method thereof |
| CN101035131A (en) * | 2007-02-16 | 2007-09-12 | 杭州华为三康技术有限公司 | Protocol recognition method and device |
| CN101499875A (en) * | 2008-02-02 | 2009-08-05 | 三星电子株式会社 | Variant processing rate supporting apparatus for LTE rate de-matching and de-interleaving |
| CN101610587A (en) * | 2009-07-13 | 2009-12-23 | 中兴通讯股份有限公司 | A kind of data transmission method and device based on the TDD standard |
| CN102761393A (en) * | 2012-07-05 | 2012-10-31 | 中兴通讯股份有限公司 | Method and device for processing data message |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103188042A (en) | 2013-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103188042B (en) | A kind of matching process of IP packet and coupling accelerator | |
| US11689501B2 (en) | Data transfer method and virtual switch | |
| CN113438642B (en) | 5G-oriented user traceability association method and system | |
| CN111782140A (en) | Network data packet storage method and device, computer equipment and storage medium | |
| CN106411924B (en) | A kind of method creating session forwarding-table item, the method and device that E-Packets | |
| CN108123775A (en) | The method and apparatus of transmission packet | |
| WO2014135038A1 (en) | Packet transmission method and device based on pcie bus | |
| CN113645140B (en) | Message statistical method, device, storage medium and network equipment | |
| CN107451092A (en) | A kind of data transmission system based on IB networks | |
| US20230006937A1 (en) | Packet flow identification with reduced decode operations | |
| CN106656714A (en) | Communication protocol method and system based on EtherCAT bus | |
| CN105635000A (en) | Message storing and forwarding method, circuit and device | |
| CN105207858B (en) | Access device and method for connecting user equipment to network executed by access device | |
| US20120140640A1 (en) | Apparatus and method for dynamically processing packets having various characteristics | |
| CN108156034B (en) | Message forwarding method and message forwarding system based on deep neural network assistance | |
| CN114422617A (en) | Message processing method, system and computer readable storage medium | |
| CN113973091A (en) | Message processing method, network equipment and related equipment | |
| CN109120731B (en) | Universal communication method, system and device | |
| CN116095003A (en) | Address mapping method and device for Ethernet data frame and FC data frame | |
| CN103348740B (en) | A kind of access processing method, equipment and system | |
| CN112612670B (en) | Session information statistical method, device, exchange equipment and storage medium | |
| CN113518032B (en) | SRv 6-based user credible identification carrying method and system | |
| CN114598675A (en) | Control method, device, equipment and medium for realizing host blocking based on ARP | |
| CN111064673B (en) | User plane data integrity protection method and device, electronic equipment and medium | |
| CN102469011B (en) | Data transmission method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170427 Address after: Nanping Street 400060 Chongqing Nan'an District Nancheng Road No. 199 left attached to the floor 403 Patentee after: Keen (Chongqing) Microelectronics Technology Co.,Ltd. Address before: 400065 Chongqing Nan'an District huangjuezhen pass Fort Park No. 1 Patentee before: CHONGQING CYIT COMMUNICATION TECHNOLOGIES Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20181102 Address after: 201203 Building 1, exhibition hall, 2288 lane, 2288 Chong, road, Zhangjiang hi tech park, Shanghai Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 400060 Nanping Road 199, Nanping Street, Nan'an District, Chongqing, 403 Patentee before: Keen (Chongqing) Microelectronics Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190321 Address after: 361006 Xiamen Free Trade Pilot Area, Xiamen, Fujian Province, Unit X, 8th Floor, Unit 05, Building D, Xiamen International Shipping Center, 97 Xiangyu Road, Xiamen Section Patentee after: Xinxin Finance Leasing (Xiamen) Co.,Ltd. Address before: 201203 Building 1, exhibition hall, 2288 lane, 2288 Chong, road, Zhangjiang hi tech park, Shanghai Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20130703 Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Assignor: Xinxin Finance Leasing (Xiamen) Co.,Ltd. Contract record no.: X2021110000009 Denomination of invention: An IP packet matching method and matching accelerator Granted publication date: 20160330 License type: Exclusive License Record date: 20210317 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221013 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288 Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. Address before: 361006 Xiamen Free Trade Pilot Area, Xiamen, Fujian Province, Unit X, 8th Floor, Unit 05, Building D, Xiamen International Shipping Center, 97 Xiangyu Road, Xiamen Section Patentee before: Xinxin Finance Leasing (Xiamen) Co.,Ltd. |
|
| TR01 | Transfer of patent right |