CN103187419A

CN103187419A - Layout distribution structure of page selecting tubes in flat type read-only memory

Info

Publication number: CN103187419A
Application number: CN2011104532460A
Authority: CN
Inventors: 赵健; 赵海; 刘晓伟
Original assignee: Wuxi China Resources Semico Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2011-12-30
Filing date: 2011-12-30
Publication date: 2013-07-03
Anticipated expiration: 2031-12-30
Also published as: CN103187419B

Abstract

The invention relates to a layout distribution structure of page selecting tubes in a flat type read-only memory. The page selecting tubes are arranged in an area of a read-only memory array, the page selecting tubes are located at two ends of the read-only memory array, and the page selecting tubes and memorizer units in the read-only memory array are of transistor structures in a same type. By means of the layout distribution structure of the page selecting tubes in the flat type read-only memory, separating distribution of left bit selecting tubes and right bit selecting tubes is achieved, quantity of unilateral tubes is reduced by a half, layout distribution has elasticity, a layout structure is optimized on the premise of completing logical functions, whole distribution of the memory array is not influenced, a structure is simple, a connecting line is short, no bend is needed, minimization of an area of the read-only memory (ROM) array is guaranteed, risks of electricity leakage and effect failures in a process procedure can be reduced, an achieving mode is simple, no extra layer is increased, yield is effectively improved, cost is obviously reduced, working performance is stable and reliable, and an application scope is wide.

Description

Page or leaf is selected the domain laying structure of pipe in the plate read-only memory

Technical field

The present invention relates to integrated circuit Butut field, particularly plate (Flat-Cell) read-only memory (ROM) element layout (Layout) is laid technical field, specifically refers to the domain laying structure of page or leaf selection pipe in a kind of plate read-only memory.

Background technology

In the prior art, it is a kind of read-only storage that read-only memory is called for short ROM (READ-ONLY-MEMORY), and in sort memory, the content of depositing can not lost under powering-off state yet the data stationary that needs long-term storage for it.

Mask version ROM is that chip just is fixed up the content of needs storage when making in factory with circuit structure.It has a variety of implementations, and Flat-Cell ROM wherein can utilize the limit of photoetching to greatest extent on technology realizes, adopt field-free oxygen technology, can reduce the ROM area greatly only increasing under the situation that a little light cuts blocks for printing.

At present, Flat-Cell ROM technology on the market adopts 0.35 micron and following technology mostly, in order to satisfy the demand of memory cell (Memory Cell) efficient, the general adopting process of memory array (Memory Array) can be accepted the wide spacing of minimum bar, and the data of memory cell to read generally be that left and right sides bit selects pipe (left-right bit selection transistors) to realize, this is selected, and pipe is actual to have played the effect that memory page is selected.Add page or leaf and select pipe in highdensity memory array, the laying out pattern design is even more important, and should pursue minimizing of chip area, guarantees the window tolerance limit that technology realizes again.

Summary of the invention

The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of can realize layout area minimize, do not influence the overall distribution of memory array, simple in structure, stable and reliable working performance, the scope of application comparatively widely in the plate read-only memory page or leaf select the domain laying structure of pipe.

In order to realize above-mentioned purpose, page or leaf selects the domain laying structure of pipe to have following formation in the plate read-only memory of the present invention:

Page or leaf is selected the domain laying structure of pipe in this plate read-only memory, its main feature is, described page or leaf selects pipe to be arranged in the read-only memory array zone, this page selection pipe is positioned at the end positions of described read-only memory array, and the memory cell in this page selection pipe and the read-only memory array is the transistor arrangement of same kind.

Page or leaf in this plate read-only memory in the domain laying structure of page or leaf selection pipe selects a pipe to comprise left bit selection pipe and right bit selection pipe, and described left bit is selected to manage and right bit selects pipe to lay respectively at the end positions of described read-only memory array.

It is polysilicon that page or leaf in this plate read-only memory in the domain laying structure of page or leaf selection pipe is selected the grid of pipe, and this page selects source electrode and the drain electrode of pipe to be the n type buried layer diffusion region.

The drain electrode output of the row memory cell in the read-only memory array in this plate read-only memory in the domain laying structure of page or leaf selection pipe has the prolongation line, described prolongation line selects the source electrode of pipe to be connected with the corresponding page or leaf of this row memory cell, and this page selects the drain electrode of pipe to be connected with external circuit with the Metal Contact window by metal level.

N type buried layer diffusion region in this plate read-only memory in the domain laying structure of page or leaf selection pipe is strip.

The tail end of this strip n type buried layer diffusion region in this plate read-only memory in the domain laying structure of page or leaf selection pipe is the T font.

Adopted page or leaf in the plate read-only memory of this invention to select the domain laying structure of pipe, owing to wherein page or leaf is selected pipe place the ROM array region, select pipe to lay respectively at the two ends of memory array left and right sides bit wherein, and adopt the transistor arrangement of same kind with memory cell, thereby realized that left and right sides bit selects pipe separately to arrange, monolateral number of tubes reduces by half, make laying out pattern have elasticity more, under the prerequisite of completion logic function, domain structure has obtained optimization, do not influence the overall distribution of memory array, simple in structure, line very short and need not the bending, both guaranteed that the ROM array area minimized, reduced the risk that electric leakage was lost efficacy in the manufacturing process again, implementation is simple, need not to increase extra level, effectively improved yield, significantly reduced cost, stable and reliable working performance, the scope of application are comparatively extensive.

Description of drawings

Fig. 1 is that page or leaf selects in the domain laying structure of pipe page or leaf to select the corresponding logical construction schematic diagram of pipe in the plate read-only memory of the present invention.

Fig. 2 is the domain laying structure schematic diagram that page or leaf is selected pipe in the plate read-only memory of the present invention.

Embodiment

In order more to be expressly understood technology contents of the present invention, describe in detail especially exemplified by following examples.

See also illustrated in figures 1 and 2, page or leaf is selected the domain laying structure of pipe in this plate read-only memory, wherein, described page or leaf selects pipe to be arranged in the read-only memory array zone, this page selection pipe is positioned at the end positions of described read-only memory array, and the memory cell in this page selection pipe and the read-only memory array is the transistor arrangement of same kind.

Wherein, described page or leaf selects pipe to comprise that left bit is selected to manage and right bit is selected pipe, and described left bit selects pipe and right bit selection pipe to lay respectively at the end positions of described read-only memory array.

Simultaneously, it is polysilicon that described page or leaf is selected the grid of pipe, this page selects source electrode and the drain electrode of pipe to be the n type buried layer diffusion region, the drain electrode output of the row memory cell in the read-only memory array in the described domain laying structure has the prolongation line, described prolongation line selects the source electrode of pipe to be connected with the corresponding page or leaf of this row memory cell, and this page selects the drain electrode of pipe to be connected with external circuit with the Metal Contact window by metal level.

Moreover, the n type buried layer diffusion region in this plate read-only memory in the domain laying structure of page or leaf selection pipe is strip, and the tail end of described this strip n type buried layer diffusion region is the T font, or claims dog bone (Dog-bone).

In the middle of reality is used, the present invention selects pipe to place the ROM array region page or leaf among the Flat-Cell ROM, select pipe to lay respectively at the two ends of memory array left and right sides bit wherein, transistor arrangement with memory cell employing same kind, polysilicon (POLY) is gate terminal, n type buried layer diffusion region (buried N+diffusions, BN) be the source end, drain terminal, utilize the conductor characteristics of n type buried layer diffusion region, the drain terminal output of one row memory cell self is prolonged as line, the selection Guan Yuanduan corresponding with these row links to each other, and selects the drain terminal of pipe to be connected to the outside by metal level (metal) and Metal Contact window (ContactWindow) again.

See also shown in Figure 1ly, N0～N31 is 32 memory cells in the ROM array, and M1～M13 is that corresponding memory page is selected pipe.With wherein one row N0～N3 pipe be example, their source end node is all l＜0 〉, by BN bar l＜0 shown in Fig. 2 link to each other with the source end of M1; The drain terminal node is all l＜1 〉, by BN bar l＜1 shown in Fig. 2〉link to each other with the source end of M2 and M8 simultaneously. the left and right sides bit among Fig. 1 selects signal left/right to be connected the grid that page or leaf is selected pipe by the polysilicon shown in Fig. 2, the unnecessary pipe (Cell) that this polysilicon forms when crossing over the BN bar can inject by ROM CODE and make it invalid, need not to increase the excessive data layer.The source end of M1 is the dog bone (Dog-bone) that BN bar l＜0〉extended line forms, drain terminal BN layer outputs to node b＜0 by metal level Metal and Metal Contact window (Contact) 〉, the source end of M2 is BN bar l＜1〉prolongation, drain terminal BN layer outputs to node b＜1 by metal level and Metal Contact window 〉.When the left signal enabled, M1 and M2 effectively opened, and read the data of certain cell among N0～N3.

Because left and right sides bit selects pipe placed apart up and down, 13 pages or leaves that being easy to place circuit in 8 row array of memory cells width needs are selected pipe, avoided the length of BN bar and polysilicon strip apart from cabling and bending, BN bar layout straggly as shown in Figure 2, and with l＜0/2/4/6/8〉the bar tail make dog bone shape, can can reduce the failure risk of BN bar in manufacturing process on the other hand as the source end of M1/M4/M7/M9/M12 on the one hand.

In sum, basic thought of the present invention is that the page or leaf among the Flat-Cell ROM selects pipe to adopt the mode of permutation two ends placement, and selects the source/drain terminal of pipe as page or leaf in BN bar urogenesis dog bone shape.

Memory array shown in above Fig. 1 and Fig. 2 just is used for the embodiment that is illustrated, also has other various possible variations, does not all deviate from basic thought of the present invention.

Adopted the domain laying structure of page or leaf selection pipe in the above-mentioned plate read-only memory, owing to wherein page or leaf is selected pipe place the ROM array region, select pipe to lay respectively at the two ends of memory array left and right sides bit wherein, and adopt the transistor arrangement of same kind with memory cell, thereby realized that left and right sides bit selects pipe separately to arrange, monolateral number of tubes reduces by half, make laying out pattern have elasticity more, under the prerequisite of completion logic function, domain structure has obtained optimization, do not influence the overall distribution of memory array, simple in structure, line very short and need not the bending, both guaranteed that the ROM array area minimized, reduced the risk that electric leakage was lost efficacy in the manufacturing process again, implementation is simple, need not to increase extra level, effectively improved yield, significantly reduced cost, stable and reliable working performance, the scope of application are comparatively extensive.

In this specification, the present invention is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.

Claims

1. page or leaf is selected the domain laying structure of pipe in the plate read-only memory, it is characterized in that, described page or leaf selects pipe to be arranged in the read-only memory array zone, this page selection pipe is positioned at the end positions of described read-only memory array, and the memory cell in this page selection pipe and the read-only memory array is the transistor arrangement of same kind.

2. page or leaf is selected the domain laying structure of pipe in the plate read-only memory according to claim 1, it is characterized in that, described page or leaf selects pipe to comprise that left bit is selected to manage and right bit is selected pipe, and described left bit selects pipe and right bit selection pipe to lay respectively at the end positions of described read-only memory array.

3. the domain laying structure of page or leaf selection pipe in the plate read-only memory according to claim 1 is characterized in that it is polysilicon that described page or leaf is selected the grid of pipe, and this page selects source electrode and the drain electrode of pipe to be the n type buried layer diffusion region.

4. page or leaf is selected the domain laying structure of pipe in the plate read-only memory according to claim 3, it is characterized in that, the drain electrode output of the row memory cell in the described read-only memory array has the prolongation line, described prolongation line selects the source electrode of pipe to be connected with the corresponding page or leaf of this row memory cell, and this page selects the drain electrode of pipe to be connected with external circuit with the Metal Contact window by metal level.

5. select the domain laying structure of pipe according to page or leaf in claim 3 or the 4 described plate read-only memorys, it is characterized in that described n type buried layer diffusion region is strip.

6. the domain laying structure of page or leaf selection pipe in the plate read-only memory according to claim 5 is characterized in that the tail end of described this strip n type buried layer diffusion region is the T font.