CN103177946B - The manufacture method of false gate in back gate process - Google Patents
The manufacture method of false gate in back gate process Download PDFInfo
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- CN103177946B CN103177946B CN201110433706.3A CN201110433706A CN103177946B CN 103177946 B CN103177946 B CN 103177946B CN 201110433706 A CN201110433706 A CN 201110433706A CN 103177946 B CN103177946 B CN 103177946B
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Abstract
The invention provides a kind of manufacture method of false gate in back gate process, comprise the following steps：False gate material layer, layer of hard mask material are sequentially formed on substrate, wherein layer of hard mask material includes first mask layer of PSG and the second mask layer of TEOS silicon oxide；Using dry method and DHF wet method etch hard mask materials layer respectively, form hard mask figure wide at the top and narrow at the bottom；With hard mask figure as mask, dry etching vacation gate material layer, form false grid wide at the top and narrow at the bottom.According to the false grid manufacture method of the present invention, false grid vertical before are fabricated to trapezoid vacation grid wide at the top and narrow at the bottom；After false grid are removed, trapezoid groove can be formed；Thus greatly facilitating subsequently high K or the filling of metal gate material, expand fill process window, thus improve the reliability of device.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, more particularly, it is related to a kind of false gate in back gate process
Manufacture method.
Background technology
With high K/ metal gate engineering in the successful Application in 45 nm technology node so as to become sub- less than 30 nanometers technology
Node indispensable key modules chemical industry journey.Only adhere at present the Intel of metal gate (gate last) route after high K/
Company achieves successfully on 45 nanometers and 32 nanometers of volume productions.Follow the Samsung of IBM industry alliance, Taiwan Semiconductor Manufacturing Co., Ying Fei in recent years closely
The emphasis developed before is also turned to gate last engineering by high K/ elder generation's metal gate (gate first) by the industry giants such as icepro.
In Gate last engineering, after completing ion at high temperature annealing, need polycrystalline vacation grid to dig up, be then filled into
High K and metal gate material, flow process is shown in Fig. 1.As shown in Figure 1A, silicon substrate 1 is sequentially depositing formed silicon oxide bed course 2 with
And the false gate layer 3 of polysilicon, etching formed gate stack structure, in both sides deposited silicon nitride and etch formation side wall 4, subsequently whole
The interlayer dielectric layer (ILD) 5 of individual device surface cvd silicon oxide is simultaneously planarized using cmp (CMP).As Figure 1B institute
Show, adopt TAMH wet etching to remove the false gate layer 3 of polysilicon after CMP, and preferably employ HF or slow release etching liquid (BOE) goes
Except bed course 2, leave gate trench.As shown in Figure 1 C, gate trench is sequentially filled high k gate insulator 6, gate material layers
7 and cmp planarization.
Because device size constantly reduces, especially below 45 nm technology node, the grid that polycrystalline vacation grid are formed after diging up
Channel width is less than 50 nanometers, and depth is less than 100 nanometers, and depth is than usual ＞=1.5.So depth is larger, small-sized
Rectangle gate groove is equal in filling spreadability, consistency and wafer for the fill process of subsequently high K and metal gate material
Even property is proposed great challenge.
For this reason, being badly in need of a kind of method that effectively can uniformly fill gate trench.
Content of the invention
Therefore, it is an object of the invention to proposing a kind of manufacture method of false gate in back gate process, so that false grid go
Remove and effectively can uniformly fill gate trench afterwards.
The invention provides a kind of manufacture method of false gate in back gate process, comprise the following steps：Shape successively on substrate
Become false gate material layer, layer of hard mask material, wherein layer of hard mask material includes first mask layer of PSG and TEOS silicon oxide
Second mask layer；Using dry etching and DHF wet etching layer of hard mask material, form hard mask figure wide at the top and narrow at the bottom；With
Hard mask figure is mask, dry etching vacation gate material layer, forms false grid wide at the top and narrow at the bottom.
Wherein, in the hard mask figure wide at the top and narrow at the bottom of formation, the second mask layer has the cantilevered out portion than the first mask slice width
Point.
Wherein, the inclination angle to control false grid for the thickness of the cantilevered out partial width of adjustment and false gate material layer.Wherein, false grid
Inclination angle is less than or equal to 10 degree.
Wherein, TEOS silicon oxide adopts PECVD method to prepare with TEOS for predecessor.
Wherein, HF: H in DHF wet etching liquid2O is less than or equal to 1: 50.
Wherein, before using dry etching and DHF wet etching layer of hard mask material, also include to layer of hard mask material
Annealing.Wherein, annealing temperature is 800～900 DEG C, and annealing time is 10～60 minutes.
Wherein, false gate material layer includes polysilicon, non-crystalline silicon, microcrystal silicon, substrate include monocrystal silicon, SOI, monocrystalline germanium,
GeOI、SiGe、SiC、InSb、GaAs、GaN.
Present invention also offers a kind of rear grid technique, including step：System using false gate in back gate process as above
Make method, false grid wide at the top and narrow at the bottom are formed on substrate；Form side wall in false grid both sides；Remove false grid, formed wide at the top and narrow at the bottom
Gate groove；Filling gate insulator and grid material in gate groove.
According to the false grid manufacture method of the present invention, false grid vertical before are fabricated to trapezoid vacation grid wide at the top and narrow at the bottom；
After false grid are removed, trapezoid groove can be formed；Thus greatly facilitating subsequently high K or the filling of metal gate material, expand
Big fill process window, thus improve the reliability of device.
Purpose of the present invention, and the other purposes that here is unlisted, in the range of the application independent claims
It is satisfied.Embodiments of the invention limit in the independent claim, and specific features limit in dependent claims thereto.
Brief description
To describe technical scheme referring to the drawings in detail, wherein：
Fig. 1 shows the rear grid technique schematic diagram of prior art；
Fig. 2 to Fig. 7 shows the generalized section of each step of false grid manufacture method according to the present invention successively.
Specific embodiment
To describe feature and its skill of technical solution of the present invention referring to the drawings and with reference to schematic embodiment in detail
Art effect, discloses false gate in back gate process manufacture method.It is pointed out that similar reference represents similar knot
Structure.
With reference first to Fig. 2, sequentially form false gate material layer 20 over the substrate 10 and by least one the first mask layer 31
With at least one second mask layer 32 constitute layer of hard mask material, forming method be, for example, APCVD, LPCVD, PECVD,
The conventional deposition method such as HDPCVD.Substrate 10 needs according to device electric property and can adopt various backing materials, for example, include
Monocrystal silicon, silicon-on-insulator (SOI), monocrystalline germanium, germanium on insulator (GeOI), or SiGe, SiC, InSb, GaAs, GaN etc. its
His compound semiconductor materials.False gate material layer 20 is using the material different from mask layer 31/32 Etch selectivity, for example, many
Crystal silicon, non-crystalline silicon or microcrystal silicon.First mask layer 31 and/or the second mask layer 32 may include phosphorosilicate glass (also referred to as p-doped oxygen
SiClx, PSG), TEOS silicon oxide, for the hard mask layer etching after a while, both materials are different, and such as PSG 31 is in lower and TEOS
Silicon oxide 32 upper, or can also employing when can make to etch after a while the different particularly lower floor etching of speed be faster than middle level,
Middle level is faster than the three-decker on upper strata, the multiple structure even interlocking.In embodiments of the present invention, PSG typically with silane,
Phosphine adopts the preparation of APCVD or LPCVD method for predecessor, and its stress is less, and step coverage compares undoped silicon oxide
Preferably, and can flow under high temperature (such as 1000～1100 DEG C).And TEOS silicon oxide is with tetraethyl silicate resin (Si
(OC2H5)4, TEOS) as element silicon source the undoped silicon oxide for preparing of predecessor, such as with TEOS as predecessor
Prepared using middle temperature (650～800 DEG C) LPCVD or low temperature (250～450 DEG C) PECVD method, in addition can also be in APCVD
Ozone is added to be obtained in technique, but considering for film forming speed and quality in the present invention, it is preferred to use PECVD
Method prepares TEOS silicon oxide, and hereafter if no special instructions, will refer to, with TEOS, the oxygen being prepared by TEOS as predecessor
SiClx.False gate material layer 20 thickness a isAnd be preferablyFirst mask layer 31 thickness b isAnd preferablySecond mask layer 32 thickness c isAnd preferablyAdditionally, false grid material
Can also have the bed course (not shown) of silicon oxide, for etching protection substrate 10 during false grid between the bed of material 20 and substrate 10.Excellent
After selection of land, the first mask layer 31 and the second mask layer 32 growth complete, carry out unifying annealing to eliminate boundary defect and tune
Whole subsequent etching speed, for example, 800～900 DEG C and preferably 850 DEG C of annealing temperature, annealing time is for 10～60 minutes simultaneously preferably
30 minutes.
Referring next to Fig. 3, etching forms vertical hard mask figure wide up and down.Photoetching is applied on the second mask layer 32
Glue (not shown) exposure imaging formation photoetching offset plate figure, with photoetching offset plate figure as mask, using such as plasma etching
Dry etching, being sequentially etched the second mask layer 32 and the first mask layer 31 until exposing false gate material layer 20, forming hard mask
Figure, the line thickness of hard mask figure is, for example,And preferablyWherein, plasma etching gas
May include halogen-containing gas, for example, carbon fluorine base gas (CxHyFz), NF3、SF6、XeF2、BrF2Deng fluoro-gas, and Cl2、
Br2, other halogen-containing gas such as HBr, HC1, the oxidants such as oxygen, ozone, nitrogen oxides can also be included.Noticeable
Be, the first mask layer 31 and the second mask layer 32 material be all mainly silicon oxide and can in same etching technics together with schemed
Case, but can be by selecting different etching conditions and make the second mask layer 32 of top layer in plasma etching simultaneously
Do not completely remove, but remain with certain residual thickness d, d is for example, more than or equal toEtching complete after using going
The wet-cleaning such as ionized water or be passed through the dry method such as oxygen, fluorinated gas cleaning, completely remove etch product.
Referring next to Fig. 4, selective etch forms hard mask figure wide at the top and narrow at the bottom.According to the first and second mask layer materials
Matter is different and select appropriate etching liquid to come to mask layer optionally wet etching, form hard mask figure wide at the top and narrow at the bottom.
Inventor, according to the result of many experiments and data analysiss reasoning, draws PSG and TEOS in dilution HF aqueous solution (DHF) wet method
Corrosion rate difference under corrosion is very big：When in DHF HF: H2O=1: 50 (volume ratio, if no giving advice on the contrary below, all represents body
Long-pending ratio), etching liquid temp is when being 25 DEG C, the corrosion rate of the PSG for unannealed process for the DHF isAnd for warp
The corrosion rate crossing the PSG of above-mentioned annealing (finally preferred 850 DEG C, the annealing of 30min in such as Fig. 2) is reduced toDHF for the corrosion rate of TEOS of the PECVD preparation of unannealed process isFor through upper
The corrosion rate stating the TEOS of PECVD preparation of annealing is reduced toIn other words, before and after annealing DHF for
The etch rate ratio (also referred to as etching selection ratio) of PSG/TEOS brings up to 38.67 from 24.44, improves ratio up near
58.2%.Additionally, the result that different HF concentration, etching liquid temp and different annealing temperatures, time obtain is respectively provided with class
Like attribute, namely after completing above-mentioned unified annealing, DHF improves for the etching selection ratio of PSG/TEOS.Therefore at this
In inventive embodiments, using DHF for the first mask layer 31 and the second mask layer 32 wet etching, and preferably wet etching it
Before annealed to improve etching selection ratio.Because DHF is for the second of the false gate material layer 20 of silicon materials and such as TEOS
Mask layer 32 corrosion rate is very slow and the first mask layer 31 corrosion rate of for PSG is very fast, the line of the therefore first mask layer 31
Bar can horizontal indentation, formed as shown in Figure 4 similar to nut or T-shaped structure wide at the top and narrow at the bottom.Second mask layer 32 in Fig. 4
Line thickness be maintained as close or equal to the hard mask graphic width in Fig. 3, for example,And preferablyBut the line thickness of the first mask layer 31 is less than the line thickness of the second mask layer 32, for example lateral indentation
And it is only remainingIn other words, the second mask layer 32 has the cantilevered out part beyond the first mask layer 31, and left and right is eachValue
Obtain it is noted that working as HF: H in DHF2When O is more than 1: 50, such as when 1: 100, DHF drops quickly to for PSG corrosion rateTherefore by choice than consideration, HF: H in DHF2O is preferably less than equal to 1: 50.In the same manner similarly, do not hold
Row annealing directly can also be formed similar to nut or T-shaped structure wide at the top and narrow at the bottom thus implementing the present invention using DHF corrosion,
Simply etching selection ratio is high less than the preferred embodiment of the present invention, and etching effect is not excellent.
Referring next to Fig. 5, dry etching vacation gate material layer 20 forms false grid 21 wide at the top and narrow at the bottom.Using with etch hardmask
The same or similar dry etch process of figure, such as plasma etching, false gate material layer 20 is performed etching, until exposing
Substrate 10.In etching process, the cantilevered out part of the second mask layer 32, can be horizontal under the physical bombardment of etching process plasma
To shortening.With the horizontal shortening of the second mask layer 32, transverse shifting will be produced to the etching of false gate material layer 20；Thus in polycrystalline
After the completion of etching, the trapezoid vacation grid 21 with certain angle of inclination can be formed, see Fig. 5.The lines of the wherein second mask layer 32
Width has been less than the width in Fig. 4, the line substantially equal to or slightly larger than the first mask layer 31 in Fig. 4 due to the bombardment of plasma
Bar width, the such as first mask layer 31 line thicknessSecond mask layer 32 line thickness Similarly,
For the hard mask figure of above-mentioned other forms, as long as its top width is more than bottom width, top will be in plasma
Progressively indentation under bombardment, also will produce transverse shifting to the etching of false grid.
With reference to Fig. 6, it is the partial enlarged drawing of Fig. 5.After the completion of wet etching shown in Fig. 4, the first mask layer 31 of indentation
Outer wall and the second mask layer 32 outer wall stand out are away from for e, namely the width of cantilevered out part；After the completion of dry etching shown in Fig. 5,
Laterally reduce the distance as f；It can be seen that f ＜=e, wherein f can be adjusted on the basis of e according to dry etch process parameter,
I.e. the numerical value of f is together decided on by cantilevered out partial width and dry etch process；E example can put to the proof and be F example can put to the proof and beThe inclination alpha ultimately forming=arctan f/a；In conjunction with a it is Gained α is 2.86 degree.As can be seen here, as long as controlling
Wet method lateral erosion the first mask layer 31 and the speed of dry etching vacation gate material layer 20, namely control e and f, you can control final
The angle of inclination of the trapezoid vacation grid 21 being formed, preferably α is less than or equal to 10 degree in the present invention.
Referring next to Fig. 7, remove hard mask figure.Get rid of firmly covering of false grid 20 top remaining using wet corrosion technique
Mould figure, obtains trapezoid vacation grid 21, sees Fig. 7.Using chemical liquids can be HF base chemical liquids, such as DHF or BOE, can put to the proof
For DHF concentration ratio HF: H2O=1: 100 (volume ratios), technological temperature can be put to the proof as 25 DEG C.It should be noted that herein
DHF corrosive liquid is different from the DHF of the first mask layer of selective corrosion in Fig. 4 31, due to being intended merely to quickly remove hard mask
Without considering that optimizing corrosion selects ratio, therefore DHF concentration and temperature can need Reasonable adjustment according to technique to structure.Wet method is rotten
After the completion of etching technique, wafer is carried out and is dried.
The side wall growth, side wall etching and the follow-up false grid that then carry out routine remove technique, for example with as above institute
The manufacture method of the false gate in back gate process stated, forms false grid wide at the top and narrow at the bottom on substrate；Form side wall in false grid both sides；Move
Except false grid, form gate groove wide at the top and narrow at the bottom；Filling gate insulator and grid material in gate groove.Finally give under width
Narrow trapezoid gate groove, thus be beneficial to the high K of next step or the filling of metal gate material.It is permissible that wherein false grid remove technique
Carried out using dry etching or wet etching or dry etching+wet etching hybrid technique.
According to the false grid manufacture method of the present invention, false grid vertical before are fabricated to trapezoid vacation grid wide at the top and narrow at the bottom；
After false grid are removed, trapezoid groove can be formed；Thus greatly facilitating subsequently high K or the filling of metal gate material, expand
Big fill process window, thus improve the reliability of device.
Although the present invention is described with reference to one or more exemplary embodiments, those skilled in the art could be aware that need not
Depart from the scope of the invention and device architecture is made with various suitable changes and equivalents.Additionally, can by disclosed teaching
Make many and can be adapted to the modification of particular condition or material without deviating from the scope of the invention.Therefore, the purpose of the present invention does not exist
In being limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture
And its all embodiments that manufacture method will include falling within the scope of the present invention.
Claims (9)
1. a kind of manufacture method of false gate in back gate process, comprises the following steps：
The layer of hard mask material of false gate material layer, multiple structure, wherein the hard mask material of multiple structure are sequentially formed on substrate
The bed of material includes first mask layer of PSG and the second mask layer of TEOS silicon oxide；
Using dry method and DHF wet method etch hard mask materials layer respectively, formation hard mask figure wide at the top and narrow at the bottom, wherein formation
In hard mask figure wide at the top and narrow at the bottom, the second mask layer has the cantilevered out part than the first mask slice width；
With hard mask figure as mask, dry etching vacation gate material layer, form false grid wide at the top and narrow at the bottom.
2. method as claimed in claim 1, wherein, adjusts the thickness of cantilevered out partial width and false gate material layer to control false grid
Inclination angle.
3. method as claimed in claim 2, wherein, the inclination angle of false grid is less than or equal to 10 degree.
4. method as claimed in claim 1, wherein, TEOS silicon oxide adopts PECVD method to prepare with TEOS for predecessor.
5. method as claimed in claim 1, wherein, HF in DHF wet etching liquid:H2The volume ratio of O is less than or equal to 1:50.
6. method as claimed in claim 1, wherein, before using DHF wet etching layer of hard mask material, also includes to hard mask
Material layer is annealed.
7. method as claimed in claim 6, wherein, annealing temperature is 800～900 DEG C, and annealing time is 10～60 minutes.
8. method as claimed in claim 1, wherein, false gate material layer includes polysilicon, non-crystalline silicon or microcrystal silicon, and substrate includes list
Crystal silicon, SOI, monocrystalline germanium, GeOI, SiGe, SiC, InSb, GaAs or GaN.
9. a kind of rear grid technique, including step：
Using the manufacture method of false gate in back gate process as claimed in claim 1, false grid wide at the top and narrow at the bottom are formed on substrate；
Form side wall in false grid both sides；
Remove false grid, form gate groove wide at the top and narrow at the bottom；
Filling gate insulator and grid material in gate groove.
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| CN104576373B (en) * | 2013-10-11 | 2018-04-06 | 中国科学院微电子研究所 | Afterwards in grid technique pseudo- gate device and semiconductor devices forming method |
| CN106435721A (en) * | 2016-09-22 | 2017-02-22 | 东莞市联洲知识产权运营管理有限公司 | GaAs/Si epitaxial material preparation method |
| CN113327979B (en) * | 2020-02-28 | 2023-04-18 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241026A (en) * | 1998-06-25 | 2000-01-12 | 西门子公司 | Improved SAC process flow method using isolating spacer |
| CN101101956A (en) * | 2006-07-03 | 2008-01-09 | 富士通株式会社 | Method of manufacturing pattern |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6562671B2 (en) * | 2000-09-22 | 2003-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device and manufacturing method thereof |
| US7718479B2 (en) * | 2004-08-25 | 2010-05-18 | Intel Corporation | Forming integrated circuits with replacement metal gate electrodes |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241026A (en) * | 1998-06-25 | 2000-01-12 | 西门子公司 | Improved SAC process flow method using isolating spacer |
| CN101101956A (en) * | 2006-07-03 | 2008-01-09 | 富士通株式会社 | Method of manufacturing pattern |
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