CN103166438A - Mixed random space voltage vector pulse width modulation method and modulator based on field programmable gate array (FPGA) - Google Patents

Abstract

The invention relates to a mixed random space voltage vector pulse width modulation method and a modulator based on a field programmable gate array (FPGA). According to the method, action time and pulse and pulse positioning of a basic voltage sector are controlled by two random variables, one of the two random variables is used for controlling the action time of the basic voltage vector by controlling distribution proportion of action time of two zero vectors, and the other random variable is used for performing pulse positioning by controlling the position of the widest high-level pulse. The modulator comprises a period register, a dead zone register, two groups of hop time registers, a counting and initial value reloading circuit, a register switching circuit and a pulse generation circuit, and an asymmetrical control pulse is generated through alternative comparison of the two groups of hop time registers. By the modulation method and the modulator, mechanical vibration, audio-frequency noise, electromagnetic radiation and the like due to a large peak value of a discrete set cluster spectrum are obviously avoided on the premise that fundamental wave voltage and switching frequency do not change.

Description

Mixing stochastic space voltage vector pulse duration modulation method reaches the modulator based on FPGA

Technical field

The invention belongs to the alternating frequency conversion technique field, be specifically related to a kind of mixing stochastic space voltage vector pulse duration modulation method that can reduce the harmonic wave peak value and based on the modulator of FPGA.

Background technology

That inverter as shown in Figure 1 has is simple in structure, realize the advantages such as convenient, is widely used in the occasion of the frequency controls such as electric automobile driving.The pulse-width modulation (PWM) of adopting is based on the principle of " volt-second balance ", comes equivalent command voltage with the potential pulse of the continuous conversion of duty ratio according to time average.The essence of modulation strategy is to calculate 6 path switching signal high-low level jumping moments of inverter needs according to command voltage with certain algorithm, produces 6 road pulse signals with logical circuit, then removes to open or close power switch pipe by drive circuit.Sine pulse width modulation (PWM) (SPWM) is a kind of very ripe, very classical three-phase PWM, and the fundamental voltage amplitude that can export is half of DC bus-bar voltage.The essence of space voltage vector PWM (SVPWM) is to have injected three times of subharmonic on the modulating wave of SPWM, thereby has improved the utilance of direct voltage, compares with SPWM and has improved approximately 15.4%.Its motor and inverter are regarded integral body as, to obtain loop circle flux as target, have that the busbar voltage utilance is high, harmonic characterisitic good, facilitate the advantage such as numerical control system realization, occupy dominant position at present in the conversion speed governing digital control system.

Prior art pulse duration modulation method commonly used is:

Two switching tubes in every phase up and down become complementary conducting.Different on off states can form 8 basic voltage vectors, comprise 6 non-zero basic voltage vectors (

) and 2 Zero voltage vectors (

), as shown in Figure 2.In figure: 1 expression upper arm conducting, 0 expression underarm conducting.

6 non-zero basic voltage vectors are

${\stackrel{\→}{U}}_k=\frac{2}{3}(u_{\mathrm{AN}}+{\mathrm{\αu}}_{\mathrm{BN}}+{\mathrm{\α}}^2{u}_{\mathrm{CN}})=\frac{2}{3}{U}_{\mathrm{DC}}{e}^{j(k-1)\frac{\mathrm{\π}}{3}}(k=\mathrm{1,2},...,6)---\left(1\right)$

In formula: u _AN, u _BN, u _CNBe three-phase voltage the neutral point N of load (when load is delta connection with respect to).

Any one voltage vector in the hexagon inscribed circle that the end points with 6 non-zero basic voltage vectors forms

${\stackrel{\→}{U}}_s=U_o{e}^{\mathrm{j\θ}}---\left(2\right)$

In formula: U _oAmplitude for voltage vector; θ is the phase angle of voltage vector.

Can be synthesized according to the principle of " volt-second balance " by contiguous two basic voltage vectors and Zero voltage vector.As shown in Figure 2, take 1. the sector as example,

Action time be T _s(carrier cycle is also referred to as modulation period, switch periods), T _SV1, T _SV2By the synthetic parallelogram law of vector,

$T_s{\stackrel{\→}{U}}_s=T_{\mathrm{SV}1}{\stackrel{\→}{U}}_1+T_{\mathrm{SV}2}{\stackrel{\→}{U}}_2---\left(3\right)$

Can get

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\&pi;}}{3}-\mathrm{\&theta;})\\ {\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\&theta;}\end{array}\right.---\left(4\right)$

${\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}+{\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\&pi;}}{3}+\mathrm{\&theta;})---\left(5\right)$

In formula: U _oAmplitude for the command voltage vector; θ is the phase angle of command voltage vector; U _DCBe direct voltage.

Other time need to be by Zero voltage vector

With

Next additional, be its action time

T _SV0＝T _s-T _SV1-T _SV2 (6)

As long as make the relational expression above satisfying two non-zero basic voltage vectors action times and two Zero voltage vector effect total times, can satisfy the voltage equivalence on average meaning.Space vector pulse width modulation has only been stipulated the time of basic voltage vectors effect, does not stipulate order and the distribution of its effect.Usually adopt symmetrical type of action as shown in Figure 3, namely

${\stackrel{\&RightArrow;}{U}}_0\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_7\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_0---\left(7\right)$

Two Zero voltage vectors

With

Action time be respectively

$T_{\mathrm{SV}00}=T_{\mathrm{SV}07}=\frac{{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}}{2}---\left(8\right)$

Be based on the basic principle of " volt-second balance " due to pulse-width modulation, when obtaining the fundamental voltage that needs, inevitably bring harmonic wave.Harmonic wave brings energy loss, causes that the motor feels hot; Low-frequency harmonics can also cause torque pulsation, and then causes mechanical oscillation, causes audible noise.Although improving modulating frequency (also referred to as switching frequency, carrier frequency) can improve, and can reduce audible noise if particularly modulating frequency is brought up to more than 18kHz, high switching frequency must increase switching loss.Precipitous pulse also causes serious electromagnetic interference, affects the normal operation of other electronic equipments.Particularly fixed switching frequency has caused switching frequency integral multiple and near harmonic wave to have larger amplitude; Two fixing zero vector methods of salary distribution action time, symmetrical high level arrangement have aggravated the peak value of collection bunch harmonic wave, can increase the weight of electromagnetic interference etc.

Therefore, how when obtaining required fundamental voltage, reduce the ill effects such as mechanical oscillation that the large peak value of discrete set bunch frequency spectrum brings, audible noise, electromagnetic radiation and be one and expect the problem that solves.

Summary of the invention

The object of the invention is to propose a kind of equipment that mixes stochastic space voltage vector pulse duration modulation method and adopt the method, to reduce the certainty Using dSPACE of SVPWM collection bunch problem that the harmonic spectrum peak value brings, with concentrate on the modulating frequency multiple and near collection bunch frequency spectrum launch to weaken, the ill effects such as noise that can harmonic reduction causes under lower switching frequency.

In order to achieve the above object, the invention provides a kind of mixing stochastic space voltage vector pulse duration modulation method, control action time and the pulse of basic voltage vectors locates by two stochastic variables, concrete control mode is, one of them stochastic variable is controlled the action time of basic voltage vectors by the allocation proportion of controlling two zero vector action times, another stochastic variable is carried out the pulse location by the position of controlling the widest pulse of high level, and described two stochastic variables are presented as random number R ₁And R ₂

Described mixing stochastic space voltage vector pulse duration modulation method, when for the voltage vector pulse-width modulation under formula (7) seven segmentation type of action, action time and the pulse position of two basic Zero voltage vectors are subject to random number R ₁And R ₂Control, specifically comprise the steps:

S1: according to the command voltage vector of controller output, 1. distinguish as example take the action time of calculating two adjacent basic voltage vectors and Zero voltage vector, formula is

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\&pi;}}{3}-\mathrm{\&theta;})\\ {\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\&theta;}\\ {\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula: T _sBe carrier cycle (modulation period, switch periods), T _SV1, T _SV2Be the action time of two adjacent basic voltage vectors, T _SV0Be the action time of Zero voltage vector, U _oBe the amplitude of command voltage vector, θ is the phase angle of command voltage vector, U _DCBe direct voltage;

S2: be created on random number R on interval [0,1] according to the probability distribution of setting ₁

S3: calculate Zero voltage vector

With

T action time _SV00And T _SV07, formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}\right.---\left(10\right);$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, generate random number R in the type of probability distribution and step S2 ₁Probability distribution used is separate;

S5: calculate seven segmentation type of action as shown in Figure 4, that is,

${\stackrel{\&RightArrow;}{U}}_0\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_7\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_0---\left(7\right)$

T action time of every this voltage vector of segment base ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇Be respectively:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_1=R_2{T}_{\mathrm{SV}00}\\ {\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_2={\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="3"\; label="T"\; filenames="HDA00003009892500012.png,HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_3={\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="4"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_4=T_{\mathrm{SV}07}\\ {\mathrm{<figure-callout\; id="5"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_5={\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ T_6={\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="7"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right);$

S6: calculate 6 road impulse hits constantly, and then the value of counter register variable, by logic electric current production burst signal.

Further, in described step S3, random number R ₂Scope need satisfy following condition, further to determine random number R ₂Scope, formula is:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_1\&le;\frac{1}{2}{T}_{\mathrm{SV}0}\\ {\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_1+{\mathrm{<figure-callout\; id="4"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_4\&GreaterEqual;\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.---\left(12\right)$

Or

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="7"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_7\&le;\frac{1}{2}{T}_{\mathrm{SV}0}\\ {\mathrm{<figure-callout\; id="4"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_4+{\mathrm{<figure-callout\; id="7"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_7\&GreaterEqual;\frac{1}{2}{T}_{\mathrm{SV}0}\end{array}\right.---\left(13\right)$

Formula (12) arranges and can get

$\left\{\begin{array}{c}{R}_2{R}_1{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\&le;\frac{1}{2}{T}_{\mathrm{SV}0}\\ R_2{R}_1{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}+(1-R_1){\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\&GreaterEqual;\frac{1}{2}{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\end{array}\right.$

Arrange again and can get

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&le;\frac{1}{{2R}_1}\\ {\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&GreaterEqual;1-\frac{1}{{2R}_1}\end{array}\right.---\left(14\right)$

Formula (13) arranges and can get

$\left\{\begin{array}{c}(1-R_2)R_1{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\&le;\frac{1}{2}{T}_{\mathrm{SV}0}\\ (1-R_1){\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}+(1-R_2)R_1{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\&GreaterEqual;\frac{1}{2}{\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}\end{array}\right.$

Arrange again and can get

$\left\{\begin{array}{c}(1-R_2){\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&le;\frac{1}{2}\\ 1-{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&GreaterEqual;1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\end{array}\right.$

Variable being changed to

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&GreaterEqual;1-\frac{1}{{2R}_1}\\ {\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&le;\frac{1}{{2R}_1}\end{array}\right.---\left(15\right)$

Formula (14) is actually a formula with (15), namely

$1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\&le;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&le;\frac{1}{{2R}_1}---\left(16\right)$

Random number R ₂Residing interval is [K ₁, K ₂], wherein

${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\left\{\begin{array}{cc}0& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&le;\frac{1}{2}\\ 1-\frac{1}{{2R}_1}& R_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

${\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">K</figure-callout>}}_2=\left\{\begin{array}{cc}1& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&le;\frac{1}{2}\\ \frac{1}{{2R}_1}& R_1>\frac{1}{2}\end{array}\right.---\left(18\right)$

Further, in described step S2 and S4, random number R ₁And random number R ₂The generation formula that can generate with pseudo random number, produce in real time by software programming and realize; Can be also that 0～1 pseudo random number table is stored in read-only memory with span, then random number is transformed to required scope from 0～1 generate random number.

Mixing stochastic space voltage vector pulse duration modulation method provided by the invention, break in traditional certainty modulator approach the characteristics that two zero vector methods of salary distribution action time and high level pulse are arranged symmetrically with, weakened the large peak value of collection bunch harmonic wave of certainty space voltage vector pulse width modulation method.The present invention controls action time of basic voltage vectors and pulse location by two random numbers, and random number is controlled the allocation proportion of two zero vector action times, the location of another random number control impuls.Be the zero moment to be in Zero voltage vector in order to make current deviation In the time period of effect, to two the Zero voltage vector action times of limited field all.

In order to solve the technical problem of electric machine phase current sampling in the frequency conversion speed-adjusting system closed-loop control, the phase current sampling method of described mixing stochastic space voltage vector pulse duration modulation method is: the moment of phase current sampling is set in the mid point of modulation period, i.e. each modulation period

The place is as the moment of square frame institute mark in Fig. 5 (b).

Further, in order to improve the precision of current measurement, can make the moment that current sample is avoided impulse hits constantly be subject to the measurement of avoiding electric current the impact that impulse hits disturbs, current sample has a S interval at least constantly with impulse hits constantly.According to the requirement of control system to the current sample error, observe by experiment impulse hits to the influence of peak current, and then determine time-delay S.First inequality of formula (12) and formula (13) the right needs to deduct a time-delay S, second inequality the right needs to add a time-delay S, carries out current measurement after impulse hits finishes again, and needs this moment recomputate random number R according to formula (12)-(15) ₂Span.Formula (16) becomes

$1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}+\frac{\mathrm{\&lambda;}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\&le;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&le;\frac{1}{{2R}_1}-\frac{\mathrm{\&lambda;}}{R_1}---\left(19\right)$

In formula: $\mathrm{\&lambda;}=\frac{\mathrm{<figure-callout\; id="0"\; label="S\; T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">S</figure-callout>}}{T_{\mathrm{SV}}}.$

At this moment, random number R ₂Residing interval is [K ₁, K ₂], wherein

${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\max \{1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}+\frac{\mathrm{\&lambda;}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1},0\}---\left(20\right)$

${\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">K</figure-callout>}}_2=\min \{\frac{1}{{2R}_1}-\frac{\mathrm{\&lambda;}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1},1\}---\left(21\right)$

The symmetry of pulse has been broken in randomization in the present invention, and the pulse that present generally popular digital control chip can't produce asymmetric waveform.Therefore, in order to achieve the above object, the present invention also provides a kind of modulator based on FPGA, and what it adopted is that above-mentioned any mixes stochastic space voltage vector pulse duration modulation method, and it is installed in the circuit of frequency conversion speed-adjusting system, mainly comprises:

(1) register district, it comprises two jumping moment register groups, one-period register, a dead band register.The one-period register is used for depositing modulation period; A dead band register is used for setting Dead Time.Two jumping moment register groups, every group has 6 registers, the moment of depositing every phase upper arm impulse hits in these 12 registers.The moment of underarm impulse hits is determined jointly by upper arm jumping moment corresponding register and dead band register.There are two registers to control the A phase in every group, control the forward position for one, edge after another is controlled; There are two registers to control the B phase in every group, control the forward position for one, edge after another is controlled; There are two registers to control the C phase in every group, control the forward position for one, edge after another is controlled.Two groups are used alternatingly the generation control impuls, if use first group of register a upper modulation period, this cycle is used second group, and the lower cycle will be used first group.

Count and initial value heavy cartridges circuit for (2) one, its Counter is accepted count pulse and is subtracted 1 counting according to pulse.When counter reduces to 0, then subtract 1 when overflowing, the pulse of output spill over is controlled from the period register counting initial value of reloading, and begins the counting in next cycle.D type flip flop is sent into again in the spill over pulse.The currency of counter send the comparator bank of pulse-generating circuit.

(3) register group commutation circuit, it comprises a d type flip flop and variable connector.This circuit is accepted the spill over from counter, controls two groups of registers alternately by variable connector, and send the comparator bank of pulse-generating circuit.

(4) pulse-generating circuit comprises a comparator bank and d type flip flop group.Its effect is: the currency of counter and impulse hits set point constantly compared, if identical, impulse hits.The saltus step of pulse realizes by the d type flip flop in the d type flip flop group.When every phase upper arm compares, directly with the value of corresponding registers, underarm needs the value addition of the value of corresponding register and dead band register or participates in relatively after subtracting each other again, and with the generation dead band, avoids the time-delay of opening and turn-offing of switching tube to cause underarm straight-through.

Aspect realizing based on the hardware of FPGA, the present invention alternately participates in relatively realizing the generation of random pulses by two register groups that make the control impuls jumping moment.The function of at present popular control chip is all the modulator approach that is arranged symmetrically with for pulse, i.e. the same along participating in register assignment relatively before and after pulse, can't realize mixing random space vector pulse duration modulation method provided by the invention.Main thought of the present invention is: at current period, the jumping moment register that does not participate in comparison is carried out assignment; Finish (the lower cycle begins) constantly at current period, two groups of buffer status switch, and compare in the jumping moment register participation of current period assignment, and current period participates in jumping moment register group relatively and becomes not relatively state, for assignment is prepared.The method thinking is novel, and simple in structure, the speed of service is fast.

The beneficial effect of method of the present invention and modulator is:

(1) method of the present invention can significantly reduce in constant prerequisites such as guaranteeing fundamental voltage, on-off times the large peak value of certainty space vector width pulse modulation method collection bunch harmonic wave that generally adopts;

(2) perception is accounted for the frequency conversion speed-adjusting system of leading load, the mid point of modulation period phase current deviation constantly is approximately zero, and method of the present invention is sampled by the mid point in modulation period, has improved control precision and the effect of system;

(3) modulator of the present invention can take full advantage of FPGA circuit customization characteristics flexibly, and other circuit and the algorithm of governing system is integrated in a FPGA;

(4) modulator of the present invention utilizes the executed in parallel characteristic of FPGA to improve and controls the speed that software is carried out, and is the mutual fusion of advanced control algorithm and modulation algorithm more, with and application in frequency conversion speed-adjusting system guarantee is provided.

Description of drawings

Fig. 1 is two level three-phase inverters and motor method of attachment schematic diagram;

Fig. 2 is basic voltage vectors and synthetic method schematic diagram;

Fig. 3 is the 7 sections type of action schematic diagrames of symmetrical expression that generally adopt;

Fig. 4 is 7 sections type of action schematic diagrames that the present invention adopts;

Fig. 5 is phase voltage, current deviation, sampling instant and the upper arm control signal figure of the embodiment of the present invention, 5(a wherein) be A phase voltage figure, 5(b) be A phase current deviation and sampling instant figure, 5(c) be the switching signal figure of A phase upper arm, 5(d) be switching signal figure, the 5(e of B phase upper arm) be the switching signal figure of C phase upper arm;

Fig. 6 is the flow chart of pulse duration modulation method provided by the invention;

Fig. 7 is an application scheme schematic diagram of the present invention;

Fig. 8 is the logical circuitry of modulator of the present invention;

Fig. 9 is 6 road method for generating pulse figure of the present invention;

Figure 10 is the spectrogram of 7 sections type of action modulator approach phase voltages of symmetrical expression of generally adopting;

Figure 11 is the spectrogram of embodiment of the present invention phase voltage, wherein 11(a) and 11(b) be that the A phase voltage pulse of inverter output was sampled within two different primitive periods, carry out the amplitude spectrum that Fourier transform obtains.

[main element symbol description]

1---the register district; 2---counting and initial value heavy cartridges circuit;

3---register group commutation circuit; 4---pulse-generating circuit;

11---register group 1; 12---register group 2;

13---period register; 14---dead band register

21---counter; 22---the heavy cartridges circuit;

31---d type flip flop; 32---variable connector;

41---comparator bank; 42---the d type flip flop group;

111---register 1; 112---register 3;

113---register 5; 114---register 7;

115---register 9; 116---register 11;

121---register 2; 122---register 4;

123---register 6; 124---register 8;

125---register 10; 126---register 12.

Embodiment

For making purpose of the present invention, technical scheme and beneficial effect clearer, the below will the present invention is described in further detail by execution mode.

The invention provides and a kind ofly mix stochastic space voltage vector pulse duration modulation method and based on the modulator of FPGA, the structure of its inverter as shown in Figure 1.Modulator provided by the invention can be installed between the controller and isolated drive circuit of frequency conversion speed-adjusting system, also itself and controller can be integrated in a FPGA, as shown in Figure 7.

At first enforcement of the present invention need the command voltage vector according to controller output, calculates the time of adjacent two basic voltage vectors, Zero voltage vector effect, and then calculate the moment of impulse hits, and implementation step is as shown in Figure 6, and is specific as follows:

S1: according to the command voltage vector of controller output, 1. distinguish as example take the action time of calculating two adjacent basic voltage vectors and Zero voltage vector, formula is

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\&pi;}}{3}-\mathrm{\&theta;})\\ {\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\&theta;}\\ {\mathrm{<figure-callout\; id="0"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula: T _sBe carrier cycle (modulation period, switch periods); T _SV1, T _SV2, T _SV0It is the action time of two adjacent basic voltage vectors and Zero voltage vector; U _oAmplitude for the command voltage vector; θ is the phase angle of command voltage vector; U _DCBe direct voltage.

S2: be created on random number R on interval [0,1] according to the probability distribution of setting ₁

S3: calculate Zero voltage vector

With

T action time _SV00And T _SV07, formula is

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}---\left(10\right)\right.$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, generate random number R in the type of probability distribution and step S2 ₁Probability distribution used is separate;

S5: calculate seven segmentation type of action as shown in Figure 4, namely

${\stackrel{\&RightArrow;}{U}}_0\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_7\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_0---\left(7\right)$

T action time of every this voltage vector of segment base ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇For

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_1=R_2{T}_{\mathrm{SV}00}\\ {\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_2={\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="3"\; label="T"\; filenames="HDA00003009892500012.png,HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_3={\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="4"\; label="T"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_4=T_{\mathrm{SV}07}\\ {\mathrm{<figure-callout\; id="5"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_5={\mathrm{<figure-callout\; id="2"\; label="T\; SV"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ T_6={\mathrm{<figure-callout\; id="1"\; label="T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">T</figure-callout>}}_{\mathrm{SV}}/2\\ {\mathrm{<figure-callout\; id="7"\; label="T"\; filenames="HDA00003009892500052.png"\; state="\{\{state\}\}">T</figure-callout>}}_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right)$

S6: calculate 6 road impulse hits constantly, and then the value of counter register variable, by logic electric current production burst signal.

Further, in described step S4, random number R ₂Scope need satisfy following condition

$1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\&le;{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&le;\frac{1}{{2R}_1}---\left(16\right)$

Stochastic variable R ₂Residing interval is [K ₁, K ₂], wherein

${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\left\{\begin{array}{cc}0& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&le;\frac{1}{2}\\ 1-\frac{1}{{2R}_1}& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

${\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">K</figure-callout>}}_2=\left\{\begin{array}{cc}1& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&le;\frac{1}{2}\\ \frac{1}{{2R}_1}& {\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1>\frac{1}{2}\end{array}\right.---\left(18\right)$

During the S2 of above-mentioned embodiment and S4 go on foot, random number R ₁And R ₂The value formula that can generate with pseudo random number, produce in real time by software programming and realize; Can be also that pseudo random number table on 0～1 is stored in read-only memory with span, pointer is set in program, read pseudo random number by the movement of pointer.

To random number R ₂, random number need to be transformed to interval [K from 0～1 ₁, K ₂] on, can adopt linear transformation as follows

R ₂＝K ₁+(K ₂-K ₁)x （22）

In formula: x is the random number on 0～1.

In order to solve the technical problem of electric machine phase current sampling in the frequency conversion speed-adjusting system closed-loop control, the phase current sampling method that adopts in mixing stochastic space voltage vector pulse duration modulation method of the present invention is: the moment of phase current sampling is set in the mid point of modulation period, i.e. each modulation period The place, the moment as shown in square frame in Fig. 5 (b).

If system voltage is higher, the measurement of considering electric current is subject to that impulse hits disturbs and affects, and current sample is avoided the moment of impulse hits constantly, and current sample has a S interval at least constantly with impulse hits constantly.According to the requirement of control system to the current sample error, observe by experiment impulse hits to the influence of peak current, and then determine time-delay S.

At this moment, random number R ₂Residing interval is [K ₁, K ₂], wherein

${\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">K</figure-callout>}}_1=\max \{1-\frac{1}{{2\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}+\frac{\mathrm{\&lambda;}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1},0\}---\left(20\right)$

${\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HDA00003009892500011.png,HDA00003009892500021.png"\; state="\{\{state\}\}">K</figure-callout>}}_2=\min \{\frac{1}{{2R}_1}-\frac{\mathrm{\&lambda;}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">R</figure-callout>}}_1},1\}---\left(21\right)$

In formula: $\mathrm{\&lambda;}=\frac{\mathrm{<figure-callout\; id="0"\; label="S\; T\; SV"\; filenames="HDA00003009892500021.png,HDA00003009892500022.png"\; state="\{\{state\}\}">S</figure-callout>}}{T_{\mathrm{SV}}}.$

In conjunction with Fig. 8, the modulator based on FPGA provided by the invention, it comprises:

A register district (1), it comprises two jumping moment register groups: register group 1(11) and register group 2(12), one-period register (13), a dead band register (14).Period register (13) is used for depositing modulation period, and dead band register (14) is used for setting Dead Time.Register group 1(11) and register group 2(12) every group 6 registers are arranged, the moment of depositing every phase upper arm impulse hits in these 12 registers.The moment of underarm impulse hits is by upper arm jumping moment corresponding register and the common decision of dead band register (14).Have two registers to control the A phase in every group, one of them controls the forward position, edge after another is controlled; Have two registers to control the B phase in every group, one of them controls the forward position, edge after another is controlled; Have two registers to control the C phases in every group, one wherein controls the forward position, edge after another is controlled.Two groups are used alternatingly the generation control impuls, if use register group 1(11 a upper modulation period), this cycle is used register group 2(12), next cycle is used register group 1(11).

In conjunction with Fig. 8 and Fig. 9, register group 1(11) the register 1(111 in) control the forward position of A phase upper arm, register 3(112) control the rear edge of A phase upper arm; Register 5(113) control the forward position of B phase upper arm, register 7(114) control the rear edge of B phase upper arm; Register 9(115) control the forward position of C phase upper arm, register 11(116) control the rear edge of C phase upper arm.

Register group 2(12) the register 2(121 in) control the forward position of A phase upper arm, register 4(122) control the rear edge of A phase upper arm; Register 6(123) control the forward position of B phase upper arm, register 8(124) control the rear edge of B phase upper arm; Register 10(125) control the forward position of C phase upper arm, register 12(126) control the rear edge of C phase upper arm.

Count and initial value heavy cartridges circuit (2) for one, its Counter (21) has an input and 2 outputs, and input line connects count pulse and subtracts 1 counting according to pulse; An output line is exported current count value, connects an input line of comparand register group (41) in pulse-generating circuit (4); Another output line output spill over when counter reduces to 0, then subtracts 1 when overflowing, and the pulse of output spill over is controlled heavy cartridges circuit (22) from period register 14(13) the counting initial value of reloading, begin the counting in next cycle.The input pin CP of d type flip flop (31) is sent into again in the spill over pulse.The currency of counter (21) send the comparator bank (41) of pulse-generating circuit (4).Heavy cartridges circuit (22) has 2 inputs and an output, and an input line connects the spill over of counter (21), and another input meets period register 14(13), output line connects counter (21).

Register group commutation circuit (3), it comprises a d type flip flop (31) and variable connector (32).This circuit is accepted the spill over from counter (21), controls two groups of registers alternately by variable connector (32), and send the comparator bank (41) of pulse-generating circuit (4).Variable connector (32) has 3 input and outputs, and its 2 inputs meet respectively register group 1(11) and register group 2(12); Another inputs position control end, meets the output Q of d type flip flop (31); Output line connects the input line of the comparator bank (41) of pulse-generating circuit (4).The output Q of d type flip flop (31) connects the control end of variable connector (32); The anti-phase output Q of d type flip flop (31) meets input D, realizes that the rising edge of a pulse of CP makes the output Q saltus step of d type flip flop (31) and keeps.Pulse-generating circuit (4) comprises a comparator bank (41) and d type flip flop group (42).Its effect is: the currency of counter (21) and impulse hits set point constantly compared, if identical, impulse hits.D type flip flop group (42) has comprised 6 d type flip flop groups, corresponds respectively to 6 tunnel pulses.6 comparators have been comprised in comparator bank (41), wherein 3 comparators are corresponding to the upper arm of three-phase, each has 3 inputs and an output, these four inputs connect respectively: the currency output line of counter (21), the pulse front edge jumping moment register (three-phase is respectively register 1(111) of variable connector (32) output, register 5(113), register 9(115) or register 2(121), register 6(123), register 10(125)), rear jumping moment register (three-phase is respectively register 3(112), register 7(114), register 11(116) or register 4(122), register 8(124), register 12(126)), wherein 3 comparators are corresponding to the underarm of three-phase, each has 4 inputs and an output, these four inputs connect respectively: the currency output line of counter (21), the pulse front edge jumping moment register (three-phase is respectively register 1(111) of variable connector (32) output, register 5(113), register 9(115) or register 2(121), register 6(123), register 10(125)), rear jumping moment register (three-phase is respectively register 3(112), register 7(114), register 11(116) or register 4(122), register 8(124), register 12(126)), dead band register 13(14).

When comparing, every phase upper arm directly uses the value of corresponding registers, underarm needs the value addition of the value of corresponding register and dead band register (14) or participates in relatively after subtracting each other again, to produce the dead band, avoid the time-delay of opening and turn-offing of switching tube to cause underarm straight-through.The saltus step of pulse realizes by d type flip flop group (42).

The figure place of above-mentioned related register, comparator can be 16,32 or other, need to select according to the concrete row such as model of modulation period, FPGA.

Modulator approach provided by the invention and circuit can realize having on the market on numerous FPGA, the FPGA that produces as companies such as Altera, Xilinx, Lattice.

Be that 40Hz(is that motor stator voltage angle frequency is 80 π rad/s in the fundamental voltage frequency), the pwm switch frequency is 2000Hz, modulation ratio is to implement the present invention under 0.6 condition, and Fig. 5 is phase voltage, current deviation, sampling instant and the upper arm control signal figure of the embodiment of the present invention.As shown in Fig. 5 (b), in the beginning of modulation period, the phase current deviation is zero; Constantly, the deviation of phase current is also zero in the middle of modulation period, carves at this moment and carries out current sample, measures phase current and can reduce measure error.

Figure 10 is the amplitude spectrum of 7 sections type of action modulator approach phase voltages of symmetrical expression of generally adopting, and Figure 11 is the amplitude spectrum of embodiment of the present invention phase voltage.As shown in figure 11, the peak value at switching frequency integral multiple place collection bunch harmonic wave is very large; As shown in Figure 11 (a) and Figure 11 (b), mixing investigation of random PWM method provided by the invention can greatly reduce the peak value of switching frequency integral multiple place collection bunch harmonic wave.

The characteristics of method of the present invention and modulator are:

(1) the present invention is guaranteeing to have proposed under the constant prerequisite such as fundamental voltage, on-off times to mix method of randomization and based on the modulator of FPGA, can significantly reduce the large peak value of certainty space vector width pulse modulation method collection bunch harmonic wave that generally adopts;

(2) perception is accounted for the frequency conversion speed-adjusting system of leading load, at the mid point of modulation period, the phase current deviation is approximately zero, carves at this moment and samples, and has improved control precision and the effect of system;

(3) the present invention can take full advantage of FPGA circuit customization characteristics flexibly, and other circuit and the algorithm of governing system is integrated in a FPGA;

(4) the executed in parallel characteristic of FPGA has improved the speed of controlling the software execution, be the mutual fusion of advanced control algorithm and modulation algorithm more, and the application in frequency conversion speed-adjusting system provides guarantee.

Application of the present invention, solved the large spike problem of certainty SVPWM collection bunch harmonic wave, can improve Electro Magnetic Compatibility, reliability, the man-machine friendly of system, opened up the new SVPWM strategy of a class, make the purposes of space vector pulse width modulation more extensive, also can support better the development of the industries such as China's electric automobile, wind power generation, have good society and economic benefit.

The above; it is only preferred embodiment of the present invention; be not that the present invention is done any pro forma restriction, simple modification, equivalent variations or modification that those skilled in the art utilize the technology contents of above-mentioned prompting to make all drop in protection scope of the present invention.

Claims (10)

1. one kind is mixed stochastic space voltage vector pulse duration modulation method, it is characterized in that, control action time and the pulse of basic voltage vectors locates by two stochastic variables, concrete control mode is, one of them stochastic variable is controlled the action time of basic voltage vectors by the allocation proportion of controlling two zero vector action times, another stochastic variable is carried out the pulse location by the position of controlling the widest pulse of high level, and described two stochastic variables are presented as random number R ₁And R ₂

2. mixing stochastic space voltage vector pulse duration modulation method according to claim 1, it is characterized in that, when for the voltage vector pulse-width modulation under formula (7) seven segmentation type of action, action time and the pulse position of two basic Zero voltage vectors are subject to random number R ₁And R ₂Control, specifically comprise the steps:

${\stackrel{\&RightArrow;}{U}}_0\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_7\&RightArrow;{\stackrel{\&RightArrow;}{U}}_2\&RightArrow;{\stackrel{\&RightArrow;}{U}}_1\&RightArrow;{\stackrel{\&RightArrow;}{U}}_0---\left(7\right)$

S1: according to the command voltage vector of controller output, calculate T action time of two adjacent basic voltage vectors by formula (9) _SV1And T _SV2And T action time of Zero voltage vector _SV0,

$\left\{\begin{array}{c}{T}_{\mathrm{SV}1}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin (\frac{\mathrm{\&pi;}}{3}-\mathrm{\&theta;})\\ T_{\mathrm{SV}2}=\sqrt{3}\frac{T_s{U}_o}{U_{\mathrm{DC}}}\sin \mathrm{\&theta;}\\ T_{\mathrm{SV}0}=T_s-T_{\mathrm{SV}1}-T_{\mathrm{SV}2}\end{array}\right.---\left(9\right)$

In formula (2): T _sBe carrier cycle, U _oBe the amplitude of command voltage vector, θ is the phase angle of command voltage vector, U _DCBe direct voltage;

S2: be created on random number R on interval [0,1] according to the probability distribution of setting ₁

S3: calculate zero vector by formula (10)

With

T action time _SV00And T _SV07

$\left\{\begin{array}{c}{T}_{\mathrm{SV}00}=R_1{T}_{\mathrm{SV}0}\\ T_{\mathrm{SV}07}=(1-R_1)T_{\mathrm{SV}0}\end{array}\right.---\left(10\right)$

S4: be created on interval [K according to the probability distribution of setting ₁, K ₂] on random number R ₂, generate random number R in the type of probability distribution and S2 ₁Probability distribution used is separate;

S5: T action time that calculates every section vector by formula (11) ₁, T ₂, T ₃, T ₄, T ₅, T ₆, T ₇

$\left\{\begin{array}{c}{T}_1=R_2{T}_{\mathrm{SV}00}\\ T_2=T_{\mathrm{SV}1}/2\\ T_3=T_{\mathrm{SV}2}/2\\ T_4=T_{\mathrm{SV}07}\\ T_5=T_{\mathrm{SV}2}/2\\ T_6=T_{\mathrm{SV}1}/2\\ T_7=(1-R_2)T_{\mathrm{SV}00}\end{array}\right.---\left(11\right)$

S6: calculate 6 road impulse hits constantly, and then the value of counter register variable, by logical circuit production burst signal.

3. mixing stochastic space voltage vector pulse duration modulation method according to claim 2, is characterized in that, in described step S2 and S4, and random number R ₁And R ₂Generating mode be: with the formula that pseudo random number generates, produce in real time by software programming and realize; Perhaps, be that 0～1 pseudo random number table is stored in read-only memory with span, thereby then pseudo random number is transformed to required scope from 0～1 generate described random number R ₁And R ₂

4. mixing stochastic space voltage vector pulse duration modulation method according to claim 2, is characterized in that, in described step S4, and random number R ₂Residing interval [K ₁, K ₂] according to random number R ₁Determine, be specially:

$K_1=\left\{\begin{array}{cc}0& R_1\&le;\frac{1}{2}\\ 1-\frac{1}{{2R}_1}& R_1>\frac{1}{2}\end{array}\right.---\left(17\right)$

$K_2=\left\{\begin{array}{cc}1& R_1\&le;\frac{1}{2}\\ \frac{1}{{2R}_1}& R_1>\frac{1}{2}\end{array}\right.---\left(18\right)$

5. the described mixing stochastic space of any one voltage vector pulse duration modulation method according to claim 1-4 is characterized in that: the moment of phase current sampling is set in each modulation period

The place.

6. mixing stochastic space voltage vector pulse duration modulation method according to claim 5, it is characterized in that, in order to improve the precision of current measurement, the moment that can make current sample constantly avoid impulse hits is subject to the measurement of avoiding electric current the impact that impulse hits disturbs, concrete mode is, current sample has a S interval at least constantly with impulse hits constantly.According to the requirement of control system to the current sample error, observe by experiment impulse hits to the influence of peak current, and then determine time-delay S.

7. mixing stochastic space voltage vector pulse duration modulation method according to claim 6, is characterized in that: random number R ₂Residing interval [K ₁, K ₂] need to be in conjunction with described time interval S and random number R ₁Redefine, be specially:

$K_1=\max \{1-\frac{1}{{2R}_1}+\frac{\mathrm{\&lambda;}}{R_1},0\}---\left(20\right)$

$K_2=\min \{\frac{1}{{2R}_1}-\frac{\mathrm{\&lambda;}}{R_1},1\}---\left(21\right)$

In formula (7) and (8):

8. modulator based on FPGA, it is characterized in that adopting any modulator approach in claim 1-7, it mainly comprises one-period register, dead band register, two group hopping time registers, counting and initial value heavy cartridges circuit, a register group commutation circuit and a pulse-generating circuit

Described period register is used for depositing modulation period;

Described dead band register is used for setting Dead Time;

The moment of all depositing every phase upper arm impulse hits in two groups of described jumping moment registers;

Described counting and initial value heavy cartridges circuit comprise a counter, this counter is accepted count pulse and is subtracted 1 counting according to pulse, when counter reduces to 0, subtract again 1 when overflowing, output spill over pulse is controlled from the period register counting initial value of reloading, and begins the counting in next cycle, d type flip flop is sent into again in the spill over pulse, and the currency of counter send the comparator bank of pulse-generating circuit;

Described register group commutation circuit comprises a d type flip flop and a variable connector, this d type flip flop receives the spill over pulse from counter, controls two group hopping time registers with this and alternately accesses the comparator bank of pulse-generating circuit by variable connector;

described pulse-generating circuit comprises a comparator bank and a d type flip flop group, currency and impulse hits set point constantly that this comparator bank will be received from counter compare, if identical, realize the saltus step of pulse by the d type flip flop in the d type flip flop group, every phase upper arm relatively the time directly with the set point in the impulse hits moment in corresponding jumping moment register, need during every phase underarm comparison to participate in again comparison with the value addition of Dead Time in the set point constantly of impulse hits in corresponding jumping moment register and dead band register or after subtracting each other, to produce the dead band, avoid the time-delay of opening and turn-offing of switching tube to cause underarm straight-through, two group hopping time registers alternately are used for relatively, if use the first group hopping time register a upper modulation period, this cycle is used the second group hopping time register, the lower cycle will re-use the first group hopping time register, in current finish time modulation period or next zero hour modulation period, two group hopping time register states switch, participate in a group hopping time register relatively in current modulation period and become not relatively state, and prepare for assignment, the jumping moment register of assignment becomes the comparison state in current modulation period, prepare to participate in relatively, two group hopping time registers alternately relatively produce control impuls.

9. the modulator based on FPGA according to claim 8 is characterized in that:

6 jumping moment registers are arranged in every group hopping time register,

Have two jumping moment registers to control the A phase in every group, one is the pulse front edge jumping moment register of controlling the forward position, and another is the rear jumping moment register on edge after controlling,

Have two jumping moment registers to control the B phase in every group, one is the pulse front edge jumping moment register of controlling the forward position, and another is the rear jumping moment register on edge after controlling,

Have two jumping moment registers to control the C phase in every group, one is the pulse front edge jumping moment register of controlling the forward position, and another is the rear jumping moment register on edge after controlling;

D type flip flop group (42) comprises 6 d type flip flops, corresponding 6 tunnel pulses respectively;

Comprise 6 comparators in comparator bank, 6 d type flip flops of the corresponding d type flip flop group of difference (42),

The upper arm of the corresponding three-phases of 3 comparators wherein, each has 3 inputs and an output, these 3 inputs connect respectively: the pulse front edge jumping moment register of the currency output line of counter, variable connector output and the rear jumping moment register of variable connector output

The underarm of the corresponding three-phases of 3 comparators wherein, each has 4 inputs and an output, and these four inputs connect respectively: the pulse front edge jumping moment register of the currency output line of counter, variable connector output, rear jumping moment register and the dead band register 13 of variable connector output.

10. according to claim 8 or 9 described modulators based on FPGA, is characterized in that, it realizes by FPGA, and it has used the parallel characteristics of FPGA.

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