CN1725621A - Universal pulse width modulation integrated circuit for power electric current transormer - Google Patents

Abstract

An universal pulse width modulation integrated circuit for electronic current transformer of electric power consists of a set of parameter setting registers , a data interface circuit , a digital tracking circuit of three phase synchronous phase angle , a clock frequency division circuit for sampling , a triggering signal generation circuit for sampling , a calculation circuit of reference voltage , a data format switching circuit of reference voltage , a pulse width modulation calculating circuit , K numbers of the same switch state output time sequence control circuit and K numbers of the same switch state switching circuit .

Description

The universal pulse width modulation integrated circuit that is used for electronic power convertor

Technical field

The present invention relates to a kind of universal pulse width modulation integrated circuit that is used for electronic power convertor, to realize universal pulse width modulation (hereinafter to be referred as PWM) control to many level current transformers of various number of levels, and can realize simultaneously the phase-shifting carrier wave PWM control mode of various progression, belong to the pulse control technique field and the specialized integrated circuit technique field of electronic power convertor.

Background technology

The effect that electronic power convertor is played in industrial system comes important approximately more, has all shown great superiority and irreplaceable effect in fields such as power transmission and distribution, driven by power and speed governing and utilization of new energy resources.Continuous development along with power electronic technology, aspect converter topologies, develop into multilevel converter from two traditional Level Technology, and various many level topological structure also emerges in an endless stream, and makes electronic power convertor realize good combination between high-voltage large-capacityization and high performance.Pulse width modulation (Pulse Width Modulation is called for short PWM) is the most general control method in electronic power convertor field, also is a guardian technique of current transformer.But the complicated control of current transformer and the design of hardware and software of pulse generation system of making of topological structures such as current transformer all becomes very complicated, all brought very big difficulty for the real-time and the reliability of control.

In the pulse generation generator scheme of in the past electronic power convertor, be to adopt as the patent No. is 00100551 the disclosed method of patent of invention " general purpose controller that is used for flexible AC transmission equipment " mostly, based on the pulse width modulation of digital signal processor microprocessors such as (DSP) realization current transformer.But microprocessor is based on the structure of order execution command, raising along with the complexity and the sample frequency of converter topologies, complicated pulse generating method can become more and more serious can for the computational resource problem that DSP is faced, limit the ability of finishing complicated control algolithm with DSP, increased the complexity of hardware designs.All will consider the software realization of pulse generation algorithm when realizing that based on microprocessor another major defect of the method for pulse generation is each product design, technical difficulty is strengthened, software design is complicated, is unfavorable for the standardized designs of product.

Along with the development of large scale integrated circuit technology, the application-specific integrated circuit (ASIC) of use realizes that general pulse generator becomes possibility.At document " based on the three-phase inverter space vector PWM control IC of FPGA " (IEEE Transon Power Electronics, 1997,12 (6)) recorded and narrated a kind of PWM control integrated circuit of routine two level current transformers of realizing based on FPGA in, but this technology can't be applied in many level current transformers or more in the complicated topological structure.Also do not record and narrate for the general PWM control integrated circuit of many level current transformers at present.

Further, present converter topologies also is tending towards variation, for example for the single-phase bridge cascade converter of N level, owing to need the utilance and the dc capacitor voltage at different levels of each switching device of balance, often be not suitable for directly control of space vector method, but be decomposed into it behind current transformer of a plurality of low levels (2 level or 3 level) number and carry out pulse generation control again based on the method for phase-shifting carrier wave with the N level.

Summary of the invention

The objective of the invention is to propose a kind of universal pulse width modulation integrated circuit that is used for electronic power convertor, take place, can realize PWM strategy simultaneously based on phase-shifting carrier wave to realize various many level current transformers pwm signals.

The universal pulse width modulation integrated circuit that is used for electronic power convertor that the present invention proposes comprises:

Three modulation ratio registers are used to deposit the three-phase reference pulse width modulated ratio value of setting;

Three phase shift angle registers are used to deposit the three-phase reference pulse width modulated phase shift angle value of setting;

A fundamental frequency register is used to deposit the reference pulse width modulated fundamental frequency value of setting;

A switching frequency register is used to deposit pulse width modulation sampling switch frequency configuration value;

A number of levels register is used to deposit the pulse width modulation number of levels value of setting;

A cascade number register is used to deposit the pulse width modulation stage connection number value of setting;

A zero sequence is injected the flag bit register, is used to deposit the pulse width modulation zero sequence and injects flag bit;

A data interface circuit is used for the value that above-mentioned each register was revised or read to external circuit;

A three-phase synchronous phase angle numeral tracking circuit, be used to follow the tracks of the synchronous square-wave signal frequency and the phase place of outside input, perhaps according to above-mentioned pulse width modulation with reference to the fundamental frequency value of setting, produce the reference phase angle, and on the reference phase angle that produces, add above-mentioned three-phase pulse width modulated reference phase shift angle value of setting, produce three-phase reference voltage phase angle;

A sampling clock frequency dividing circuit, being used for the external crystal-controlled oscillation signal is clock input signal, according to above-mentioned pulse width modulation sampling switch frequency configuration value, obtaining frequency is 1000 times the sample count clock signal of the sample frequency value of setting;

A sampling trigger signal generation circuit, being used for above-mentioned sample count clock signal is the clock input, under the control of above-mentioned pulse width modulation stage connection number value of setting, produce K level direction control signal, K level sampling trigger signal and total sampling trigger signal by phase shift, wherein K is the pulse width modulation stage connection number value of setting, K=1～31;

A reference voltage counting circuit, be used under the triggering of above-mentioned total sampling trigger signal, according to above-mentioned three-phase reference pulse width modulated ratio value of setting and three-phase pulse width modulated reference phase shift angle, calculate and latch the instantaneous reference voltage original value of output three-phase respectively, and produce the modulation triggering signal;

A reference voltage data format converting, be used for injecting flag bit according to above-mentioned pulse width modulation number of levels value of setting and pulse width modulation zero sequence, transfer the instantaneous reference voltage original value of above-mentioned three-phase to required data format, obtain the instantaneous reference voltage calculated value of three-phase;

A pulse width modulation counting circuit, be used under above-mentioned modulation triggering signal triggers, and according to the instantaneous reference voltage calculated value of above-mentioned three-phase, the on off state that calculates and latch the next sampling period of output reaches and on off state corresponding action time of count value, and produces the output triggering signal;

K identical on off state output timing control circuit, be used under the triggering of above-mentioned output triggering signal, reach and on off state corresponding action time of count value according to above-mentioned on off state, control the on off state output timing of K level pulse width modulation in a sampling period respectively;

K identical switch state circuit is used for transferring on off state to corresponding electronic power switch gate pole triggering signal.

The universal pulse width modulation integrated circuit that is used for electronic power convertor that the present invention proposes can realize that various many level current transformers pwm signals take place, and can realize the many level PWMs control strategy based on phase-shifting carrier wave simultaneously.The present invention is based on the hardware of large scale digital circuit and realizes that with respect to existing pulse generating method based on microprocessor, speed is fast and pulse precision is high, has thoroughly solved computational resource when realizing complicated control algolithm and the restricted problem of computing time.The present invention is integrated into the many level pulse widths modulation algorithm and the phase-shifting carrier wave modulator approach of complexity in the digital circuit, in the design of electronic power convertor controller, need not to consider again complicated pulse generation algorithm, the external circuits design is very simple, and stability and reliability greatly improve.The present invention is applicable to the pulse generation control of various two level or many level current transformers, current transformer to various number of levels is general, and can realize optimum control mode to various many level current transformers by selecting the strategy of direct many level PWMs or the many level PWMs of phase-shifting carrier wave.

Description of drawings

Fig. 1 is the theory diagram of the integrated circuit of the present invention's proposition.

Fig. 2 is the timing diagram between k level direction control signal in the integrated circuit of the present invention and the k level sampling trigger signal.

Figure 3 shows that the timing diagram between the K level sampling control signal and total sampling control signal in the integrated circuit of the present invention.

Fig. 4 is the theory diagram of the numeral of the three-phase synchronous phase angle in the integrated circuit of the present invention tracking circuit part.

Fig. 5 is the block diagram of reference voltage counting circuit in the integrated circuit of the present invention.

Fig. 6 is the typical application circuit schematic diagram of integrated circuit of the present invention.

Effect oscillogram when Fig. 7 carries out direct PWM control for adopting integrated circuit of the present invention to one 7 level current transformer.

Effect oscillogram when Fig. 8 carries out phase-shifting carrier wave PWM control for adopting integrated circuit of the present invention to one five level current transformer.

Embodiment

The universal pulse width modulation integrated circuit that is used for electronic power convertor that the present invention proposes, its theory diagram comprises as shown in Figure 1: three modulation ratio registers are used to deposit the three-phase reference pulse width modulated ratio value of setting; Three phase shift angle registers are used to deposit the three-phase reference pulse width modulated phase shift angle value of setting; A fundamental frequency register is used to deposit the reference pulse width modulated fundamental frequency value of setting; A switching frequency register is used to deposit pulse width modulation sampling switch frequency configuration value; A number of levels register is used to deposit the pulse width modulation number of levels value of setting; A cascade number register is used to deposit the pulse width modulation stage connection number value of setting; A zero sequence is injected the flag bit register, is used to deposit the pulse width modulation zero sequence and injects flag bit; A data interface circuit is used for the value that above-mentioned each register was revised or read to external circuit; A three-phase synchronous phase angle numeral tracking circuit, be used to follow the tracks of the synchronous square-wave signal frequency and the phase place of outside input, perhaps according to above-mentioned pulse width modulation with reference to the fundamental frequency value of setting, produce the reference phase angle, and on the reference phase angle that produces, add above-mentioned three-phase pulse width modulated reference phase shift angle value of setting, produce three-phase reference voltage phase angle; A sampling clock frequency dividing circuit, being used for the external crystal-controlled oscillation signal is clock input signal, according to above-mentioned pulse width modulation sampling switch frequency configuration value, obtaining frequency is 1000 times the sample count clock signal of the sample frequency value of setting; A sampling trigger signal generation circuit, being used for above-mentioned sample count clock signal is the clock input, under the control of above-mentioned pulse width modulation stage connection number value of setting, produce K level direction control signal, K level sampling trigger signal and total sampling trigger signal by phase shift, wherein K is the pulse width modulation stage connection number value of setting, K=1～31; A reference voltage counting circuit, be used under the triggering of above-mentioned total sampling trigger signal, according to above-mentioned three-phase reference pulse width modulated ratio value of setting and three-phase pulse width modulated reference phase shift angle, calculate and latch the instantaneous reference voltage original value of output three-phase respectively, and produce the modulation triggering signal; A reference voltage data format converting, be used for injecting flag bit according to above-mentioned pulse width modulation number of levels value of setting and pulse width modulation zero sequence, transfer the instantaneous reference voltage original value of above-mentioned three-phase to required data format, obtain the instantaneous reference voltage calculated value of three-phase; A pulse width modulation counting circuit, be used under above-mentioned modulation triggering signal triggers, and according to the instantaneous reference voltage calculated value of above-mentioned three-phase, the on off state that calculates and latch the next sampling period of output reaches and on off state corresponding action time of count value, and produces the output triggering signal; K identical on off state output timing control circuit, be used under the triggering of above-mentioned output triggering signal, reach and on off state corresponding action time of count value according to above-mentioned on off state, control the on off state output timing of K level pulse width modulation in a sampling period respectively; K identical switch state circuit is used for transferring on off state to corresponding electronic power switch gate pole triggering signal.

Describe content of the present invention in detail below in conjunction with drawings and Examples:

Integrated circuit structure block diagram of the present invention comprises that data interface circuit, parameter are provided with registers group, three-phase synchronous phase angle numeral tracking circuit, sampling clock frequency dividing circuit, sampling trigger signal generation circuit, reference voltage counting circuit, reference voltage data format converting, pulse width modulation counting circuit, one group of on off state output timing control circuit and one group of switch state circuit as shown in Figure 1.Whole integrated circuit is a full-digital circuit.

In the integrated circuit of the present invention data interface circuit be used to provide and external microprocessor between the data-interface function, external microprocessor to the operation of integrated circuit of the present invention with identical to common sram chip operation, can be by this chip of control CS pin gating, determine read-write mode by the R/W pin, by the register that the selection of A (3:0) address pins will be operated, change or read the value of register by data/address bus D (15:0).

Comprise in the integrated circuit of the present invention that one group of parameter is provided with register, be used to be provided with the working method of frequency, amplitude, phase information and the pulse width modulation algorithm of reference voltage.

Wherein three 7 modulation ratio register is used to deposit three-phase reference pulse width modulated and compares m _a, m _b, m _cThe value of setting, number range is 1～115, corresponding actual modulation ratio is 0.01～1.15;

Wherein three 12 phase angle register is used to deposit three-phase reference pulse width modulated phase shift angle δ _a, δ _b, δ _c, number range is 0～3599, corresponding actual angle value is 0.1 °～359.9 °;

One 12 fundamental frequency register is used to deposit the reference pulse width modulated fundamental frequency value of setting f ₁, number range is 0～4000, corresponding actual frequency values is 0.1～400.0Hz;

One 8 sample frequency register is used to deposit pulse width modulation sampling switch frequency configuration value C _Fs, storage is the frequency division multiple value of setting to the external crystal-controlled oscillation clock frequency here, scope is 1～255;

One 4 number of levels register is used to deposit the pulse width modulation number of levels value of setting N, and number range is 2～15, and corresponding actual number of levels is 2～15 level;

One 5 cascade number register is used to deposit the pulse width modulation stage connection number value of setting K, and number range is 1～31, and corresponding actual cascade number is 1～31 grade;

One 1 zero sequence is injected the flag bit register, is used to deposit the pulse width modulation zero sequence and injects flag bit ZFLAG; When ZFLAG is ' 1 ' level, can comprise zero sequence in the sign output voltage, actual modulated can be 1.15 than maximum under this mode; When ZFLAG is ' 0 ' level, do not comprise zero sequence in the sign output voltage, actual modulated can be 1.00 than maximum under this mode.

In the integrated circuit of the present invention, the sampling clock frequency dividing circuit is a frequency dividing circuit, and it is to be clock input signal with the external crystal-controlled oscillation signal, with above-mentioned pulse width modulation sampling switch frequency configuration value C _FSBe frequency division multiple C _FS, outside clock crystal oscillator signal is carried out frequency division, obtaining frequency is the sample count clock signal of 1000 times of sample frequencys.The frequency division multiple value of setting C _FS, the pass between external clock crystal oscillator frequency fclk and the sample frequency fs is

$C_{\mathrm{fs}}=\frac{{\mathrm{<figure-callout\; id="1000"\; label="f\; cls"\; filenames="A20051008522000122.png"\; state="\{\{state\}\}">f</figure-callout>}}_{\mathrm{cls}}}{1000\&times;f_s}$

For example, if the external crystal-controlled oscillation clock frequency is 50MHz, the sample frequency value of setting that needs is 2kHz, then only needs by the sample frequency register C _FSBe set to 25.

The sampling clock frequency dividing circuit is with C _FSBe the frequency division multiple, the external crystal-controlled oscillation clock is carried out frequency division, obtain a sample count clock signal, the frequency of this clock signal is 1000 times of sample frequency, also we can say by this clock signal a sampling period has been divided into 1000 parts uniformly.The sample count clock signal will be used to control the time of sampling trigger signal and the output time of each on off state of control as the clock input of sampling trigger signal generation circuit and on off state output timing control circuit.

The effect of the sampling trigger signal generation circuit in the integrated circuit of the present invention is according to the cascade number value of setting K, produces K level direction control signal and K level sampling trigger signal, and produces total sampling trigger signal.Sampling trigger signal generation circuit comprises that K counter circuit, a K monostable trigger-action circuit and a K import or door.The input of the clock of K counter circuit is the sample count clock signal, and the count cycle is 2000, and duty ratio is that the counting phase place of 1/2, a k counter circuit is (k-1) * 2000/K, k=1 wherein, and 2 ... .K.The output of K counter circuit is respectively as K level direction control signal like this, they are the cycle is that 2000 sample count clock cycle, duty ratio are 1/2 square-wave signal, and the phase place of direction control signals at different levels lags behind 2000/K sample count clock cycle successively.Then, K level direction control signal is input to K monostable trigger-action circuit respectively, and each the variation edge at K level direction control signal obtains the K level sampling trigger signal that the high level width is 1 sample count clock cycle by monostable trigger-action circuit.At last, total sampling trigger signal is imported or produced behind the door to all K sampling trigger signal by a K.

During with cascade number K=4 is example, Figure 2 shows that the timing diagram between k level direction control signal and the k level sampling trigger signal.Figure 3 shows that the timing diagram between k level sampling control signal and the total sampling control signal.

Figure 4 shows that the theory diagram of the three-phase synchronous phase angle numeral tracking circuit part among the present invention, be used to generate the phase angle of three-phase reference voltage.Numerical frequency in the circuit is measured with phase lock circuitry and is used to produce synchronizing frequency doubling signal in this section, perhaps follows the tracks of the frequency and the phase place of square wave synchronizing signal, perhaps according to the reference pulse width modulated fundamental frequency value of setting f ₁Frequency, by the frequency multiplication generation cycle be the pulse of 0.1 electrical degree (corresponding to synchronous signal cycle), it as the input of clock of phase angle summation circuit, at its rising edge of a pulse, is increased progressively 1 with triggering synchronous phase angle counter; And the square wave synchronizing signal is imported as the zero clearing of phase angle summation circuit, and its rising edge makes zero triggering synchronous phase angle counter.The numeral output of such reference phase angle ω t to the end, its digital output area is 0～3599, corresponding to actual electrical angle 0.0～359.9 degree, can be with one 12 data representation.Then with ω t and three-phase reference phase shift angle δ _a, δ _b, δ _cAddition respectively just can obtain three-phase reference voltage phase angle θ _a, θ _b, θ _c, all be respectively 12 data format in integrated circuit.

Fig. 5 is the block diagram of reference voltage counting circuit.The three-phase reference pulse width modulated ratio value of setting m _a, m _b, m _cWith three-phase reference voltage phase angle θ _a, θ _b, θ _cInput as the computational logic control circuit.The computational logic control circuit is to be triggered by total sampling trigger signal, triggers the back three-phase reference pulse width modulated ratio value of setting m _a, m _b, m _cWith three-phase reference voltage phase angle θ _a, θ _b, θ _cAt first be latched, latch respectively as modulation ratio m and angle θ output according to sequential then, and deliver to the sinusoidal form circuit and the displacement multiplier circuit of back.

Sinusoidal form memory circuit is used to store between 0.0 °～90.0 ° every 0.1 ° of pairing sine value.Because in digital circuit, carrying out the complex mathematical computing is the comparison difficulty, so in advance the angle between =0.0～90.0 degree is calculated the sine value data every 0.1 degree, be stored in the RAM data form of a 901 * 10bits, the data format of storage is: FIX (1000 * sin ()), wherein FIX is a bracket function.Angle θ is the output of sinusoidal form memory circuit, and the output of sinusoidal form memory circuit is sin θ.

The displacement multiplier circuit is 7 data bit according to the modulation ratio data, and the offset of sinusoidal Value Data carries out the logical process that moves to left of different numbers respectively, again with the data addition after each shifting processing, obtains final multiplication result of calculation.The input of displacement multiplier circuit is m and sin θ, and output is m * sin θ

Behind the reference voltage counting circuit, just can obtain carrying out the instantaneous reference voltage level V of three-phase _Ra1, V _Rb1, V _Rc1, their computing formula can followingly be represented:

$\left[\begin{array}{c}{v}_{\mathrm{ra}1}\\ v_{\mathrm{rb}1}\\ v_{\mathrm{<figure-callout\; id="1"\; label="rc"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">rc</figure-callout>}1}\end{array}\right]=\left[\begin{array}{c}{m}_a\sin {\mathrm{\&theta;}}_a\\ m_b\sin {\mathrm{\&theta;}}_b\\ m_c\sin {\mathrm{\&theta;}}_c\end{array}\right]=\left[\begin{array}{c}{m}_a\sin (\mathrm{\&omega;t}+{\mathrm{\&delta;}}_a)\\ m_b\sin (\mathrm{\&omega;t}+{\mathrm{\&delta;}}_b)\\ m_c\sin (\mathrm{\&omega;t}+{\mathrm{\&delta;}}_c)\end{array}\right]$

Like this, after calculating finished, the reference voltage counting circuit latched the instantaneous reference voltage original value of output three-phase, and produced the modulation triggering signal.

For the ease of the calculating of pulse width modulation algorithm, original instantaneous reference voltage level need be converted into required data format, and this part processing realizes in the reference voltage data format converting.The input of reference voltage data format converting is the instantaneous reference voltage level V of three-phase _Ra1, V _Rb1, V _Rc1Inject flag bit ZFLAG with the pulse width modulation zero sequence.

The pulse width modulation zero sequence is injected flag bit ZFLAG and has been determined residual voltage injection value V ₀Residual voltage injection value V ₀Purpose be in order to improve the scope of maximum modulation, just to improve the utilance scope of direct voltage.Residual voltage injection value V ₀To be subjected to zero sequence to inject the control of flag bit ZFLAG as follows:

Wherein max () and min () are respectively and get max function and get minimum value function.

The reference voltage data format converting is carried out the following three-phase reference voltage calculated value V that calculates and export like this _Ra, V _Rb, V _Rc

$\left[\begin{array}{c}{v}_{\mathrm{ra}}\\ v_{\mathrm{rb}}\\ v_{\mathrm{rc}}\end{array}\right]=\mathrm{<figure-callout\; id="1000"\; label="FIX"\; filenames="A20051008522000122.png"\; state="\{\{state\}\}">FIX</figure-callout>}\left[\begin{array}{c}1000\&times;\frac{N-1}{2}\end{array}\left[\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="V\; ra"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ra}}+{\mathrm{<figure-callout\; id="0"\; label="V"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">V</figure-callout>}}_0+1\\ {\mathrm{<figure-callout\; id="1"\; label="V\; rb"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{rb}}+{\mathrm{<figure-callout\; id="0"\; label="v"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">v</figure-callout>}}_0+1\\ {\mathrm{<figure-callout\; id="1"\; label="V\; rc"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{rc}}+{\mathrm{<figure-callout\; id="0"\; label="V"\; filenames="A20051008522000121.png,A20051008522000123.png"\; state="\{\{state\}\}">V</figure-callout>}}_0+1\end{array}\right]\right]$

Wherein N is the number of levels set point, V ₀Be residual voltage injection value.

In the integrated circuit of the present invention, the pulse width modulation counting circuit is the core of pulse generation, is used to realize to the general many level space vectors modulation algorithm of number of levels.Pulse width modulation is calculated sequential and is triggered by the modulation triggering signal.When the modulation triggering signal takes place, at first three-phase reference voltage calculated value is latched, carry out each step successively according to the external crystal-controlled oscillation clock then, being described as follows of each calculation procedure:

(1) the instantaneous reference voltage calculated value of three-phase is decomposed, obtain the slope switch state and be

$\left[\begin{array}{c}\mathrm{SOFA}\\ \mathrm{SOFB}\\ \mathrm{SOFC}\end{array}\right]=\left[\begin{array}{c}\mathrm{FIX}\left(\frac{V_{\mathrm{ra}}}{1000}\right)\\ \mathrm{FIX}\left(\frac{V_{\mathrm{rb}}}{1000}\right)\\ \mathrm{FIX}\left(\frac{V_{\mathrm{rc}}}{1000}\right)\end{array}\right]$

Obtaining two level reference voltage is,

$\left[\begin{array}{c}\mathrm{VTWLA}\\ \mathrm{VTWLB}\\ \mathrm{VTWLC}\end{array}\right]=\left[\begin{array}{c}{V}_{\mathrm{ra}}-1000\&times;\mathrm{SOFA}\\ V_{\mathrm{rb}}-1000\&times;\mathrm{SOFB}\\ V_{\mathrm{rc}}-1000\&times;\mathrm{SOFB}\end{array}\right]$

(2) according to two level reference voltage VTWLA, VTWLB, VTWLC, and, obtain four two level switch states according to the existing two level space vector methods of foundation:

STWL1＝(S1a，S1b，S1c)，STWL2＝(S2a，S2b，S2c)，SWTL3＝(S3a，S3b，S3c)，

STWL4＝(S4a，S4b，S4c)；

(3) calculating count value four action time is

T1＝1000-MAX(VTWLA，VTWLB，VTWLC)，

T2＝MAX(VTWLA，VTWLB，VTWLC)-MID(VTWLA，VTLWB，VTWLC)，

T3＝MID(VTWLA，VTWLB，VTWLC)-MIN(VTWLA，VTLWB，VTWLC)，

T4＝1000-T1-T2-T3；

(4) with slope switch state and two level switch state additions, obtain four output on off states be:

(SOFA+S1c), its corresponding count value action time is T1 to SWS1=for SOFA+S1a, SOFA+S1b

(SOFA+S2c), its corresponding count value action time is T2 to SWS2=for SOFA+S2a, SOFA+S2b

(SOFA+S3c), its corresponding count value action time is T3 to SWS3=for SOFA+S3a, SOFA+S3b

SWS4=(SOFA+S4a, SOFA+S4b, SOFA+S4c); Its corresponding count value action time is T4

(5) latch four on off states of output and action time count value, and produce the output triggering signal

Comprise K identical on off state output timing control circuit in the integrated circuit of the present invention, be used to realize the pulse width modulation algorithm of K level phase-shifting carrier wave.Each on off state output timing control circuit is actually a counter circuit, is imported as clock by the sample count clock signal, to control successively preface according to the output of controlling four on off states in the sampling period action time.When k counter circuit receives output triggering signal and k level sampling trigger signal at the same time, with the count value zero clearing, and with described four on off states, four action time count value and k level direction control signal latch.Be the clock input with the sample count clock signal then, the rising edge of each clock input signal increases progressively 1 to output counter; The output of on off state is to determine that by triggering direction control signal constantly concrete mode is as follows in proper order:

(1) when described direction control signal is ' 1 ' level, when being 0～T1, the value of output counter exports described SWS1 on off state, when being T1～T1+T2, the value of output counter exports described SWS2, when the value of output counter is T1+T2～T1+T2+T3, export described SWS3, when the value of output counter is T1+T2+T3～1000, export described SWS4;

(2) when described direction control signal is ' 0 ' level, when being 0～T4, the value of output counter exports described SWS4 on off state, when being T4～T4+T3, the value of output counter exports described SWS3, when the value of output counter is T4+T3～T4+T3+T2, export described SWS2, when the value of output counter is T4+T3+T2～1000, export described SWS1;

In the integrated circuit of the present invention, K identical switch state circuit is used at last switch state signal being transferred to corresponding switching device gate pole triggering signal.For every phase current transformer brachium pontis, the N level circuit will be made up of 2 * (N 1) individual switching devices, need N-1 independently gate pole triggering signal (other N-1 device gate pulse oppositely obtained by this N-1 gate pole triggering signal).The truth table of many level switches state of every phase and gate pulse state corresponding relation is as shown in table 1.

The truth table of table 1 level switch state and gate pulse state corresponding relation

The technical staff at first selects control strategy according to the topological structure of current transformer when using this integrated circuit, select the number of levels of corresponding cascade number and every grade of modulation.Then, can select corresponding gate pulse output signal according to the number of levels of every grade of modulation.For example, if every grade of modulation is two level, then select P _X1Get final product; If every grade of modulation is three level, then select P _X1, P _X2Get final product; If every grade of modulation is four level, then select P _X1, P _X2, P _X3Get final product; During other number of levels and the like.

Fig. 6 has provided the typical application circuit schematic diagram of integrated circuit of the present invention.Microprocessor Interface such as the data-interface of integrated circuit and DSP, DSP can be by revising the register controlled reference voltage and the PWM Control Parameter of IC interior like this.For the occasion that needs synchronizing signal,, can the square wave synchronizing signal be input to integrated circuit by the SYN pin as static reacance generator (STATCOM); For not needing synchronous occasion, as variable-frequency governor, can be directly by revising the frequency that fundamental frequency is provided with the register controlled reference voltage.

Fig. 7 has provided the result of use when adopting integrated circuit of the present invention that one 7 level current transformer is carried out direct PWM control.In this used, number of levels N was set to 7, and cascade number K is set to 1.Given waveform is 7 final level output voltage waveforms.

Fig. 8 has provided one five level current transformer has been carried out the phase-shifting carrier wave PWM result of use in when control.In this used, one five level current transformer adopts to be controlled based on the PWM strategy of three level phase-shifting carrier wave, and number of levels N is set to 3, and cascade number K is set to 2.Given oscillogram is respectively the 1st grade of PWM waveform, the 2nd grade of PWM waveform, phase-shifting carrier wave five level output voltage waveforms after synthetic from top to bottom.

Claims (1)

1, a kind of universal pulse width modulation integrated circuit that is used for electronic power convertor is characterized in that this integrated circuit comprises:

Three modulation ratio registers are used to deposit the three-phase reference pulse width modulated ratio value of setting;

Three phase shift angle registers are used to deposit the three-phase reference pulse width modulated phase shift angle value of setting;

A fundamental frequency register is used to deposit the reference pulse width modulated fundamental frequency value of setting;

A switching frequency register is used to deposit pulse width modulation sampling switch frequency configuration value;

A number of levels register is used to deposit the pulse width modulation number of levels value of setting;

A cascade number register is used to deposit the pulse width modulation stage connection number value of setting;

A zero sequence is injected the flag bit register, is used to deposit the pulse width modulation zero sequence and injects flag bit;

A data interface circuit is used for the value that above-mentioned each register was revised or read to external circuit;

A three-phase synchronous phase angle numeral tracking circuit, be used to follow the tracks of the synchronous square-wave signal frequency and the phase place of outside input, perhaps according to above-mentioned pulse width modulation with reference to the fundamental frequency value of setting, produce the reference phase angle, and on the reference phase angle that produces, add above-mentioned three-phase pulse width modulated reference phase shift angle value of setting, produce three-phase reference voltage phase angle;

A sampling clock frequency dividing circuit, being used for the external crystal-controlled oscillation signal is clock input signal, according to above-mentioned pulse width modulation sampling switch frequency configuration value, obtaining frequency is 1000 times the sample count clock signal of the sample frequency value of setting;

A sampling trigger signal generation circuit, being used for above-mentioned sample count clock signal is the clock input, under the control of above-mentioned pulse width modulation stage connection number value of setting, produce K level direction control signal, K level sampling trigger signal and total sampling trigger signal by phase shift, wherein K is the pulse width modulation stage connection number value of setting, K=1～31;

A reference voltage counting circuit, be used under the triggering of above-mentioned total sampling trigger signal, according to above-mentioned three-phase reference pulse width modulated ratio value of setting and three-phase pulse width modulated reference phase shift angle, calculate and latch the instantaneous reference voltage original value of output three-phase respectively, and produce the modulation triggering signal;

A reference voltage data format converting, be used for injecting flag bit according to above-mentioned pulse width modulation number of levels value of setting and pulse width modulation zero sequence, transfer the instantaneous reference voltage original value of above-mentioned three-phase to required data format, obtain the instantaneous reference voltage calculated value of three-phase;

A pulse width modulation counting circuit, be used under above-mentioned modulation triggering signal triggers, and according to the instantaneous reference voltage calculated value of above-mentioned three-phase, the on off state that calculates and latch the next sampling period of output reaches and on off state corresponding action time of count value, and produces the output triggering signal;

K identical on off state output timing control circuit, be used under the triggering of above-mentioned output triggering signal, reach and on off state corresponding action time of count value according to above-mentioned on off state, control the on off state output timing of K level pulse width modulation in a sampling period respectively;

K identical switch state circuit is used for transferring on off state to corresponding electronic power switch gate pole triggering signal.

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