CN103165573A - Vertical parasitic PNP device in Bipolar CMOS (BiCMOS) technology and manufacturing method thereof - Google Patents

Vertical parasitic PNP device in Bipolar CMOS (BiCMOS) technology and manufacturing method thereof Download PDF

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CN103165573A
CN103165573A CN2011104126378A CN201110412637A CN103165573A CN 103165573 A CN103165573 A CN 103165573A CN 2011104126378 A CN2011104126378 A CN 2011104126378A CN 201110412637 A CN201110412637 A CN 201110412637A CN 103165573 A CN103165573 A CN 103165573A
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emitter window
base stage
active area
polysilicon
region
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CN103165573B (en
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陈帆
陈雄斌
刘冬华
薛恺
周克然
潘嘉
李�昊
蔡莹
陈曦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a vertical parasitic PNP device in the Bipolar CMOS (BiCMOS) technology. Both an emitter region and a base terminal are composed of polycrystalline silicon filled in a window which is formed above a base region. According to the vertical parasitic PNP device in the BiCMOS technology, a photolithography plate does not need to be additionally arranged, the emitter region and the base terminal are both composed of the polycrystalline silicon, and therefore even diffusion of implanted ions can be achieved easily, a highly-concentrated emitter region and a highly-concentrated base terminal are easy to form, and emission efficiency, the amplification coefficient and cut-off frequency of the device can be greatly improved. Due to the fact that longhole contact and a pseudo buried layer are adopted to lead out a collector region, the area of the device can be effectively reduced, the parasitic effect of the device can be reduced, collector resistance can be reduced, characteristics of the device can be improved, the current gain coefficient of the device can be improved, and frequency characteristics of the device can be improved. The invention further discloses a manufacturing method of the vertical parasitic PNP device in the BiCMOS technology, extra technological conditions are not needed, and production cost can be reduced.

Description

Vertical parastic PNP device and manufacture method thereof in BiCMOS technique
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to the vertical parastic PNP device in a kind of BiCMOS technique, the invention still further relates to the manufacture method of the vertical parastic PNP device in this BiCMOS technique.
Background technology
In radio frequency applications, need more and more higher device feature frequency.In the BiCMOS technology, NPN triode, particularly Ge-Si heterojunction triode (SiGe) or germanium silicon-carbon heterojunction triode (SiGeC HBT) are the fine selections of hyperfrequency device.And SiGe technique is substantially compatible mutually with silicon technology, so SiGe HBT has become one of main flow of hyperfrequency device.Under this background, its requirement to output device also correspondingly improves, such as having certain current gain coefficient (being not less than 15) and cut-off frequency.
For ambipolar field-effect transistor (BiCMOS) technique, be the complementation of Ge-Si heterojunction NPN triode as the NPN device, the PNP device is also extremely important.The PNP device is divided into two kinds of lateral PNP and longitudinal P NP usually.Wherein longitudinal P NP performance of devices is higher, is also needed in performance application.But the integrated difficulty of longitudinal P NP device and NPN device is larger, even can't carry out integrated.And the lateral PNP performance of devices is relatively poor, but the integrated ratio of device is easier to.
It is identical and be to form simultaneously that the germanium silicon single crystal that the germanium silicon single crystal of the emitter region of existing PNP triode forms technique and the base of existing Ge-Si heterojunction NPN triode forms technique.The polysilicon of drawing the base of existing PNP triode adopts the technique of the polysilicon of the emitter region that has Ge-Si heterojunction NPN triode now.But the device property to existing PNP triode is verified discovery, and its performance is unsatisfactory, and amplification coefficient is smaller, and cut-off frequency is also lower.Its main cause is that the actual doped level of described emitter region is lower.
The doping of the described emitter region of existing PNP triode is to be undertaken by injection, and shares with the outer base area injection of existing Ge-Si heterojunction NPN triode and namely adopt same process to inject simultaneously formation.Because the thickness of the germanium silicon that has Ge-Si heterojunction NPN triode now is very thin, so its outer base area Implantation Energy is also very little, only has 5KEV～10KEV.Due to the emitter region of the existing PNP triode germanium silicon single crystal for the base of sharing existing NPN triode, in order to reduce the base width of existing NPN triode, improve the performance of NPN, so in the germanium silicon single crystal, doping contains certain density carbon.These carbon can suppress the diffusion of boron.Therefore although cause the doping dosage of described emitter region of existing PNP triode very large, but because energy is very little, can't punch the carbon-coating in this one deck germanium-silicon alloy, cause most boron to be suppressed in the germanium silicon single crystal of emitter region very near surperficial zone.And because the emitter region of existing PNP triode needs to grow in the subsequent technique process layer of metal silicide, so the region doping that heavily mix on the surface that causes the germanium silicon single crystal of emitter region is consumed major part, thereby the emission ratio that makes existing PNP triode is very low and cause the device amplification coefficient lower, and cut-off frequency is also not high enough.
Summary of the invention
Technical problem to be solved by this invention is to provide the vertical parastic PNP device in a kind of BiCMOS technique, need not to add reticle, making the emitter region is polycrystalline structure, can improve the doping content of emitter region, thereby improve the emission effciency of device and the amplification coefficient of device, and can increase the cut-off frequency of device; Can as the output device in the BiCMOS high-frequency circuit, for providing many a kind of devices, circuit select; Effectively the reduction of device area, reduce device ghost effect, reduce collector resistance, improve performance of devices.The present invention also provides the manufacture method of the vertical parastic PNP device in a kind of BiCMOS technique, and process conditions that need not be extra can reduce production costs.
For solving the problems of the technologies described above, vertical parastic PNP device in BiCMOS technique provided by the invention is formed on silicon substrate, the isolation structure that active area is active area by the isolation of shallow slot field oxygen be a shallow trench isolation from (SIT), described vertical parastic PNP device comprises:
One collector region is comprised of a P type ion implanted region that is formed in described active area, and the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen.
One counterfeit buried regions, P type ion implanted region by the oxygen bottom, described shallow slot field that is formed at all sides of described collector region forms, described counterfeit buried regions and described collector region touch at described shallow slot field oxygen bottom connection, draw collector electrode by the deep hole contact that forms in the oxygen of the described shallow slot field at described counterfeit buried regions top.
One base is comprised of a N-type ion implanted region that is formed in described active area and be positioned at described collector region top, and described base and described collector region contact.
One emitter window dielectric layer is formed on described active area and extends on the described shallow slot field oxygen of described active area week side; After being fallen by partial etching, described emitter window dielectric layer defines emitter window and base stage Windows.
Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described emitter window is exposed described base; Described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area to be had overlapping and described base is exposed.
All be filled with polysilicon in described emitter window and described base stage Windows, this polysilicon top does not extend on described emitter window dielectric layer; Polysilicon in described emitter window is that the P type adulterates and forms the emitter region, and the polysilicon in described base stage Windows is that N-type is adulterated and forms base terminal; Be formed with Metal Contact and draw emitter on described emitter region; Be formed with Metal Contact and draw base stage on described base terminal.
Further improvement is, described emitter window dielectric layer is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer is 0.05 micron～0.4 micron.
Further improving is that the width of described emitter window is 0.2 micron～0.5 micron; The width of described base stage Windows is 0.2 micron～0.5 micron.
For solving the problems of the technologies described above, the manufacture method of the vertical parastic PNP device in BiCMOS technique provided by the invention comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate; Adopt the silicon nitride hardmask during etching above described active area.
Step 2, pass described silicon nitride hardmask and carry out the N-type Implantation at described active area and form the base; The degree of depth of described base is less than the bottom degree of depth of described shallow trench.
Step 3, carry out P type Implantation in described shallow trench bottom and form counterfeit buried regions.
Step 4, carry out annealing process, the horizontal and vertical diffusion of described counterfeit buried regions also extends in described active area.
Step 5, insert silica form shallow slot field oxygen in described shallow trench.
Step 6, carry out P type Implantation form collector region in described active area, the degree of depth of described collector region more than or equal to the bottom degree of depth of described shallow slot field oxygen and and described counterfeit buried regions formation contact.
Step 7, at the positive deposit one emitter window dielectric layer of described silicon substrate, described emitter window dielectric layer is positioned on described active area and extends on the described shallow slot field oxygen of described active area week side.
Step 8, graphical definition goes out the formation zone of emitter window and base stage Windows with photoresist; Described emitter window dielectric layer forms described emitter window and described base stage Windows take described photoetching offset plate figure as mask etching; Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area to be had overlapping; Etching adopts the etching of fixing time, and makes the described base region surface of the bottom of described emitter window and described base stage Windows also remain with certain thickness described emitter window dielectric layer.
The residual described emitter window dielectric layer in bottom of step 9, the employing wet-etching technology described emitter window of removal and described base stage Windows also exposes described base region surface, comprehensive depositing polysilicon on described silicon substrate; The thickness of described polysilicon satisfies fills described emitter window and described base stage Windows fully.
Step 10, described polysilicon is returned quarter, the described polysilicon of described emitter window and described base stage Windows outside is all removed, remaining described polysilicon only is filled in described emitter window and described base stage Windows.
Step 11, the polysilicon in described base stage Windows is carried out N-type doping form base terminal; Polysilicon in described emitter window is carried out the doping of P type form the emitter region.
Step 12, form the deep hole contact draw described collector electrode in the oxygen of the shallow slot field at described counterfeit buried regions top; Form Metal Contact at top, described emitter region and draw emitter; Form Metal Contact at the top of described base terminal and draw base stage.
Further improvement is, the dielectric layer of emitter window described in step 7 is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer is 0.05 micron～0.4 micron.
Further improvement is, the width of emitter window described in step 8 is 0.2 micron～0.5 micron, and the width of described base stage Windows is 0.2 micron～0.5 micron.
Further improving is that in step 9, the thickness of the described polysilicon of deposit is 0.2 micron～0.5 micron.
Further improving is that the Hui Kewei to described polysilicon in step 10 returns quarter comprehensively, does not adopt mask; Adopt the terminal point etching to detect, make etch-stop on described emitter window dielectric layer, guarantee that the polysilicon on described emitter window dielectric layer is etched totally.
Further improve is that the N-type doping process of base terminal described in step 11 shares the injection technology of the polysilicon emissioning area of the NPN device in BiCMOS technique; The P+ that the P type doping process of emitter region described in step 11 shares in BiCMOS technique injects.
Further improve is that the surface that also is included in described emitter region and described base terminal in step 11 forms the technique of metal silicide.
Device of the present invention can as the output device in the BiCMOS high-frequency circuit, be selected for circuit provides many a kind of devices.The present invention need not to add reticle, emitter region and base terminal are made of polysilicon simultaneously, polysilicon is conducive to the even diffusion of ion, thereby can form emitter region and the base terminal of high concentration, the emission effciency of device can be greatly improved like this, amplification coefficient can be greatly improved, and cut-off frequency also can be greatly improved.The present invention is by adopting deep hole contact and counterfeit buried regions to draw collector region, effectively the reduction of device area, reduce device ghost effect, reduce the feature of collector resistance, raising device; Can also improve the current gain coefficient of device and the frequecy characteristic that improves device.The inventive method need not be extra process conditions, can reduce production costs.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of the vertical parastic PNP device in embodiment of the present invention BiCMOS technique;
Fig. 2-Figure 11 is the structural representation of vertical parastic PNP device in manufacture process in the BiCMOS technique of the embodiment of the present invention.
Embodiment
As shown in Figure 1, be the structural representation of the vertical parastic PNP device in embodiment of the present invention BiCMOS technique.Vertical parastic PNP device in embodiment of the present invention BiCMOS technique is formed on silicon substrate 1, and active area is formed with N-type deep trap 2 by shallow slot field oxygen 3 isolation on described silicon substrate 1, and described N-type deep trap 2 surrounds vertical parastic PNP device; Described vertical parastic PNP device comprises:
One collector region 7 is comprised of a P type ion implanted region that is formed in described active area, and the degree of depth of described collector region 7 is more than or equal to the bottom degree of depth of described shallow slot field oxygen 3.The process conditions of the P trap in the P type ion implanted region of described collector region 7 and CMOS technique are identical.
One counterfeit buried regions 6, P type ion implanted region by oxygen 3 bottoms, described shallow slot field that are formed at described collector region 7 all sides forms, described counterfeit buried regions 6 and described collector region 7 touch at described shallow slot field oxygen 3 bottom connections, draw collector electrode by the deep hole contact 12 that forms in the described shallow slot field at described counterfeit buried regions 6 tops oxygen 3.The process conditions of the P type Implantation of described counterfeit buried regions 6 are: implantation dosage is 1e14cm-2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
One base 5 is comprised of a N-type ion implanted region that is formed in described active area and be positioned at described collector region 7 tops, and described base 5 and described collector region 7 contact.The N-type Implantation of described base 55 will pass a silicon nitride hardmask, and the concrete technology condition is: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e14cm -2～1e16cm -2
One emitter window dielectric layer 8 is formed on described active area and extends on the described shallow slot field oxygen 3 of described active area week side; After being fallen by partial etching, described emitter window dielectric layer 8 defines emitter window and base stage Windows.Described emitter window dielectric layer 8 is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer 8 is 0.05 micron～0.4 micron.
Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described emitter window is exposed described base 5; Described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area has overlapping and described base 5 is exposed.The width of described emitter window is 0.2 micron～0.5 micron; The width of described base stage Windows is 0.2 micron～0.5 micron.
All be filled with polysilicon in described emitter window and described base stage Windows, this polysilicon top does not extend on described emitter window dielectric layer 8; Polysilicon in described emitter window is that the P type adulterates and forms emitter region 9a, and the polysilicon in described base stage Windows is that N-type is adulterated and forms base terminal 9b.The N-type doping process of described base terminal 9b shares the injection technology of the polysilicon emissioning area 9a of the NPN device in BiCMOS technique.The P type doping process of described emitter region 9a shares the P+ injection technology in BiCMOS technique.
Surface at described emitter region 9a and described base terminal 9b also is formed with metal silicide 10.Be formed with Metal Contact 13 and draw emitter on described emitter region 9a; Be formed with Metal Contact 13 and draw base stage on described base terminal 9b.Interlayer film 11 is formed at the surface of device and is used for emitter region, base and collector region and the metal level of device are isolated.Metal level 14 is used for realizing that emitter, base stage and the collector electrode of device be connected connection.
To shown in Figure 11, be the structural representation of vertical parastic PNP device in manufacture process in the BiCMOS technique of the embodiment of the present invention as Fig. 2.The manufacture method of the vertical parastic PNP device in embodiment of the present invention BiCMOS technique comprises the steps:
Step 1, as shown in Figure 2 adopts etching technics to be formed with source region and shallow trench 3a on silicon substrate 1.Adopt silicon nitride hardmask 4 during etching above described active area.The thickness of described silicon nitride hardmask 4 is 300 dust to 800 dusts.
Adopt ion implantation technology at the formation zone formation N-type deep trap 2. of the described vertical parastic PNP device of described silicon substrate 1
Step 2, is as shown in Figure 3 passed described silicon nitride hardmask 4 and is carried out the N-type Implantation at described active area and form base 5; The degree of depth of described base 5 is less than the bottom degree of depth of described shallow trench 3a.The process conditions of the N-type Implantation of described base 55 are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e14cm -2～1e16cm -2
Step 3, is as shown in Figure 4 carried out P type Implantation in described shallow trench 3a bottom and is formed counterfeit buried regions 6.The process conditions of the P type Implantation of described counterfeit buried regions 6 are: implantation dosage is 1e14cm-2～1e16cm -2, energy is for being boron or boron difluoride less than 15keV, implanted dopant.
Step 4, is as shown in Figure 5 carried out annealing process, and the horizontal and vertical diffusion of described counterfeit buried regions 6 also extends in described active area.The temperature of this annealing process is 900 ℃～1100 ℃, and annealing time is 10 minutes～100 minutes.
Step 5, is as shown in Figure 6 inserted silica and is formed shallow slot field oxygen 3 in described shallow trench 3a.
Step 6, is as shown in Figure 6 carried out P type Implantation and is formed collector region 7 in described active area, the degree of depth of described collector region 7 more than or equal to the bottom degree of depth of described shallow slot field oxygen 3 and and 6 formation of described counterfeit buried regions contact.The process conditions of the P trap in the P type ion implanted region of described collector region 7 and CMOS technique are identical.
Step 7, as shown in Figure 7, at the positive deposit one emitter window dielectric layer 8 of described silicon substrate 1, described emitter window dielectric layer 8 is positioned on described active area and extends on the described shallow slot field oxygen 3 of described active area week side.Described emitter window dielectric layer 8 is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer 8 is 0.05 micron～0.4 micron.
For integrated with the NPN device, before the described emitter window dielectric layer 8 of deposit, also be included in the step of the front definition of the front growth germanium silicon growth window deielectric-coating of whole silicon substrate 1, then the germanium silicon layer of growing, then adopt chemical wet etching technique that the zone of described vertical parastic PNP device is all opened, and definition window deielectric-coating before etching is removed the regional germanium silicon layer of described vertical parastic PNP device and removed this regional germanium silicon growth comprehensively.
Step 8, as shown in Figure 8, graphical definition goes out the formation zone of emitter window and base stage Windows with photoresist; Described emitter window dielectric layer 8 forms described emitter window and described base stage Windows take described photoetching offset plate figure as mask etching; Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area to be had overlapping; Etching adopts the etching of fixing time, and making 5 surfaces, described base of the bottom of described emitter window and described base stage Windows also remain with thickness is the described emitter window dielectric layer 8 of 0.01 micron～0.03 micron.The width of described emitter window is 0.2 micron～0.5 micron; The width of described base stage Windows is 0.2 micron～0.5 micron.
Step 9, as shown in Figure 9, the residual described emitter window dielectric layer in bottom that adopts wet-etching technology to remove described emitter window and described base stage Windows also exposes described base region surface, depositing polysilicon 9 comprehensively on described silicon substrate 1; The depositing technics of this polysilicon 9 shares the depositing technics of the emitter-polysilicon of NPN device.The thickness of described polysilicon 9 satisfies fills described emitter window and described base stage Windows fully, and polysilicon 9 is combined in described emitter window and described base stage Windows.Be preferably, the thickness of described polysilicon 9 is 0.2 micron～0.5 micron.
Step 10, as shown in figure 10, described polysilicon 9 is returned quarter, the described polysilicon 9 of described emitter window and described base stage Windows outside is all removed, and remaining described polysilicon 9 only is filled in described emitter window and described base stage Windows.Hui Kewei to described polysilicon 9 returns quarter comprehensively, does not adopt mask; Adopt the terminal point etching to detect, make etch-stop on described emitter window dielectric layer 8, guarantee that the polysilicon 9 on described emitter window dielectric layer 8 is etched totally.
Step 11, is as shown in figure 10 carried out the N-type doping to the polysilicon in described base stage Windows and is formed base terminal 9b; Polysilicon in described emitter window is carried out the doping of P type form emitter region 9a.The N-type doping process of described base terminal 9b shares the injection technology of the polysilicon emissioning area 9a of the NPN device in BiCMOS technique; The P+ that the P type doping process of described emitter region 9a shares in BiCMOS technique injects.
As shown in figure 11, form metal silicide 10 on the surface of described emitter region 9a and described base terminal 9b.
Step 12, as shown in Figure 1, at the positive deposit interlayer film 11 of described silicon substrate 1, this interlayer film 11 is used for the fabric of device and top-level metallic isolation.Form deep hole contact 12 and draw described collector electrode in the shallow slot field at described counterfeit buried regions 6 tops oxygen 3; Form Metal Contact 13 at 9a top, described emitter region and draw emitter; Form Metal Contact 13 at the top of described base terminal 9b and draw base stage.Form at last emitter, base stage and collector electrode that metal level 14 is used for realizing device and be connected connection.
Abovely by specific embodiment, the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (10)

1. the vertical parastic PNP device in a BiCMOS technique, be formed on silicon substrate, and active area is characterized in that by shallow slot field oxygen isolation, and described vertical parastic PNP device comprises:
One collector region is comprised of a P type ion implanted region that is formed in described active area, and the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen;
One counterfeit buried regions, P type ion implanted region by the oxygen bottom, described shallow slot field that is formed at all sides of described collector region forms, described counterfeit buried regions and described collector region touch at described shallow slot field oxygen bottom connection, draw collector electrode by the deep hole contact that forms in the oxygen of the described shallow slot field at described counterfeit buried regions top;
One base is comprised of a N-type ion implanted region that is formed in described active area and be positioned at described collector region top, and described base and described collector region contact;
One emitter window dielectric layer is formed on described active area and extends on the described shallow slot field oxygen of described active area week side; After being fallen by partial etching, described emitter window dielectric layer defines emitter window and base stage Windows;
Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described emitter window is exposed described base; Described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area to be had overlapping and described base is exposed;
All be filled with polysilicon in described emitter window and described base stage Windows, this polysilicon top does not extend on described emitter window dielectric layer; Polysilicon in described emitter window is that the P type adulterates and forms the emitter region, and the polysilicon in described base stage Windows is that N-type is adulterated and forms base terminal; Be formed with Metal Contact and draw emitter on described emitter region; Be formed with Metal Contact and draw base stage on described base terminal.
2. the vertical parastic PNP device in BiCMOS technique as claimed in claim 1, it is characterized in that: described emitter window dielectric layer is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer is 0.05 micron～0.4 micron.
3. the vertical parastic PNP device in BiCMOS technique as claimed in claim 1, it is characterized in that: the width of described emitter window is 0.2 micron～0.5 micron; The width of described base stage Windows is 0.2 micron～0.5 micron.
4. the manufacture method of the vertical parastic PNP device in a BiCMOS technique, is characterized in that, comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate; Adopt the silicon nitride hardmask during etching above described active area;
Step 2, pass described silicon nitride hardmask and carry out the N-type Implantation at described active area and form the base; The degree of depth of described base is less than the bottom degree of depth of described shallow trench;
Step 3, carry out P type Implantation in described shallow trench bottom and form counterfeit buried regions;
Step 4, carry out annealing process, the horizontal and vertical diffusion of described counterfeit buried regions also extends in described active area;
Step 5, insert silica form shallow slot field oxygen in described shallow trench;
Step 6, carry out P type Implantation form collector region in described active area, the degree of depth of described collector region more than or equal to the bottom degree of depth of described shallow slot field oxygen and and described counterfeit buried regions formation contact;
Step 7, at the positive deposit one emitter window dielectric layer of described silicon substrate, described emitter window dielectric layer is positioned on described active area and extends on the described shallow slot field oxygen of described active area week side;
Step 8, graphical definition goes out the formation zone of emitter window and base stage Windows with photoresist; Described emitter window dielectric layer forms described emitter window and described base stage Windows take described photoetching offset plate figure as mask etching; Described emitter window be positioned at described active area directly over and the size of described emitter window less than described active area size, described base stage Windows is positioned at described emitter window both sides and described base stage Windows and described active area to be had overlapping; Etching adopts the etching of fixing time, and makes the described base region surface of the bottom of described emitter window and described base stage Windows also remain with certain thickness described emitter window dielectric layer;
The residual described emitter window dielectric layer in bottom of step 9, the employing wet-etching technology described emitter window of removal and described base stage Windows also exposes described base region surface, comprehensive depositing polysilicon on described silicon substrate; The thickness of described polysilicon satisfies fills described emitter window and described base stage Windows fully;
Step 10, described polysilicon is returned quarter, the described polysilicon of described emitter window and described base stage Windows outside is all removed, remaining described polysilicon only is filled in described emitter window and described base stage Windows;
Step 11, the polysilicon in described base stage Windows is carried out N-type doping form base terminal; Polysilicon in described emitter window is carried out the doping of P type form the emitter region;
Step 12, form the deep hole contact draw described collector electrode in the oxygen of the shallow slot field at described counterfeit buried regions top; Form Metal Contact at top, described emitter region and draw emitter; Form Metal Contact at the top of described base terminal and draw base stage.
5. method as claimed in claim 4, it is characterized in that: the dielectric layer of emitter window described in step 7 is oxide-film or oxide-film and the film formed composite membrane of nitrogenize, and the thickness of described emitter window dielectric layer is 0.05 micron～0.4 micron.
6. method as claimed in claim 4, it is characterized in that: the width of emitter window described in step 8 is 0.2 micron～0.5 micron, the width of described base stage Windows is 0.2 micron～0.5 micron.
7. method as claimed in claim 4, it is characterized in that: in step 9, the thickness of the described polysilicon of deposit is 0.2 micron～0.5 micron.
8. method as claimed in claim 4, it is characterized in that: the Hui Kewei to described polysilicon in step 10 returns quarter comprehensively, does not adopt mask; Adopt the terminal point etching to detect, make etch-stop on described emitter window dielectric layer, guarantee that the polysilicon on described emitter window dielectric layer is etched totally.
9. method as claimed in claim 4, is characterized in that: the injection technology of the polysilicon emissioning area of the NPN device in the shared BiCMOS technique of the N-type doping process of base terminal described in step 11; The P+ that the P type doping process of emitter region described in step 11 shares in BiCMOS technique injects.
10. method as claimed in claim 4, is characterized in that: the technique that also is included in the surface formation metal silicide of described emitter region and described base terminal in step 11.
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