CN103165512A - Extremely thin semiconductor-on-insulator material and preparation method thereof - Google Patents

Extremely thin semiconductor-on-insulator material and preparation method thereof Download PDF

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CN103165512A
CN103165512A CN2011104187973A CN201110418797A CN103165512A CN 103165512 A CN103165512 A CN 103165512A CN 2011104187973 A CN2011104187973 A CN 2011104187973A CN 201110418797 A CN201110418797 A CN 201110418797A CN 103165512 A CN103165512 A CN 103165512A
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layer
insulator material
semiconductor
ultra
thin semiconductor
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姜海涛
狄增峰
张苗
卞剑涛
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

The invention provides extremely thin semiconductor-on-insulator material and a preparation method of the extremely thin semiconductor-on-insulator material. A plurality of Si1-xGex transition layers with a Ge component gradually varied in a gradient mode and a Si1-zGez stop layer are formed, a semiconductor layer is formed on the Si1-zGez stop layer, and then the semiconductor layer is linked with a substrate with an insulating layer, stripping is conducted through the intelligent stripping technology, and the extremely thin semiconductor-on-insulator material is prepared through surface treatment. By adopting the method, the extremely thin semiconductor-on-insulator material has the advantages of being thin in thickness, suitable for an integrated circuit with relatively small size, and capable of improving integration level of the integrated circuit. The preparation method of the extremely thin semiconductor-on-insulator material is easy to operate and suitable for the semiconductor technology of general industry.

Description

A kind of ultra-thin semiconductor-on-insulator material and preparation method thereof
Technical field
The present invention relates to a kind of semi-conducting material and preparation method thereof, particularly relate to a kind of ultra-thin semiconductor-on-insulator material and preparation method thereof.
Background technology
SOI (Silicon-On-Insulator, the silicon on dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and backing to bury oxide layer.By forming semiconductive thin film on insulator, the SOI material had advantages of body silicon incomparable: can realize the medium isolation of components and parts in integrated circuit, thoroughly eliminate the parasitic latch-up in the Bulk CMOS circuit; Adopt integrated circuit that this material is made to have also that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantage such as low voltage and low power circuits, therefore can say that SOI might become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.
Along with the VLSI technology enters 22nm node and following, running into stern challenge aspect the characteristic size that further reduces integrated circuit, must have than quantum jump at material and technique.In order to break through this technology barrier, the researcher proposes can continue to make device to continue micromation based on ultrathin insulating layer semiconductor-on-insulator (extremely thin Semiconductor-On-Insulator, ETSOI) device.The Specifeca tion speeification of the thickness effect device of SOI.Mainly determined by the thickness of ETSOI as threshold voltage (Vt).22nm node and following, SOI thickness need to be even thinner less than 10nm.At present, the thickness of SOI is often greater than 30nm.This just needs to continue to reduce its thickness.
Summary of the invention
The shortcoming of prior art and designs requirement in view of the above, the object of the present invention is to provide a kind of ultra-thin semiconductor-on-insulator material and preparation method thereof, be used for to solve the problem that prior art is difficult to obtain the semiconductor-on-insulator (ssoi) material of thickness ultrathin and high conformity.
Reach for achieving the above object other relevant purposes, the invention provides a kind of ultra-thin semiconductor-on-insulator material preparation method, it is characterized in that, described preparation method comprises the following steps at least:
1) provide the first substrate, form successively the Si of a plurality of Ge content gradually variationals on described the first substrate 1-xGe xLayer, wherein, 0＜x＜0.8, and this Si respectively 1-xGe xIn layer, Ge component x increases gradually, until form a Si 1-xGe xTop layer;
2) at described Si 1-xGe xForm Si on top layer 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer, wherein, 0＜z＜1, and at described Si 1-zGe zForm semiconductor layer on layer, then carry out Implantation with at described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zForm in layer and peel off the interface;
3) provide the second substrate with insulating barrier, the described insulating barrier of bonding and described semiconductor layer;
4) carry out the first annealing stage and make described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer is peeled off described peeling off at the interface, then carries out the second annealing stage to strengthen the bonding of described insulating barrier and described semiconductor layer, removes at last the Si on described semiconductor layer surface 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer is to complete described ultra-thin semiconductor-on-insulator material preparation.
In ultra-thin semiconductor-on-insulator material preparation method of the present invention, the material of described semiconductor layer is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr III-V compounds of group.
In ultra-thin semiconductor-on-insulator material preparation method of the present invention, the thickness of described semiconductor layer is 5nm～20nm.
At ultra-thin semiconductor-on-insulator material preparation method step 2 of the present invention), middle employing H, He, B or its combination in any are carried out Implantation.
In ultra-thin semiconductor-on-insulator material preparation method of the present invention, described step 3) also comprise before bonding described semiconductor layer and described insulating barrier are cleaned step with activation processing.
In ultra-thin semiconductor-on-insulator material preparation method of the present invention, described step 4) after the second annealing stage, also comprise described the first substrate is carried out the step that the substrate repair process can recycle it.
In ultra-thin semiconductor-on-insulator material preparation method of the present invention, described step 4) the middle described Si of selective corrosion method removal that adopts 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer.
The present invention also provides a kind of ultra-thin semiconductor-on-insulator material, comprises the substrate with insulating barrier, and described surface of insulating layer bonding has semiconductor layer, and wherein, the thickness of described semiconductor layer is 5n～20nm.
In ultra-thin semiconductor-on-insulator material of the present invention, the material of described semiconductor layer is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr III-V compounds of group.
As mentioned above, ultra-thin semiconductor-on-insulator material of the present invention and preparation method thereof has following beneficial effect: the present invention is by a plurality of Si of growth Ge component gradual change in gradient 1-xGe xTransition zone and Si 1-zGe zStop-layer is at Si 1-zGe zThen grown semiconductor layer on stop-layer makes described semiconductor layer and have the substrate bonding of insulating barrier, peels off by the smart peeling technology at last, prepares the ultra-thin semiconductor-on-insulator material through after surface treatment.Adopt the ultra-thin semiconductor-on-insulator material of this method preparation to have less thickness, be applicable to the integrated circuit than small-feature-size, can improve the integrated level of integrated circuit.Technological operation of the present invention is simple, is applicable to the semiconductor technology of general industry.
Description of drawings
Fig. 1 a～Fig. 1 b is shown as ultra-thin semiconductor-on-insulator material preparation method step 1 of the present invention) structural representation that presents.
Fig. 2 a～Fig. 2 c is shown as ultra-thin semiconductor-on-insulator material preparation method step 2 of the present invention) structural representation that presents.
Fig. 3 a～Fig. 3 b is shown as ultra-thin semiconductor-on-insulator material preparation method step 3 of the present invention) structural representation that presents.
Fig. 4 a～Fig. 5 b is shown as ultra-thin semiconductor-on-insulator material preparation method step 4 of the present invention) structural representation that presents.
The element numbers explanation
11 first substrates
12 Si 1-xGe xLayer
13 Si 1-xGe xTop layer
14 Si 1-zGe zLayer
15 semiconductor layers
21 second substrates
22 insulating barriers
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under spirit of the present invention not deviating from.
See also Fig. 1 a to Fig. 5 b.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
As shown in the figure, the invention provides a kind of ultra-thin semiconductor-on-insulator material preparation method, described preparation method comprises the following steps at least:
See also Fig. 1 a～Fig. 1 b, as shown in the figure, at first carry out step 1), the first substrate 11 is provided, form successively the Si of a plurality of Ge content gradually variationals on described the first substrate 11 1-xGe xLayer 12, wherein, 0＜x＜0.8, and this Si respectively 1-xGe xIn layer 12, Ge component x increases gradually, until form a Si 1-xGe xTop layer 13.In the present embodiment, described the first substrate 11 is the Si substrate, certainly, also is not limited in the Si substrate.
Particularly, adopt chemical vapour deposition technique to deposit successively the Si that a plurality of Ge components increase gradually on described the first substrate 11 1-xGe xLayer 12 certainly, also can adopt described respectively these Si of formation such as molecular beam epitaxy 1-xGe xLayer 12, wherein, described Si 1-xGe x Layer 12 is 1～30 layer, respectively this Si 1-xGe xThe thickness of layer 12 is 5～20nm, until form a Si 1-xGe xTop layer 13.In a concrete implementation process, Si 1-xGe xLayer 12 is 6 layers, is respectively Si 0.8Ge 0.2Layer, Si 0.7Ge 0.3Layer, Si 0.6Ge 0.4Layer, Si 0.5Ge 0.5Layer, Si 0.4Ge 0.6Layer and Si 0.3Ge 0.7Layer that is to say described Si 1-xGe x Top layer 13 is Si 0.3Ge 0.7Layer.
See also Fig. 2 a～Fig. 2 c, as shown in the figure, then carry out step 2), at described Si 1-xGe xForm Si on top layer 13 1-zGe zThe Si of the elements such as layer 14 or doping B, As or Sb 1-zGe zLayer 14, wherein, 0＜z＜1, and at described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe z Form semiconductor layer 15 on layer 14, then carry out Implantation with at described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zThe interface is peeled off in layer 14 interior formation.
Particularly, at described Si 1-xGe xAdopt chemical vapour deposition technique or molecular beam epitaxy to prepare Si on top layer 13 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14, wherein, then 0＜z＜1 adopts the methods such as chemical vapour deposition technique or molecular beam epitaxy at described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe z Form semiconductor layer 15 on layer 14, the material of described semiconductor layer 15 is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr the III-V compounds of group, thickness is 5nm～20nm.Then carry out Implantation with specific energy and angle from described semiconductor layer 15 surfaces, with at described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 interior formation one ion are assembled peels off the interface, and described ion can adopt H, He, B or its combination in any, and wherein, Implantation Energy is according to described semiconductor layer 15 and described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zThe thickness of layer 14 determines.
See also Fig. 3 a～Fig. 3 b, as shown in the figure, then carry out step 3), provide the second substrate 21 with insulating barrier 22, the described insulating barrier 22 of bonding and described semiconductor layer 15.In the present embodiment, also comprise before bonding described semiconductor layer 15 and described insulating barrier 22 are cleaned step with activation processing.Described the second substrate 21 is the Si substrate, and described insulating barrier 22 can be dielectric material arbitrarily, is preferably SiO 2Or Si 3N 4
See also Fig. 4 a～5b, as shown in the figure, carry out step 4 at last), carry out the first annealing stage and make described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 is peeled off described peeling off at the interface, then carries out the second annealing stage to strengthen the bonding of described insulating barrier 22 and described semiconductor layer 15, removes at last the Si on described semiconductor layer surface 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 is to complete described ultra-thin semiconductor-on-insulator material preparation.
In the present embodiment, at N 2Or in the atmosphere such as Ar, first be incubated so that the ion that injects is assembled at the described near interface of peeling off at 250 ℃～350 ℃, then be warming up to 450 ℃～550 ℃ insulations and make the ion of gathering form bubble at the described near interface of peeling off, bubble expands gradually and finally makes described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 is peeled off described peeling off at the interface, then is warming up to 900 ℃～1100 ℃ insulations to strengthen the bond strength of described insulating barrier 22 and described semiconductor layer 15.After peeling off, described bonding structure produces two lift-off structure, wherein, as shown in Fig. 4 a～Fig. 4 b, the lift-off structure that contains described the first substrate 11 is carried out the substrate repair process it can be recycled, particularly, use wet etching to remove the Si on described the first substrate 11 surfaces 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 and this Si respectively 1-xGe xLayer 12, and polishing is carried out on described the first substrate 11 surfaces, for described step 1) use.As shown in Fig. 5 a～Fig. 5 b, the lift-off structure that contains the second substrate 21, insulating barrier 22 and semiconductor layer 15 is carried out selective corrosion, to remove described Si 1-zGe zThe Si of layer 14 or doping B, As or Sb element 1-zGe zLayer 14 is finally to prepare the ultra-thin semiconductor-on-insulator material.
See also Fig. 5 b, as shown in the figure, the present invention also provides a kind of ultra-thin semiconductor-on-insulator material, comprises the substrate 21 with insulating barrier 22, and described insulating barrier 22 surface bonds have semiconductor layer 15, and wherein, the thickness of described semiconductor layer 15 is 5n～20nm.
In the present embodiment, the material of described semiconductor layer 15 is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr III-V compounds of group.
In sum, ultra-thin semiconductor-on-insulator material of the present invention and preparation method thereof is by a plurality of Si of growth Ge component gradual change in gradient 1-xGe xTransition zone and Si 1-zGe zStop-layer is at Si 1-zGe zThen grown semiconductor layer on stop-layer makes described semiconductor layer and have the substrate bonding of insulating barrier, peels off by the smart peeling technology at last, prepares the ultra-thin semiconductor-on-insulator material through after surface treatment.Adopt the ultra-thin semiconductor-on-insulator material of this method preparation to have less thickness, be applicable to the integrated circuit than small-feature-size, can improve the integrated level of integrated circuit.Technological operation of the present invention is simple, is applicable to the semiconductor technology of general industry.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can under spirit of the present invention and category, modify or change above-described embodiment.Therefore, have in technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of completing under disclosed spirit and technological thought, must be contained by claim of the present invention.

Claims (9)

1. a ultra-thin semiconductor-on-insulator material preparation method, is characterized in that, described preparation method comprises the following steps at least:
1) provide the first substrate, form successively the Si of a plurality of Ge content gradually variationals on described the first substrate 1-xGe xLayer, wherein, 0＜x＜0.8, and this Si respectively 1-xGe xIn layer, Ge component x increases gradually, until form a Si 1-xGe xTop layer;
2) at described Si 1-xGe xForm Si on top layer 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer, wherein, 0＜z＜1, and at described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zForm semiconductor layer on layer, then carry out Implantation with at described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zForm in layer and peel off the interface;
3) provide the second substrate with insulating barrier, the described insulating barrier of bonding and described semiconductor layer;
4) carry out the first annealing stage and make described Si 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer is peeled off described peeling off at the interface, then carries out the second annealing stage to strengthen the bonding of described insulating barrier and described semiconductor layer, removes at last the Si on described semiconductor layer surface 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer is to complete described ultra-thin semiconductor-on-insulator material preparation.
2. ultra-thin semiconductor-on-insulator material preparation method according to claim 1, it is characterized in that: the material of described semiconductor layer is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr III-V compounds of group.
3. ultra-thin semiconductor-on-insulator material preparation method according to claim 1 and 2, it is characterized in that: the thickness of described semiconductor layer is 5nm～20nm.
Ultra-thin semiconductor-on-insulator material according to claim 1 and the preparation method, it is characterized in that: adopt at least a Implantation that carries out in H, He or B ion described step 2).
5. ultra-thin semiconductor-on-insulator material preparation method according to claim 1 is characterized in that: described step 3) also comprise before bonding described semiconductor layer and described insulating barrier are cleaned step with activation processing.
6. ultra-thin semiconductor-on-insulator material preparation method according to claim 1, is characterized in that: described step 4) after the second annealing stage, also comprise described the first substrate is carried out the step that the substrate repair process can recycle it.
7. ultra-thin semiconductor-on-insulator material preparation method according to claim 1, is characterized in that: adopt the selective corrosion method to remove described Si described step 4) 1-zGe zThe Si of layer or doping B, As or Sb element 1-zGe zLayer.
8. a ultra-thin semiconductor-on-insulator material, comprise the substrate with insulating barrier, it is characterized in that: described surface of insulating layer bonding has semiconductor layer, and wherein, the thickness of described semiconductor layer is 5n～20nm.
9. ultra-thin semiconductor-on-insulator material according to claim 8, it is characterized in that: the material of described semiconductor layer is Si, Ge, SiC, Si 1-m-n-pGe mC nSn pOr III-V compounds of group.
CN2011104187973A 2011-12-14 2011-12-14 Extremely thin semiconductor-on-insulator material and preparation method thereof Pending CN103165512A (en)

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Application publication date: 20130619