CN103165512A - Extremely thin semiconductor-on-insulator material and preparation method thereof - Google Patents

Extremely thin semiconductor-on-insulator material and preparation method thereof Download PDF

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CN103165512A
CN103165512A CN 201110418797 CN201110418797A CN103165512A CN 103165512 A CN103165512 A CN 103165512A CN 201110418797 CN201110418797 CN 201110418797 CN 201110418797 A CN201110418797 A CN 201110418797A CN 103165512 A CN103165512 A CN 103165512A
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semiconductor
thin
material
extremely
insulator
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CN 201110418797
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Chinese (zh)
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姜海涛
狄增峰
张苗
卞剑涛
王曦
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中国科学院上海微系统与信息技术研究所
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Abstract

The invention provides extremely thin semiconductor-on-insulator material and a preparation method of the extremely thin semiconductor-on-insulator material. A plurality of Si1-xGex transition layers with a Ge component gradually varied in a gradient mode and a Si1-zGez stop layer are formed, a semiconductor layer is formed on the Si1-zGez stop layer, and then the semiconductor layer is linked with a substrate with an insulating layer, stripping is conducted through the intelligent stripping technology, and the extremely thin semiconductor-on-insulator material is prepared through surface treatment. By adopting the method, the extremely thin semiconductor-on-insulator material has the advantages of being thin in thickness, suitable for an integrated circuit with relatively small size, and capable of improving integration level of the integrated circuit. The preparation method of the extremely thin semiconductor-on-insulator material is easy to operate and suitable for the semiconductor technology of general industry.

Description

一种超薄绝缘体上半导体材料及其制备方法 An ultra-thin semiconductor-on-insulator material and method

技术领域 FIELD

[0001] 本发明涉及一种半导体材料及其制备方法,特别是涉及一种超薄绝缘体上半导体材料及其制备方法。 [0001] The present invention relates to a semiconductor material and a preparation method, particularly to a thin insulator semiconductor material and method of preparation.

背景技术 Background technique

[0002] SOI (Silicon-On-1nsulator,绝缘衬底上的娃)技术是在顶层娃和背衬底之间引入了一层埋氧化层。 [0002] SOI (Silicon-On-1nsulator, baby on the insulating substrate) technology is between the top layer and the back substrate is introduced into baby buried oxide layer. 通过在绝缘体上形成半导体薄膜,SOI材料具有了体硅所无法比拟的优点:可以实现集成电路中元器件的介质隔离,彻底消除了体硅CMOS电路中的寄生闩锁效应;采用这种材料制成的集成电路还具有寄生电容小、集成密度高、速度快、工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势,因此可以说SOI将有可能成为深亚微米的低压、低功耗集成电路的主流技术。 By forming a semiconductor thin film on the insulator, the SOI material has the advantage of bulk silicon unmatched: an integrated circuit can be realized dielectric isolation of components, the complete elimination of parasitic latch-up in bulk CMOS circuit; manufactured by using this material into the integrated circuit further having a parasitic capacitance, high integration density, high speed, simple process, small short-channel effect and the advantage is particularly suitable for low voltage and low power circuits and the like, it can be said SOI will likely become a low-pressure deep sub-micron , mainstream technology low-power integrated circuits.

[0003] 随着VLSI技术进入22nm节点及以下,在进一步减小集成电路的特征尺寸方面遇到了严峻的挑战,必须在材料和工艺有较大突破。 [0003] As VLSI technology into the 22nm node and below, encountered a serious challenge in further reducing the integrated circuit feature dimensions, must be a major breakthrough in materials and workmanship. 为了突破此技术障碍,研究人员提出基于超薄绝缘层上半导体(extremely thin Semiconductor-On-1nsulator, ETS0I)器件能够继续使器件持续缩微化。 In order to break through this barrier technique, researchers have proposed based on the ultra-thin insulating layer of a semiconductor (extremely thin Semiconductor-On-1nsulator, ETS0I) means the device can continue sustained microfilm. SOI的厚度影响器件的主要性能参数。 The thickness of the SOI device of the main performance parameters caused. 如阈值电压(Vt)主要由ETSOI的厚度决定。 The threshold voltage (Vt) is mainly determined by the thickness of the ETSOI. 22nm节点及以下,SOI厚度需要小于IOnm甚至更薄。 22nm node and beyond, SOI desired thickness of less than IOnm or even thinner. 目前,SOI的厚度往往大于30nm。 Currently, often greater than the thickness of the SOI 30nm. 这就需要继续降低其厚度。 This needs to continue to reduce its thickness.

发明内容 SUMMARY

[0004] 鉴于以上所述现有技术的缺点和器件设计要求,本发明的目的在于提供一种超薄绝缘体上半导体材料及其制备方法,用于解决现有技术中难以获得厚度超薄且一致性好的绝缘体上半导体材料的问题。 [0004] In view of the foregoing disadvantages of the prior art and device design requirements, object of the present invention to provide a method of preparing a semiconductor material and an ultra-thin insulation, for solving the prior art is difficult to obtain uniform and ultrathin good insulator semiconductor material issues.

[0005]为实现上述目的及其他相关目的,本发明提供一种超薄绝缘体上半导体材料的制备方法,其特征在于,所述制备方法至少包括以下步骤: [0005] To achieve the above objects and other related objects, the present invention provides a method for preparing ultra-thin semiconductor-on-insulator material, characterized in that said method comprises preparing at least the following steps:

[0006] I)提供第一衬底,在所述第一衬底上依次形成多个Ge组分渐变的SihGex层,其中,0 < X < 0.8,且各该SihGex层中Ge组分x逐渐增大,直至形成一Si^xGex顶层; [0006] I) providing a first substrate, a plurality of sequentially formed SihGex Ge composition graded layer on the first substrate, wherein, 0 <X <0.8, and each of the layers SihGex x Ge content gradually increases, until the formation of a Si ^ xGex top;

[0007] 2)在所述SihGex顶层上形成Si1=Gez层或掺杂B、As、或Sb元素的Si1=Gez层,其中,O < z < I,并在所述SihGez层上形成半导体层,然后进行离子注入以在所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层内形成剥离界面; Si1 [0007] 2) formed Si1 = Gez layer on the top layer or doped SihGex B, As, or Sb = Gez element layer, wherein, O <z <I, and forming a semiconductor layer on the layer SihGez and then the ion implantation layer Gez the SihGez layer or a doped Si1 B, As, or Sb element is formed = peeling at the interface;

[0008] 3)提供具有绝缘层的第二衬底,键合所述绝缘层与所述半导体层; A second substrate [0008] 3) provided with an insulation layer, bonding the insulating layer and the semiconductor layer;

[0009] 4)进行第一退火阶段使所述Si1=Gez层或掺杂B、As、或Sb元素的Si1=Gez层在所述剥离界面处剥离,然后进行第二退火阶段以加强所述绝缘层与所述半导体层的键合,最后去除所述半导体层表面上的或掺杂B、As、或Sb兀素的Si1=Gez层,以完成所述超薄绝缘体上半导体材料的制备。 [0009] 4) a first annealing stage the layer or doped Si1 = Gez B, As, or Si1 Sb = Gez elements in the peeling layer peeling at the interface, followed by a second annealing stage to enhance the bonding the insulating layer and the semiconductor layer, and finally removing or on the surface of the semiconductor layer doped with B, As, or Sb Wu pigment Si1 = Gez layer to complete the preparation of semiconductor material on said thin insulator.

[0010] 在本发明的超薄绝缘体上半导体材料的制备方法中,所述半导体层的材料为S1、Ge、SiC、Si1ItpGemCnSnp 或II1-V 族化合物。 [0010] In the ultra-thin insulator of the invention of preparing a semiconductor material, the material of the semiconductor layer S1, Ge, SiC, Si1ItpGemCnSnp or II1-V compound. [0011] 在本发明的超薄绝缘体上半导体材料的制备方法中,所述半导体层的厚度为5nm 〜20nmo [0011] In the ultra-thin insulator of the invention of preparing a semiconductor material, the thickness of the semiconductor layer is 5nm ~20nmo

[0012] 在本发明的超薄绝缘体上半导体材料的制备方法步骤2),中采用H、He、B或其任意组合进行离子注入。 [0012] Preparation Step 2 of semiconductor material), the use of H, He, B or any combination thereof in a thin insulator of the invention is ion implantation.

[0013] 在本发明的超薄绝缘体上半导体材料的制备方法中,所述步骤3)在键合前还包括对所述半导体层与所述绝缘层进行清洗与活化处理的步骤。 [0013] In the present invention, the ultra-thin insulator semiconductor material preparation method, the step 3) a step of cleaning and activation of the semiconductor layer and the insulating layer further comprises prior to bonding.

[0014] 在本发明的超薄绝缘体上半导体材料的制备方法中,所述步骤4)在第二退火阶段后,还包括对所述第一衬底进行衬底修复处理使其可以循环使用的步骤。 [0014] In the present invention, the ultra-thin insulator semiconductor material preparation method, the step 4) after the second annealing stage, the first substrate further comprises a substrate for a repair process that it can be recycled step.

[0015] 在本发明的超薄绝缘体上半导体材料的制备方法中,所述步骤4)中采用选择性腐蚀方法去除所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层。 [0015] In the present invention, the ultra-thin insulator semiconductor material preparation method, the step selective etching method 4) removing said layer or doped SihGez B, As, or Sb element Si1 = Gez layer.

[0016] 本发明还提供一种超薄绝缘体上半导体材料,包括具有绝缘层的衬底,所述绝缘层表面键合有半导体层,其中,所述半导体层的厚度为5n〜20nm。 [0016] The present invention also provides an ultra-thin semiconductor-on-insulator material comprising a substrate having an insulating layer, the insulating layer is bonded to the surface of the semiconductor layer, wherein a thickness of the semiconductor layer is 5n~20nm.

[0017] 在本发明的超薄绝缘体上半导体材料中,所述半导体层的材料为S1、Ge、SiC、SilmGemCnSnp 或II1-V 族化合物。 [0017] In the present invention, the insulator thin semiconductor material, the semiconductor material layer is S1, Ge, SiC, SilmGemCnSnp or II1-V compound.

[0018] 如上所述,本发明的超薄绝缘体上半导体材料及其制备方法,具有以下有益效果:本发明通过生长Ge组分呈梯度渐变的多个SihGex过渡层及Si1=Gez停止层,在Si1=Gez停止层上生长半导体层,然后使所述半导体层与一具有绝缘层的衬底键合,最后通过智能剥离技术进行剥离,经过表面处理后制备出超薄绝缘体上半导体材料。 [0018] As described above, the thin insulator semiconductor material of the present invention and its preparation method has the following advantages: the present invention was more gradual and SihGex transition gradient Si1 = Gez stop layer is formed by growing Ge content, in Si1 = Gez stop layer grown on the semiconductor layer, the semiconductor layer and then bonded to a substrate with an insulation layer, and finally peeling by smart Cut technology, after the surface treatment were prepared the ultra-thin insulator semiconductor material. 采用本方法制备的超薄绝缘体上半导体材料具有较小的厚度,适用于较小特征尺寸的集成电路,可以提高集成电路的集成度。 A thin insulator prepared using the method of a semiconductor material having a small thickness, for smaller feature sizes of integrated circuits can be increased integration of integrated circuits. 本发明工艺操作简单,适用于一般工业的半导体工艺。 The present invention has simple process operation, process is generally applied to the semiconductor industry.

附图说明 BRIEF DESCRIPTION

[0019] 图1a〜图1b显示为本发明的超薄绝缘体上半导体材料的制备方法步骤I)所呈现的结构示意图。 [0019] FIG 1a~ FIG. 1b a schematic structural diagram of the presented method of preparing the ultra-thin insulator of the present invention, the step of semiconductor material I) display.

[0020] 图2a〜图2c显示为本发明的超薄绝缘体上半导体材料的制备方法步骤2)所呈现的结构示意图。 [0020] FIG 2a~ schematic structural diagram of FIG. 2c preparing the ultra-thin insulator semiconductor material of the present invention step 2) presented display.

[0021] 图3a〜图3b显示为本发明的超薄绝缘体上半导体材料的制备方法步骤3)所呈现的结构示意图。 [0021] FIG 3a~ schematic structural diagram of FIG. 3b preparing the ultra-thin insulator semiconductor material of the present invention in step 3) presented display.

[0022] 图4a〜图5b显示为本发明的超薄绝缘体上半导体材料的制备方法步骤4)所呈现的结构示意图。 [0022] FIG 4a~ schematic structural diagram of FIG. 5b prepared on-insulator thin semiconductor material of the present invention in step 4) of the presented display.

[0023] 元件标号说明 [0023] DESCRIPTION OF REFERENCE NUMERALS element

[0024] 11 第一衬底 [0024] The first substrate 11

[0025] 12 SihGex 层 [0025] 12 SihGex layer

[0026] 13 SihGex 顶层 [0026] 13 SihGex top

[0027] 14 S“_zGez 层 [0027] 14 S "_zGez layer

[0028] 15 半导体层 [0028] The semiconductor layer 15

[0029] 21 第二衬底 [0029] The second substrate 21

[0030] 22 绝缘层具体实施方式 [0030] DETAILED DESCRIPTION insulating layer 22

[0031] 以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。 [0031] Hereinafter, an embodiment of the present invention by certain specific examples, those skilled in the art disclosed in this specification may readily understand the content of other advantages and effects of the present invention. 本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。 The present invention may also be implemented or applied through other different specific embodiments, the details of the specification may be carried out in various modified or changed without departing from the spirit of the invention based on various concepts and applications.

[0032] 请参阅图1a至图5b。 [0032] Please refer to FIG. 1a to Figure 5b. The 需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。 Incidentally, the present embodiment illustrates a schematic manner only examples provided to illustrate the basic idea of ​​the invention, then the drawings shows only related to the present invention, the number of components in the assembly when not in accordance with the actual embodiment, the shape and drawn to scale, its actual implementation of each component type, number and proportion of changes may be as a free, and the layout of the components may also be more complex patterns.

[0033] 如图所示,本发明提供一种超薄绝缘体上半导体材料的制备方法,所述制备方法至少包括以下步骤: [0033] As shown, the present invention provides a method for preparing ultra-thin semiconductor-on-insulator material, the manufacturing method comprising at least the steps of:

[0034] 请参阅图1a〜图lb,如图所示,首先进行步骤I),提供第一衬底11,在所述第一衬底11上依次形成多个Ge组分渐变的Si^Gex层12,其中,O < x < 0.8,且各该Si^Gex层12中Ge组分X逐渐增大,直至形成一SihGex顶层13。 [0034] FIG 1a~ see FIG. Lb, as shown, first, the I step), providing a first substrate 11, a plurality of sequentially formed on a graded Ge content of the first substrate 11 of Si ^ Gex layer 12, which, O <x ​​<0.8, and each of the Si ^ Gex layer Ge content X 12 gradually increases, until the formation of a top layer 13 SihGex. 在本实施例中,所述第一衬底11为Si衬底,当然,也并不仅限于Si衬底。 In the present embodiment, the first substrate 11 is a Si substrate, of course, not limited to the Si substrate.

[0035] 具体地,采用化学气相沉积法在所述第一衬底11上依次沉积多个Ge组分逐渐增大的SihGex层12,当然,也可以采用分子束外延法等形成所述的各该SihGex层12,其中,所述SihGex层12为I〜30层,各该Si1Jex层12的厚度为5〜20nm,直至形成一Si1^xGex顶层13。 [0035] Specifically, a SihGex layer 12 are sequentially deposited by chemical vapor deposition on a plurality of Ge content gradually increases the first substrate 11, of course, may be used for each molecular beam epitaxy method, or the like according to the SihGex layer 12, wherein the layer I~30 SihGex layer 12, the thickness of each layer 12 is Si1Jex 5~20nm, until the formation of a Si1 ^ xGex top 13. 在一个具体的实施过程中,SihGexM 12为6层,分别为Sia8Gea2层、Sia7Gea3层、Sia6Gea4 层、Sia5Gea5 层、Sia4Gea6 层以及Si。 In a particular embodiment of the process, SihGexM 12 of layer 6, respectively Sia8Gea2 layer, Sia7Gea3 layer, Sia6Gea4 layer, Sia5Gea5 layer, Sia4Gea6 layer, and Si. .3GeQ.7 层,也就是说,所述SipxGex 顶层13 为 .3GeQ.7 layer, i.e., the top layer 13 is SipxGex

Si0.3^®0.7 层。 Si0.3 ^ ®0.7 layer.

[0036] 请参阅图2a〜图2c,如图所示,然后进行步骤2),在所述SihGex顶层13上形成SihGez层14或掺杂B、As、或Sb等元素的Si1=Gez层14,其中,0<z < I,并在所述Si1=Gez层14或掺杂B、As、或Sb元素的SihGez层14上形成半导体层15,然后进行离子注入以在所述Si1=Gez层14或掺杂B、As、或Sb元素的Si1=Gez层14内形成剥离界面。 [0036] Please refer to FIG 2a~ to Figure 2c, as shown, and step 2), is formed on the layer SihGez SihGex top layer doping 1314 or B, As, or Sb element layer 14 Si1 = Gez where, 0 <z <I, and the Si1 = Gez layer 15 is formed on the semiconductor layer 1414 doped or SihGez layer B, As, Sb, or elements, and then ion implantation layer in the Si1 = Gez 14 or doping B, As, or Sb is formed of Si1 = 14 Gez inner debonding layer.

[0037] 具体地,在所述SihGex顶层13上采用化学气相沉积法或分子束外延法制备 Preparation [0037] In particular, chemical vapor deposition or molecular SihGex top layer 13 on the beam epitaxy SYSTEM

14或掺杂B、As、或Sb元素的SihGez层14,其中,O < z < I,然后采用化学气相沉积法或分子束外延法等方法在所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层14上形成半导体层15,所述半导体层15的材料为S1、Ge、SiC、SilmGemCnSnp或II1-V族化合物,厚度为5nm〜20nm。 14 or doping B, As, or Sb element SihGez layer 14, wherein, O <z <I, and using chemical vapor deposition or molecular beam epitaxy method or the like in the SihGez doping layer B, As, or = Si1 Sb element is formed on the semiconductor layer 14 Gez layer 15, the material of the semiconductor layer 15 is S1, Ge, SiC, SilmGemCnSnp II1-V compound, or a thickness of 5nm~20nm. 然后以特定的能量与角度从所述半导体层15表面进行离子注入,以在所述Si1=Gez层14或掺杂B、As、或Sb元素的Si1=Gez层14或掺杂B、As、或Sb元素的SihGez层14内形成一离子聚集的剥离界面,所述离子可采用H、He、B或其任意组合,其中,注入能量根据所述半导体层15及所述SihGez层14或掺杂B、As、或Sb元素的Si1=Gez层14的厚度决定。 Then a specific energy 15 from the angle ion implantation surface of the semiconductor layer, the Si1 = Gez to 14 or a doped layer B, As, or Si1 Sb = Gez element layer 14 doped or B, As, or Sb layer formed SihGez element 14 is aggregated to a peeling interface, the ions can be H, He, B or any combination thereof, wherein the implantation energy in accordance with the semiconductor layer 15 and the layer 14 or the doped SihGez Si1 B, As, or Sb = thickness determines Gez element layer 14.

[0038] 请参阅图3a〜图3b,如图所示,接着进行步骤3),提供具有绝缘层22的第二衬底21,键合所述绝缘层22与所述半导体层15。 [0038] Please refer to FIG 3a~ to Figure 3b, as shown, followed by step 3), providing a second substrate 21 having the insulating layer 22, the insulating bonding layer 22 and the semiconductor layer 15. 在本实施例中,在键合前还包括对所述半导体层15与所述绝缘层22进行清洗与活化处理的步骤。 In the present embodiment, further comprising prior to the bonding of the semiconductor layer 15 and the insulating layer 22 and the washing step of the activation process. 所述第二衬底21为Si衬底,所述绝缘层22可为任意的介电材料,优选为SiO2或Si3N4。 The second substrate 21 is a Si substrate, the insulating layer 22 may be any dielectric material, preferably SiO2 or Si3N4.

[0039] 请参阅图4a〜5b,如图所示,最后进行步骤4),进行第一退火阶段使所述Si1=Gez层14或掺杂B、As、或Sb元素的SihGez层14在所述剥离界面处剥离,然后进行第二退火阶段以加强所述绝缘层22与所述半导体层15的键合,最后去除所述半导体层表面上的SipzGez层14或掺杂B、As、或Sb元素的SihGez层14,以完成所述超薄绝缘体上半导体材料的制备。 [0039] Referring to FIG 4a~5b, as shown, the final step 4), a first annealing stage the Si1 = Gez or doped layer 14 B, As, or Sb element layer 14 are SihGez peeling said peel at the interface, followed by a second annealing stage to enhance the bonding of the insulating layer 22 and the semiconductor layer 15, and finally removed SipzGez layer on the surface of the doped semiconductor layer 14 or B, As, or Sb SihGez layer elements 14, to complete the preparation of ultra-thin semiconductor-on-insulator material.

[0040] 在本实施例中,在N2或Ar等气氛中,先在250°C〜350°C保温以使注入的离子在所述剥离界面附近聚集,然后升温至450°C〜550°C保温使聚集的离子在所述剥离界面附近形成气泡,气泡逐渐膨胀并最终使所述SihGez层14或掺杂B、As、或Sb元素的Si1=Gez层14在所述剥离界面处剥离,接着升温至900°C〜1100°C保温以加强所述绝缘层22与所述半导体层15的键合强度。 [0040] In the present embodiment, N2 or the like in an Ar atmosphere, first at 250 ° C~350 ° C to heat the implanted ions in the vicinity of the interface peeling aggregate, then warmed to 450 ° C~550 ° C insulation ions aggregated gas bubbles formed in the vicinity of the interface peeling, and eventually the bubble is progressively expanded SihGez said doped layer 14 or B, As, or Sb element Si1 = Gez layer 14 is peeled off at the peeling interface, then warmed to 900 ° C~1100 ° C incubation with 22 to enhance the bond strength of the semiconductor layer 15 is bonded to the insulating layer. 所述键合结构剥离以后产生两个剥离结构,其中,如图4a〜图4b所示,对含有所述第一衬底11的剥离结构进行衬底修复处理使其可以循环使用,具体地,使用湿法刻蚀去除所述第一衬底11表面的SihGez层14或掺杂B、As、或Sb兀素的Si1=Gez层14以及各该SihGex层12,并对所述第一衬底11表面进行抛光,以供所述步骤I)使用。 The bonded structure produced after the two release release structure, which, as shown in FIG. 4b 4a~, the peeling structure containing the first substrate 11 is treated to fix the substrate can be recycled, in particular, removed by wet etching using the SihGez surface of the first layer 11 or substrate 14 doped with B, As, or Sb Wu pigment Si1 = Gez SihGex layer 14, and each of the layers 12, and the first substrate polishing the surface 11, for the step I) used. 如图5a〜图5b所示,对含有第二衬底21、绝缘层22以及半导体层15的剥离结构进行选择性腐蚀,以去除所述的SihGez层14或掺杂B、As、或Sb元素的Si^zGez层14,以最终制备出超薄绝缘体上半导体材料。 As shown in FIG. 5b 5a~, 21, the release layer 22 and the semiconductor structure of the insulating layer 15 containing the second substrate is selectively etched to remove the layer 14 or SihGez doping B, As, or Sb element the Si ^ zGez layer 14 to prepare the final thin insulator semiconductor material.

[0041] 请参阅图5b,如图所示,本发明还提供一种超薄绝缘体上半导体材料,包括具有绝缘层22的衬底21,所述绝缘层22表面键合有半导体层15,其中,所述半导体层15的厚度为5n 〜20nmo [0041] Referring to FIG. 5b, as shown, the present invention also provides an ultra-thin insulator semiconductor material, an insulating layer 22 includes a substrate 21, the insulating layer 22 is bonded to the surface of the semiconductor layer 15, wherein thickness of the semiconductor layer 15 to 5n ~20nmo

[0042] 在本实施例中,所述半导体层15的材料为SlGhSiaSi1ItpGemCnSnp或II1-V族化合物。 [0042] In the present embodiment, the material of the semiconductor layer 15 is SlGhSiaSi1ItpGemCnSnp or II1-V compound.

[0043] 综上所述,本发明的超薄绝缘体上半导体材料及其制备方法,通过生长Ge组分呈梯度渐变的多个SihGex过渡层及SihGez停止层,在Si1=Gez停止层上生长半导体层,然后使所述半导体层与一具有绝缘层的衬底键合,最后通过智能剥离技术进行剥离,经过表面处理后制备出超薄绝缘体上半导体材料。 [0043] In summary, the present invention thin insulator semiconductor material and a preparation method, by growing the gradient graded Ge content of the plurality of transition layers and SihGez SihGex stop layer, stopping on the semiconductor layer grown Si1 = Gez layer, the semiconductor layer and then bonded to a substrate with an insulation layer, and finally peeling by smart Cut technology, after the surface treatment were prepared the ultra-thin insulator semiconductor material. 采用本方法制备的超薄绝缘体上半导体材料具有较小的厚度,适用于较小特征尺寸的集成电路,可以提高集成电路的集成度。 A thin insulator prepared using the method of a semiconductor material having a small thickness, for smaller feature sizes of integrated circuits can be increased integration of integrated circuits. 本发明工艺操作简单,适用于一般工业的半导体工艺。 The present invention has simple process operation, process is generally applied to the semiconductor industry. 所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。 Therefore, the present invention effectively overcomes the drawbacks of the prior art and with a high degree of value industry.

[0044] 上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。 [0044] The above-described embodiments are only illustrative of the principles and effect of the present invention, the present invention is not intended to be limiting. 任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。 Any person skilled in this art can be made at without departing from the spirit and scope of the present invention, the above-described embodiments can be modified or changed. 因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。 Thus, one skilled in the art that whenever all having ordinary knowledge in the technical ideas and spirit of the present invention is disclosed without departing from the completed equivalent modified or altered, yet the claims shall be encompassed by the present invention.

Claims (9)

  1. 1.一种超薄绝缘体上半导体材料的制备方法,其特征在于,所述制备方法至少包括以下步骤: 1)提供第一衬底,在所述第一衬底上依次形成多个Ge组分渐变的311_!^6!£层,其中,O< X < 0.8,且各该SipxGex层中Ge组分x逐渐增大,直至形成一SihGex顶层; 2)在所述SihGex顶层上形成SihGez层或掺杂B、As、或Sb元素的Si1=Gez层,其中,O < z < 1,并在所述或掺杂B、As、或Sb元素的SihGez层上形成半导体层,然后进行离子注入以在所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层内形成剥离界面; 3)提供具有绝缘层的第二衬底,键合所述绝缘层与所述半导体层; 4)进行第一退火阶段使所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层在所述剥离界面处剥离,然后进行第二退火阶段以加强所述绝缘层与所述半导体层的键合,最后去除所述半导体层表面上的SihGez层或掺杂B、As、或Sb元素的Si1=Gez层, The method of preparing a semiconductor material on an insulator An ultrathin, characterized in that said method comprises preparing at least the following steps: 1) providing a first substrate, a plurality of sequentially formed on the Ge content in said first substrate !! graded layer 311 _ ^ 6 £, wherein, O <x ​​<0.8, and each of the layers SipxGex x Ge content gradually increases, until the formation of a top layer SihGex; 2) is formed SihGez layer on the top layer or SihGex doped with B, As, or Sb element Si1 = Gez layer, wherein, O <z <1, and a semiconductor layer formed on the doped or B, As, or Sb element SihGez layer, followed by ion implantation Si1 SihGez formed in said doped layer or B, As, Sb, or elements within the interface delamination = Gez; 3) providing a second substrate having an insulating layer, bonding the insulating layer and the semiconductor layer; 4 ) a first annealing stage or the SihGez doped layer B, As, or Sb element Si1 = Gez said peeling layer peeling at the interface, followed by a second annealing stage to enhance the insulating layer and the semiconductor bonding layer, and finally removing SihGez layer on the surface of the semiconductor layer or a doped B, As, or Sb element Si1 = Gez layer, 完成所述超薄绝缘体上半导体材料的制备。 Completing the preparation of ultra-thin semiconductor material on an insulator.
  2. 2.根据权利要求1所述的超薄绝缘体上半导体材料的制备方法,其特征在于:所述半导体层的材料为S1、Ge、SiC, SilmGemCnSnp或II1-V族化合物。 2. Preparation method of a semiconductor material on said thin insulator according to claim 1, wherein: the material of the semiconductor layer S1, Ge, SiC, SilmGemCnSnp or II1-V compound.
  3. 3.根据权利要求1或2所述的超薄绝缘体上半导体材料的制备方法,其特征在于:所述半导体层的厚度为5nm〜20nm。 The method of preparing a semiconductor material with a thin insulator of claim 1 or claim 2, wherein: a thickness of the semiconductor layer is 5nm~20nm.
  4. 4.根据权利要求1所述的超薄绝缘体上半导体材料及的制备方法,其特征在于:所述步骤2)中采用H、He、或B离子中的至少一种进行离子注入。 The thin according to claim 1 and a method for preparing a semiconductor-on-insulator material, characterized in that: said step 2) using H, at least one of ion implantation He, or B ions.
  5. 5.根据权利要求1所述的超薄绝缘体上半导体材料的制备方法,其特征在于:所述步骤3)在键合前还包括对所述半导体层与所述绝缘层进行清洗与活化处理的步骤。 The preparation method of a semiconductor material on said thin insulator as claimed in claim 1, wherein: said step 3) further comprises prior to bonding of the semiconductor layer and the insulating layer was washed with activation of the step.
  6. 6.根据权利要求1所述的超薄绝缘体上半导体材料的制备方法,其特征在于:所述步骤4)在第二退火阶段后,还包括对所述第一衬底进行衬底修复处理使其可以循环使用的步骤。 The method of preparing a semiconductor material on said thin insulator as claimed in claim 1, wherein: said step 4) after the second annealing stage, the first substrate further comprises a substrate for a repair process so the steps may be recycled.
  7. 7.根据权利要求1所述的超薄绝缘体上半导体材料的制备方法,其特征在于:所述步骤4)中采用选择性腐蚀方法去除所述SihGez层或掺杂B、As、或Sb元素的Si1=Gez层。 The method of preparing a semiconductor material on said thin insulator as claimed in claim 1, wherein: said step 4) removing the selective etching layer or a doped SihGez B, As, or Sb element Si1 = Gez layer.
  8. 8.—种超薄绝缘体上半导体材料,包括具有绝缘层的衬底,其特征在于:所述绝缘层表面键合有半导体层,其中,所述半导体层的厚度为5n〜20nm。 8.- kinds of thin semiconductor on insulator material, comprising a substrate having an insulating layer, wherein: said insulating layer is bonded to a surface of the semiconductor layer, wherein a thickness of the semiconductor layer is 5n~20nm.
  9. 9.根据权利要求8所述的超薄绝缘体上半导体材料,其特征在于:所述半导体层的材料为S1、Ge、SiC, SilmGemCnSnp 或II1-V 族化合物。 9. The on-insulator thin semiconductor material according to claim 8, wherein: the material of the semiconductor layer S1, Ge, SiC, SilmGemCnSnp or II1-V compound.
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