CN103152302B - Calculate the circuit of am signals received signal to noise ratio - Google Patents
Calculate the circuit of am signals received signal to noise ratio Download PDFInfo
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- CN103152302B CN103152302B CN201110401200.4A CN201110401200A CN103152302B CN 103152302 B CN103152302 B CN 103152302B CN 201110401200 A CN201110401200 A CN 201110401200A CN 103152302 B CN103152302 B CN 103152302B
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Abstract
The invention discloses a kind of circuit calculating am signals received signal to noise ratio, including: enumerator, count by the sampling period of the frequency signal of am signals；First accumulator, its input signal is frequency signal；Subtraction block, an input input frequency signal, another input connects the first accumulator；Take absolute value module, and its input connects subtraction block；Second accumulator, its input connects the module that takes absolute value；First dividing module, an input connects the first accumulator, and another input connects the second accumulator；Look-up table means, its input connects the first dividing module；Adder, an input connects the first dividing module, another input connection and locating table module；Second dividing module, an input connects adder, another input input constant；Depositor, its input connects the second dividing module, and output receives the signal to noise ratio of signal.The present invention, without knowing transmission information, just can calculate am signals signal to noise ratio.
Description
Technical field
The present invention relates to digital signal transmission field, particularly relate to a kind of am signals received signal to noise ratio of calculating
Circuit.
Background technology
Amplitude modulation(PAM) is conventional signal modulation system, and the calculating of signal to noise ratio is various product, and such as AM (amplitude modulation) receives
Sound machine, non-all products with AM receive capabilities such as card that connect generally need the function of realization.
The method calculating am signals signal to noise ratio at present includes: the most fixing by the known information of a part in data
Synchronizing frame head, or the data packet head of known certain format, calculate and receive the signal to noise ratio of am signals in signal.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of circuit calculating am signals received signal to noise ratio, it is not necessary to
Know transmission information, just can calculate am signals signal to noise ratio in reception signal.
For solving above-mentioned technical problem, the circuit calculating am signals received signal to noise ratio of the present invention, including:
One enumerator, counted according to the sampling period of the frequency signal sig_freq of am signals, and frequency is believed
The input pulse signal that sampled signal sig_freq_samp is this enumerator of number sig_freq, its cycle is equal to the sampling period,
The counting cycle is 2N+1, wherein N is positive integer；Described enumerator has three output signals, respectively output signals state0, defeated
Go out signal state1, output signal state2；When the count value of described enumerator is less than 2NTime, output signal state0 is 1, defeated
Go out signal state1 and output signal state2 is 0；When the count value of described enumerator is more than 2NLess than 2N+1Time, output signal
State1 is 1, and output signal state0 and output signal state2 are 0；When the count value of described enumerator is equal to 2N+1Time, defeated
Going out signal state2 is 1, and output signal state0 and output signal state1 are 0；When the count value of described enumerator 1 0～
2NTime between-1, represent that described circuit is calculating meansigma methods；When the count value of described enumerator 1 is 2N～2N+1Time between-1, table
Show that described circuit is calculating mean square deviation；
One first accumulator, adding up for signed number, its input signal is the frequency signal of am signals
Sig_freq, output signal is sum_freq；This first accumulator is controlled by output signal state0 of described enumerator, state2
System, when output signal state0=1 of enumerator, adds up to its input signal, obtains input frequency signal sig_
The sum of freq；When output signal state0=0 of enumerator, keep accumulation result；Output signal state2 when enumerator
When=1, to the first accumulator 2 clear 0；
One subtraction block, the frequency signal sig_freq of one input input range modulated signal, as minuend；
Another input is connected with described first accumulator, inputs output signal sum_freq of the first accumulator, as subtrahend；
Its output signal is err_freq；
One takes absolute value module, and its input is connected with the outfan of described subtraction block, and its output signal is err_
Freq_abs, for calculating the absolute value used by mean square deviation；
One second accumulator, its input is connected with the outfan of the described module that takes absolute value, and its output signal is
sum_err_freq_abs；This second accumulator is controlled by described counter output signal state1, output signal state2；When
During counter output signal state1=1, input signal is added up；As counter output signal state1=0, keep cumulative
Result；As counter output signal state2=1, clear to the second accumulator 0；
One first dividing module, one input is connected with the outfan of described first accumulator, and input first is tired out
Add output signal sum_freq of device, as dividend；Another input is connected with the outfan of described second accumulator,
Inputting output signal sum_err_freq_abs of the second accumulator, as divisor, its output signal is snr_est；For believing
Make an uproar than division arithmetic, obtain signal to noise ratio snr_est through simulation calculation；
One look-up table means, its input is connected with described dividing module, inputs the output signal of the first dividing module
Snr_est, its output signal is est_err；This look-up table means is used for recording and exporting, and add on channel during emulation is known
Signal to noise ratio and the difference between signal to noise ratio snr_est that simulation calculation obtains；
One adder, one input is connected with the outfan of described dividing module, another input and lookup
The outfan of table module is connected；Its output signal is snr_cal；Signal to noise ratio snr_ obtained through simulation calculation for compensation
Est and the difference of actual result；
One second dividing module, one input is connected with the outfan of described adder, as dividend；Another
Individual input one constant of input, as divisor；For frequency signal as signal energy in signal to noise ratio is done at normalization
Reason；
One depositor, its input is connected with the outfan of described second dividing module, this register output signal
Snr_o is the signal to noise ratio receiving signal；Described depositor is controlled by counter output signal state2；When enumerator output letter
During number state2=1, output signal snr_o becomes the output snr_t of the second dividing module；As counter output signal state2
When=0, output signal snr_o keeps constant；After ensureing that only all calculating at described circuit terminate, depositor defeated
Go out and just can change.
Owing to, in preferable am signals, frequency is constant；Therefore, the core concept of the present invention is by adjusting
The standard deviation of signal frequency processed regards the noise energy of reception as, the meansigma methods of frequency is regarded as the signal energy of reception, comes straight
Connect the received signal to noise ratio of am signals in signal calculated bandwidth.Wherein the computational short cut of standard deviation is for taking after calculating difference
Adding up of absolute value.The signal to noise ratio so calculated is closed with the signal to noise ratio emulating out with white noise channel exists a forward
System.If needing signal to noise ratio accurately, the signal to noise ratio calculated above can be obtained plus an error amount.Here
Error amount refers to that the real signal to noise ratio (known signal to noise ratio) being added in during contrast simulation on channel, and by the present invention's through emulation
Error between the signal to noise ratio of circuit counting.Therefore, the present invention, without knowing transmission information, just can calculate width in reception signal
Degree modulated signal signal to noise ratio, and the SNR (signal to noise ratio) of current AM receptor calculates and is required for knowing the specifying information of transmission
Can do.But some applies such as AM radio, receptor is cannot to be known a priori by the information that AM sending station sends, so
SNR value just cannot be calculated by traditional method.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Accompanying drawing is the schematic block circuit diagram calculating am signals received signal to noise ratio.
Detailed description of the invention
Accompanying drawing is the circuit one embodiment theory diagram of described calculating am signals received signal to noise ratio, including:
One enumerator 1, counted according to the sampling period of the frequency signal sig_freq of am signals.Frequency is believed
The input pulse signal that sampled signal sig_freq_samp is this enumerator of number sig_freq, its cycle is equal to the sampling period.
The counting cycle is 2N+1, wherein N is positive integer.Described enumerator 1 has three output signals, respectively output signals state0, defeated
Go out signal state1, output signal state2.
When the count value of described enumerator 1 is less than 2NTime, output signal state0 is 1, output signal state1 and output
Signal state2 is 0.When the count value of described enumerator 1 is more than 2NLess than 2N+1Time, output signal state1 is 1, output signal
State0 and output signal state2 are 0.When the count value of described enumerator 1 is equal to 2N+1Time, output signal state2 is 1, defeated
Go out signal state0 and output signal state1 is 0.So when the count value of described enumerator 1 is 0～2NTime between-1, represent
Described circuit is calculating meansigma methods；When the count value of described enumerator 1 is 2N～2N+1Time between-1, represent that described circuit is at meter
Calculate mean square deviation.
One first accumulator 2, adding up for signed number, its input signal is the frequency signal of am signals
sig_freq.Output signal is sum_freq.First accumulator 2 is controlled by output signal state0 of enumerator 1, state2,
When output signal state0=1 of enumerator 1, its input signal is added up, obtain input frequency signal sig_freq
Sum；When output signal state0=0 of enumerator 1, keep accumulation result；Output signal state2=1 when enumerator 1
Time, to the first accumulator 2 clear 0.
One first dextroposition module 3, its input is connected with the outfan of described first accumulator 2, and input first is tired out
Add output signal sum_freq of device 2, output signal sum_freq of the first accumulator 2 is carried out dextroposition；Its output signal
For aver_freq.The shift amount of the first dextroposition module 3 is foregoing N.First accumulator 2 and the first dextroposition mould
Block 3 completes the mean value calculation to input frequency signal sig_freq jointly.
One subtraction block 4, the frequency signal sig_freq (minuend) of one input input range modulated signal；Separately
One input is connected with the outfan of described first dextroposition module 3, inputs the output signal of the first dextroposition module 3
Aver_freq (subtrahend)；Its output signal is err_freq, obtains input frequency signal sig_freq and the first dextroposition module
The difference of the meansigma methods of 3 output signals aver_freq.The purpose of do so is for the needs of subsequent calculations mean square deviation, at this
The absolute value of bright middle mean square deviation difference is cumulative does average replacement again.
One takes absolute value module 5, and its input is connected with the outfan of described subtraction block 4, input subtraction block 4
Output signal e rr_freq；Its output signal is err_freq_abs；For calculating the absolute value used by mean square deviation.
One second accumulator 6, its input is connected with the described outfan taking absolute value module 5, and input takes absolute value
Output signal e rr_freq_abs of module 5；Its output signal is sum_err_freq_abs.This second accumulator 6 is by described
Enumerator 1 output signal state1, output signal state2 control；When enumerator 1 output signal state1=1, to input
Signal adds up；When enumerator 1 output signal state1=0, keep accumulation result；When enumerator 1 output signal
During state2=1, to the second accumulator 6 clear 0.
One second dextroposition module 7, its input is connected with the outfan of described second accumulator 6, and input second is tired out
Add output signal sum_err_freq_abs of device 6, output signal sum_err_amp_abs of the second accumulator 6 is carried out the right side
Displacement；Its output signal is aver_err_freq_abs, i.e. obtains the meansigma methods of the sum of the absolute value of the second accumulator 6 output.
The shift amount of the second dextroposition module is N.Described second accumulator 6 and the second dextroposition module 7 complete to take absolute value jointly
The mean value calculation of the absolute value err_amp_abs of module 5 output, this meansigma methods is required when being to calculate mean square deviation.
One first dividing module 8, one input is connected with the outfan of described first dextroposition module 3, input
Output signal aver_freq (dividend) of the first dextroposition module 3, another input and described second dextroposition module 7
Outfan be connected, input output signal aver_err_freq_abs of the second dextroposition module 7, as divisor；Its output
Signal is snr_est.For realizing the division arithmetic of SNR, obtain signal to noise ratio snr_est through simulation calculation.
One look-up table means 9, its input is connected with the outfan of described first dividing module 8, inputs the first division
Output signal snr_est of module 8, its output signal is est_err.Described look-up table means 9 records, channel during emulation
On the known signal to noise ratio snr that adds and the difference between signal to noise ratio snr_est that simulation calculation obtains (this difference is and looks into
Look for the output of table module 9).
One adder 10, one input is connected with the outfan of described first dividing module 8, inputs the first division
Output signal e st_err of module 8, another input is connected with the outfan of described look-up table means 9, inputs look-up table
Output signal snr_est of module 9；Its output signal is snr_cal.First dividing module 8 is exported through simulation calculation
Signal to noise ratio snr_est obtained, adds the known signal to noise ratio that look-up table means 9 records and the signal to noise ratio obtained through simulation calculation
Difference between snr_est, its objective is for compensating signal to noise ratio snr_est and actual result obtained through simulation calculation
Difference.
One second dividing module 11, one input is connected with the outfan of described adder 10, as dividend,
Another input one constant of input, as divisor.The value of this constant is the carrier frequency of described am signals.Second
The effect of dividing module 11 is, frequency signal as signal energy in SNR is done normalized, not so the letter of same SNR
Number result of calculation can be made different due to carrier frequency difference.
One depositor 12, its input is connected with the outfan of described second dividing module 11, inputs the second division mould
Output signal snr_t of block 11, its output signal is snr_o.This depositor is controlled by described enumerator 1 output signal state2
System；As counter output signal state2=1, output signal snr_o becomes the output snr_t of the second dividing module；Work as meter
During number device output signal state2=0, output signal snr_o keeps constant.This register output signal finally obtained
Snr_o is exactly the signal to noise ratio receiving signal.After the effect of this depositor is to ensure that only all calculating at circuit terminate, deposit
The output SNR of device 12 just can change.
In the above-described embodiments, the input of described first dividing module 8 can be the output signal of the first dextroposition module 3
Aver_freq and output signal aver_err_freq_abs of the second dextroposition module 7；Can also be the defeated of the first accumulator 2
Go out output signal sum_err_freq_abs (divisor) of signal sum_freq (dividend) and the second accumulator 6.Tire out with first
When adding output signal sum_freq of device 2 and output signal sum_err_freq_abs of the second accumulator 6 as input, first
Dextroposition module 3 and the second dextroposition module 7 avoid the need for.When two dextroposition modules all do not have, it is simply that two are added up
Value is divided by, because the number of two accumulated values is all 2N, the most first move to right N position be divided by again so being equivalent to two accumulated values.Logical
It is divided by again the figure place of the input that can reduce divider after first moving to right N position.
Above by detailed description of the invention and embodiment, the present invention has been described in detail, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and changes
Entering, these also should be regarded as protection scope of the present invention.
Claims (3)
1. the circuit calculating am signals received signal to noise ratio, it is characterised in that including:
One enumerator, counts according to the sampling period of the frequency signal sig_freq of am signals, frequency signal
Sampled signal sig_freq_samp of sig_freq is the input pulse signal of this enumerator, and its cycle is equal to sampling period, meter
One number time is 2N+1, wherein N is positive integer；Described enumerator has three output signals, respectively output signals state0, output
Signal state1, output signal state2；When the count value of described enumerator is less than 2NTime, output signal state0 is 1, output
Signal state1 and output signal state2 are 0；When the count value of described enumerator is more than 2NLess than 2N+1Time, output signal
State1 is 1, and output signal state0 and output signal state2 are 0；When the count value of described enumerator is equal to 2N+1Time, defeated
Going out signal state2 is 1, and output signal state0 and output signal state1 are 0；When the count value of described enumerator 1 0～
2NTime between-1, represent that described circuit is calculating meansigma methods；When the count value of described enumerator 1 is 2N～2N+1Time between-1, table
Show that described circuit is calculating mean square deviation；
One first accumulator, adding up for signed number, its input signal is the frequency signal sig_ of am signals
Freq, output signal is sum_freq；This first accumulator is controlled by output signal state0 of described enumerator, state2,
When output signal state0=1 of enumerator, its input signal is added up, obtain input frequency signal sig_freq's
With；When output signal state0=0 of enumerator, keep accumulation result；When output signal state2=1 of enumerator,
To the first accumulator 2 clear 0；
One subtraction block, the frequency signal sig_freq of one input input range modulated signal, as minuend；Another
Individual input is connected with described first accumulator, inputs output signal sum_freq of the first accumulator, as subtrahend；It is defeated
Going out signal is err_freq；
One takes absolute value module, and its input is connected with the outfan of described subtraction block, and its output signal is err_freq_
Abs, for calculating the absolute value used by mean square deviation；
One second accumulator, its input is connected with the outfan of the described module that takes absolute value, and its output signal is sum_
err_freq_abs；This second accumulator is controlled by described counter output signal state1, output signal state2；Work as counting
During device output signal state1=1, input signal is added up；As counter output signal state1=0, keep cumulative knot
Really；As counter output signal state2=1, clear to the second accumulator 0；
One first dividing module, one input is connected with the outfan of described first accumulator, inputs the first accumulator
Output signal sum_freq, as dividend, another input is connected with the outfan of described second accumulator, input
Output signal sum_err_freq_abs of the second accumulator, as divisor, its output signal is snr_est；For signal to noise ratio
Division arithmetic, obtain signal to noise ratio snr_est through simulation calculation；
One look-up table means, its input is connected with the outfan of described dividing module, inputs the output of the first dividing module
Signal snr_est, its output signal is est_err；This look-up table means is used for recording and exporting, and adds during emulation on channel
Known signal to noise ratio and the difference between signal to noise ratio snr_est that simulation calculation obtains；
One adder, one input is connected with the outfan of described dividing module, another input and look-up table mould
The outfan of block is connected；Its output signal is snr_cal；Signal to noise ratio snr_est obtained through simulation calculation for compensation
Difference with actual result；
One second dividing module, one input is connected with the outfan of described adder, and as dividend, another is defeated
Enter end one constant of input, as divisor；For frequency signal as signal energy computation in signal to noise ratio is done at normalization
Reason；
One depositor, its input is connected with the outfan of described second dividing module, and this register output signal snr_o is i.e.
For receiving the signal to noise ratio of signal；Described depositor is controlled by counter output signal state2；Work as counter output signal
During state2=1, output signal snr_o becomes the output snr_t of the second dividing module；As counter output signal state2=
When 0, output signal snr_o keeps constant；After ensureing that only all calculating at described circuit terminate, the output of depositor
Just can change.
2. circuit as claimed in claim 1, it is characterised in that: also include one first dextroposition module and one second dextroposition mould
Block；
Described first dextroposition module, its input is connected with the outfan of described first accumulator, inputs the first accumulator
Output signal sum_freq, output signal sum_freq of the first accumulator is carried out dextroposition, its output signal is aver_
freq；The shift amount of the first dextroposition module is N；The outfan of the first dextroposition module respectively with described first dividing module
An input be connected with the input of subtraction block, its output signal is respectively as dividend and subtrahend；This first moves to right
Position module and described first accumulator complete the mean value calculation to input frequency signal sig_freq jointly；
Described second dextroposition module, its input is connected with the outfan of described second accumulator, the second dextroposition module
Shift amount be N；The outfan of the second dextroposition module is connected with another input of described first dividing module, and it is defeated
Go out signal as divisor；This second dextroposition module and described second accumulator complete the absolute of module output that take absolute value jointly
The mean value calculation of value err_amp_abs.
3. circuit as claimed in claim 1, it is characterised in that: the value of described constant is the carrier frequency of am signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110401200.4A CN103152302B (en) | 2011-12-06 | Calculate the circuit of am signals received signal to noise ratio |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110401200.4A CN103152302B (en) | 2011-12-06 | Calculate the circuit of am signals received signal to noise ratio |
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| Publication Number | Publication Date |
|---|---|
| CN103152302A CN103152302A (en) | 2013-06-12 |
| CN103152302B true CN103152302B (en) | 2016-12-14 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1358365A (en) * | 1999-06-24 | 2002-07-10 | 艾比奎蒂数字公司 | Method for estimating signal-to-noise ratio of digital carriers in AM compatible digital audio broadcasting system |
| CN101640572A (en) * | 2008-07-18 | 2010-02-03 | 俊茂微电子（上海）有限公司 | Method and apparatus for signal/noise ratio measurement and communication equipment |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1358365A (en) * | 1999-06-24 | 2002-07-10 | 艾比奎蒂数字公司 | Method for estimating signal-to-noise ratio of digital carriers in AM compatible digital audio broadcasting system |
| CN101640572A (en) * | 2008-07-18 | 2010-02-03 | 俊茂微电子（上海）有限公司 | Method and apparatus for signal/noise ratio measurement and communication equipment |
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