CN103152154A - Full duplex single-ended serial link communication system - Google Patents

Full duplex single-ended serial link communication system Download PDF

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Publication number
CN103152154A
CN103152154A CN2012105171981A CN201210517198A CN103152154A CN 103152154 A CN103152154 A CN 103152154A CN 2012105171981 A CN2012105171981 A CN 2012105171981A CN 201210517198 A CN201210517198 A CN 201210517198A CN 103152154 A CN103152154 A CN 103152154A
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data
signal
forward channel
speed serial
chn
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CN2012105171981A
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CN103152154B (en
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C·伊尔马泽尔
M·E·厄内尔
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/143—Two-way operation using the same type of signal, i.e. duplex for modulated signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The application describes a system utilizing single-ended communications links for full duplex communication. The system comprises a first link interface which is configured to generate a signal for transmission through the single-ended communications links. The signal includes data encoded in a forward channel. The system also comprises a seocnd link interface which is configured to receive the signal from the first link interface via the single-ended communications links and modulate the signal to encode data in a reverse channel, so that the signal includes the forward channel data and the reverse channel data simultaneously.

Description

Full duplex single ended serial link communication system
The cross reference of related application
The application is according to 35U.S.C. § 120, application serial 12/545,744 U.S. Patent application, be entitled as the cip application of " SYSTEM AND METHOD FOR TRANSFERRING DATA OVERFULL-DUPLEX DIFFERENTIAL SERIAL LINK ", it is in this combination comprehensively by reference.
Background technology
In many application, high-speed data simultaneously is sent to receiver from the source basically together with the transmission of low speed data.For example, in Video Applications, video data (for example, relative data at a high speed) is sent to video receiver (for example, display) from video source (for example, camera).Control data (for example, low speed data) relatively can be simultaneously two-way transmission between video source and video receiver together with the transmission of this video data.For example, how the control data from the video source to the video receiver can the instruction video data show.And for example the control data from the video receiver to the video source can be indicated the state of visual angle, exposure, focusing or the video equipment of camera.High speed and low speed data are usually via the entity cable transmission.
Summary of the invention
A kind of system that uses single-ended communication link to carry out full-duplex communication has been described.This system comprises the first LI(link interface), and it is configured to generate the signal that transmits via this single-ended communication link.This signal is included in coded data on forward channel.This system also comprises the second LI(link interface), it is configured to receive this signal via this single-ended communication link from this first LI(link interface), and modulate this signal with coded data on backward channel, make this signal comprise simultaneously this forward channel data and this backchannel data.
It is in order to introduce in simplified form the selection to concept that this summary is provided, and it is further described in the following detailed description.This summary is not intended to be equal to key feature or the essential characteristic of claimed theme, does not also attempt the supplementary means as the scope of determining claimed theme.
Description of drawings
This detailed description is described with reference to this accompanying drawing.Utilize identical Ref. No. can indicate similar or identical object in the different example of specification and accompanying drawing.
Figure 1A is a kind of block diagram according to an example embodiment of the present disclosure, illustrates a kind of system for transmitting data.
Figure 1B is a kind of signal diagrams according to another example embodiment of the present disclosure, illustrates a kind of forward channel data frame.
Fig. 1 C is time-domain diagram according to example embodiment of the present disclosure to 1E, illustrates the signal of encoding on forward direction and backward channel.
Fig. 2 A is a kind of block diagram according to another example embodiment of the present disclosure, illustrates a kind of system for transmitting data, and wherein this system comprises video/audio source, video/audio controller, display, audio process and demonstration-Audio Controller.
Fig. 2 B is a kind of signal diagrams according to another example embodiment of the present disclosure, illustrates another kind of forward channel data frame.
Fig. 3 is a kind of block diagram, illustrate the part for the system that transmits data that Fig. 1 shows, wherein this part of this system comprises that forward channel driver, backward channel driver, high-frequency suppressing circuit and low frequency suppress circuit, and wherein these data are transmitted on full duplex single ended serial data link.
Fig. 4 is the another kind of block diagram according to another example embodiment of the present disclosure, illustrates a kind of system for transmitting data, and wherein this system further comprises transceiver.
Fig. 5 is a kind of block diagram according to another example embodiment of the present disclosure, illustrates a kind of system for transmitting data, and wherein this system comprises a plurality of forward channel receivers.
Fig. 6 A is a kind of block diagram according to an example embodiment of the present disclosure, illustrates a kind of forward channel high-speed data transmission device and a kind of backward channel low speed data receiver.
Fig. 6 B is a kind of block diagram according to another example embodiment of the present disclosure, illustrates a kind of forward channel high-speed data transmission device and a plurality of backward channel low speed data receiver.
Fig. 7 is a kind of block diagram according to an example embodiment of the present disclosure, illustrates a kind of forward channel high-speed data receiver and a kind of backward channel low speed data reflector.
Fig. 8 is a kind of block diagram according to another example embodiment of the present disclosure, illustrate the another kind of system that is used for transmitting data, wherein this system comprises high-speed data source, forward channel low speed data source, backward channel low speed data receiver, high-speed data receiver, forward channel low speed data receiver and backward channel low speed data source.
Embodiment
Summary
High-speed data can be at least basically be sent to receiver from the source simultaneously together with the transmission of low speed data.In one or more embodiments, automobile and aircraft system can utilize Video Applications and voice applications so that supplementary features (for example, the safety device that replenishes, additional amusement equipment etc.) to be provided to this system.For example, automobile can comprise central information display, instrument display, back seat amusement unit etc.Yet, due to general strict space and weight requirement on automobile and aircraft, may wish to reduce physical space and the weight of the cable that is used to transmit data.
Therefore, a kind of system that uses single-ended communication link to carry out full-duplex communication has been described.This system comprises the first LI(link interface), and it is configured to generate the signal that transmits via this single-ended communication link.This signal is included in coded data on forward channel.This system also comprises the second LI(link interface), it is configured to receive this signal via this single-ended communication link from this first LI(link interface), and modulate this signal with coded data on backward channel, make this signal comprise simultaneously this forward channel data and this backchannel data.This signal can be through single-ended communication link transmission.This single-ended communication link can be coupling between the first LI(link interface) and the second LI(link interface).In one or more embodiments, this single-ended communication link may comprise single coaxial cable, single printed circuit board trace etc.
In another embodiment, this system can comprise that the inhibition circuit is to suppress the part of these data, to export the relevant data part of this signal.For example, this system can comprise that forward channel suppresses circuit, and it is configured to suppress the forward data part of this signal to export the reverse data part of this signal.In another example, this system can comprise that backward channel suppresses circuit, and it is configured to suppress the backchannel data part of this signal, to export the forward data part of this signal.
In being discussed below, an example system of using single-ended communication link to carry out full-duplex communication has been described.
Example embodiment
Figure 1A illustrates a kind of block diagram of the example system 100 for transmitting data according to an exemplary embodiment of the present invention.In a word, system 100 uses the data transmission technology that full duplex single ended serial data link is provided.Especially, this data transmission technology need to the transmission of low speed data on backward channel (for example, control data) together, (for example send high-speed data in forward channel simultaneously, video data) and low speed data (for example, audio frequency and/or control data).In addition, the full duplex transmission of these data can occur on cheap physical medium, for example single coaxial cable, printed circuit board (PCB) (PCB) trace etc.
More precisely, system 100 comprises high-speed data source 110, forward channel (FWD CHN) low speed data source 112 and backward channel (REV CHN) low speed data receiver 114, and all these is positioned on an end of full duplex single ended serial data link 130.In one or more embodiments, full duplex single ended serial data link 130 comprises single communication link.For example this single communication link can be single coaxial cable, single PCB trace, wall scroll electric wire etc.High-speed data source 110 can generate parallel high-speed (HS) data (for example, video data).Parallel, forward direction (channel) low speed (FLS) data (for example, control and/or voice data) that FWD CHN low speed data source 112 can generate.REV CHN low speed data receiver 114 can receive parallel, reverse (channel) low speed (RLS) data (for example, controlling data).
Term " high-speed data " is meaning it and is transmitting with the speed higher than " low speed data " (for example, higher frequency).For example, high-speed data can be video data.And this low speed data can be audio frequency and/or control data.Should be appreciated that " high-speed data " is not necessarily limited to video, can comprise the data of other type.Similarly, low speed data is not necessarily limited to control and/or voice data, can comprise the data of other type.
System 100 further comprises serial link interface 120, it is used for high-speed data source 110, FWDCHN low speed data source 112 and REV CHN low speed data receiver 114 are connected to communication link 130, in this case, communication link 130 is configured to full duplex single ended serial data link.Serial link interface 120 comprises that high-speed serializer 122, FWD CHN low-speed serial device 124, REV CHN low speed deserializer 126 and FWD CHN suppress circuit 128.High-speed serializer 122 conversion is carried out it time-multiplexed to generate the forward channel frame, in order to transmit via full duplex single ended serial data link 130 from the parallel HS data in high-speed data source 110 together with serial FLS data.
And FWD CHN low-speed serial device 124 will become serial FLS data from the parallel FLS data transaction in FWD CHN low speed data source 112, and as discussed, serial FLS data are time-multiplexed together with high-speed serial data.Sometimes, FWD CHN low speed data source 112 can serial mode generate the FLS data.In this case, can cancel FWD CHN low-speed serial device 124, and FWD CHN low speed data source 112 can be directly coupled to high-speed serializer 122.
FWD CHN suppresses circuit 128 and (for example at least basically suppresses forward channel signal, the single-ended signaling of serial HS and FLS data), with the serial of at least basically exporting the opposite end that is received from communication link 130, reverse (channel) low speed (RLS) signal.For example, FWD CHN inhibition circuit 128 can be low pass filter (LPF) or the band pass filter (BPF) that is applicable to filtering high frequency forward channel signal.As another example, it can be the signal abatement apparatus that FWD CHN suppresses circuit 128, and it is used at least basically eliminating forward channel signal.REV CHN low speed deserializer 126 becomes parallel RLS data with serial RLS data transaction, in order to process by REV CHN low speed data receiver 114.
At the other end of communication link 130, system 100 comprises high-speed data receiver 160, FWD CHN low speed data receiver 162 and REV CHN low speed data source 164.High-speed data receiver 160 receives and processes parallel high-speed (HS) data (for example, video data) from high-speed data source 110.FWD CHN low speed data receiver 162 receives and processes from the parallel FLS data in FWD CHN low speed data source 112 (for example, control and/or voice data).That REV CHN low speed data source 164 produces is parallel, RLS data (for example, controlling data) to be to be used for being transferred to REV CHN low speed data receiver 114.
System 100 further comprises serial link interface 140, and it is used for high-speed data receiver 160, FWD CHN low speed data receiver 162 and REV CHN low speed data source 164 are connected to communication link 130.Serial link interface 140 comprises that REV CHN suppresses circuit 142, high speed deserializer 144, FWD CHN low speed deserializer 146, REV CHN low-speed serial device 150 and single-ended signal modulator 148.
REV CHN suppresses circuit 142 and suppresses reverse channel signals (for example, single-ended modulated serial RLS data) at least basically to export the forward channel signal (for example HS and FLS data) of the opposite end that is received from communication link 130.For example, REV CHN inhibition circuit 142 can be high pass filter (HPF) or the BPF that is applicable to filtering low frequency back channel signal.As another example, it can be the signal abatement apparatus that REV CHN suppresses circuit 142, and it is used at least basically eliminating reverse channel signals.
High speed deserializer 144 is converted into the forward channel parallel data with the forward channel serial data.The HS data division of forward channel parallel data is sent to high-speed data receiver 160 and processes.The FLS data division of forward channel parallel data is sent to FWD CHN low speed deserializer 146, and it becomes the FLS data transaction parallel.Parallel FLS data are sent to FWD CHN low speed data receiver 162 and process.Sometimes, FWDCHN low speed data receiver 162 can have serial data input and receive this FLS data, and the FLS data division of HS data is only individual bit.In this case, can cancel FWD CHN low speed deserializer 146, and the corresponding bit of high speed deserializer 144 can be directly connected to FWD CHN data sink 162.
REV CHN low-speed serial device 150 will become serial RLS data from the parallel RLS data transaction in REV CHN low speed data source 164.Sometimes, REV CHN low speed data source 164 is with serial mode output RLS data.In this case, can cancel REV CHN low-speed serial device 150, and REV CHN low speed data source 164 can be directly coupled to single-ended signal modulator 148.Single-ended signal modulator 148 use RLS Data Modulation forward channel signals.Single-ended signal modulator 148 can comprise conversion rate control, to modulate the spectral content that forward channel signal is controlled backward channel with relatively slow mode, makes at least basically from the spectral content of forward direction channel its isolation.
Figure 1B illustrates the signal diagrams of the forward channel data frame of example according to disclosed another embodiment.In this example, the forward channel frame comprises whole HS data word.For example, HS data bit HS 0 to HSN is included into this forward channel frame, and wherein N+1 is the length of this HS data word.In addition, the forward channel frame comprises the part of FLS data word.For example, the individual bit of this forward channel frame keeps to these FLS data.Should be appreciated that, can be used to these FLS data and/or other data more than a bit in forward channel.
Fig. 1 C according to another embodiment of the present disclosure, illustrates the time-domain diagram of the example signal of forward direction and backward channel to 1E.Fig. 1 C illustrates the forward channel single-ended signal of (for example, the 101010) pattern that has repeating signal.Fig. 1 D illustrates the forward channel single-ended signal after modulation.Fig. 1 E illustrates the multiple backchannel data of ash after suppressing high fdrequency component.
About Fig. 1 C, the forward channel single-ended signal comprises voltage signal V PVoltage signal V PAt upper voltage V UWith lower voltage V LBetween the change.As diagram, voltage signal V PInitially (for example, period 1) is at lower voltage V LThen the place is varying to voltage V during second round UYet very clear, voltage signal V PInitially can press from power on V UBeginning.And Fig. 1 C illustrates a kind of pattern of repetition, knows that very the forward channel single-ended signal can be based on random data, and therefore, the forward direction single-ended signal can be comprised of the signal that represents random data.
About Fig. 1 D, the forward channel single-ended signal is reversed the channel signal modulation.Modulated single-ended signal comprises modulated voltage signal V P'.The forward channel single-ended signal can be at upper voltage V UOn or lower voltage V LUnder modulate.For example, in the period 1, modulated signal V P' can comprise V UThe upper voltage of+Δ M (for example, the peak change of amplitude).At another cycle of reverse channel signals, modulated signal V P' can be at V LOn the lower voltage of-Δ M (for example the trough of amplitude changes).Yet, as shown in Fig. 1 D, modulation signal V P' can be modulated onto V UAnd V UValue between+Δ M and V LAnd V LValue between-Δ M.
Fig. 1 E illustrates modulated voltage V P' suppressed circuit 128 by FWD CHN to process the signal that is produced (for example, the reverse channel signals of recovery) afterwards.Thereby FWD CHN suppresses circuit 128 and partly extracts reverse channel signals by the modulated of partly processing the forward channel single-ended signal, to export this reverse channel signals.
Fig. 2 A illustrates the block diagram for another example system 200 of transmitting data according to another embodiment of the present disclosure.System 200 is example application of previously described system 100.Especially, system 200 is configured at the forward channel transferring multimedia data, for example Audio and Video data, and control data, and control data in the backward channel transmission.This can be following situation, video/audio (V/A) source wherein, and for example camera or DVD player, send video, audio frequency and control data to display in forward channel.Forward channel control data can indicate this video how to show and how this audio frequency reproduces.Demonstration and voicefrequency circuit can comprise the controller that is associated, and it is used for sending the control data and gets back to the V/A source on backward channel.Backward channel is controlled data and can be indicated this V/A source how to produce this Audio and Video data.
More precisely, system 200 comprises video/audio (V/A) source 210 and V/A controller 212, and both are positioned at an end of full duplex single ended serial data link 230.V/A source 210 produces parallel video data and parallel audio data under the control of V/A controller 212.For example, voice data can be suitable I 2The S form.V/A controller 212 can generate parallel forward channel and control (FCC) data.Parallel, backward channel control (RCC) data that V/A controller 212 can also receive.As previous discussion, the FCC data can be used for controlling one or more aspects that video shows and/or audio frequency is play.The RCC data can be used for controlling one or more aspects of catching and producing of these Audio and Video data.The data transfer rate of this video data is generally higher than the data transfer rate of audio frequency and FCC data.
System 200 further comprises serial link interface 220, and it is used for V/A source 210 and V/A controller 212 are connected to full duplex single ended serial data link 230.Serial link interface 220 comprises that voice data serializer 222, high-speed serializer 224, FWD CHN control data serializer 226, REV CHN controls data deserializer 228 and FWD CHN suppresses circuit 229.
Voice data serializer 222 will become the serial voice data from the parallel audio data transaction in V/A source 210.Similarly, FWD CHN controls data serializer will become serial FCC data from the parallel FCC data transaction of V/A controller 212.High-speed serializer 224 conversion is from the parallel video data in V/A source 210, and it is time-multiplexed generating the forward channel frame together with serial voice data and serial FCC data, transmits via full duplex single ended serial data link 230 being used for.Sometimes, V/A controller 212 can generate the FCC data with serial mode, rather than parallel mode.In this case, can cancel FWD CHN and control data serializer 226, and V/A controller 212 can be directly coupled to high-speed serializer 224.
FWD CHN suppresses circuit 229 and suppresses forward channel signal, with the serial of at least basically exporting the opposite end that is received from full duplex single ended serial data link 230, reverse (RCC) data of controlling.For example, FWD CHN inhibition circuit 229 can be LPF or the BPF that is applicable to the filtering forward channel signal.As another example, it can be the signal abatement apparatus that FWDCHN suppresses circuit 229, and it is applicable at least basically eliminate forward channel signal.REV CHN controls data deserializer 228 becomes parallel RCC data to process for V/A controller 212 with serial RCC data transaction.Sometimes, V/A controller 212 can be configured to receive the RCC data with serial mode, rather than parallel mode.In this case, can cancel REV CHN and control data deserializer 228, and V/A controller 212 can be directly coupled to FWD CHN inhibition circuit 229.
At the other end of full duplex single ended serial data link 230, system 200 comprises audio process 260, transducer 262 (for example loudspeaker), display 264 (for example, liquid crystal display (LCD)) and demonstration-Audio Controller 266.Audio process 260 is processed the parallel audio data that receive and is used for driving loudspeaker 262 to generate simulated audio signal under the control of demonstration-Audio Controller 266.Display 264 is under the control of demonstration-Audio Controller 266, and the parallel video data that processing receives are to show correspondence image.Demonstration-Audio Controller 266 can be controlled audio process 260 and display 264 based on the FCC data that receive.In addition, demonstration-Audio Controller 266 can generate the RCC data and is used for being transferred to V/A controller 212 to control one or more operations in this V/A source 210.
System 200 further comprises serial link interface 240, and it is connected to full duplex single ended serial data link 230 with audio process 260, display 264 and demonstration-Audio Controller 266.Serial link interface 240 comprises that voice data deserializer 242, REV CHN suppress circuit 246, high speed deserializer 244, FWD CHN control data deserializer 247, single-ended (SE) signal modulator 248 and REV CHN and control data serializer 250.
REV CHN suppresses circuit 246 and suppresses reverse channel signals (for example RCC data) at least basically to export forward channel signal (for example video, audio frequency and FCC data).In one embodiment, REV CHN inhibition circuit 246 can be HPF or the BPF that is applicable to the filtering reverse channel signals.In another embodiment, it can be the signal abatement apparatus that REV CHN suppresses circuit 246, and it is used at least basically eliminating reverse channel signals.
High speed deserializer 244 is converted into the forward channel parallel data with the forward channel serial data.The video data of forward channel parallel data partly is sent to display 264 and is used for image demonstration purpose.The voice data of forward channel parallel data partly is sent to voice data deserializer 242.Voice data deserializer 242 is converted into the parallel audio data with this serial voice data, and provides these parallel audio data to be used for the sounding purpose to audio process 260.The FCC data division of forward channel parallel data is sent to FWD CHN and controls data deserializer 247, and it becomes this FCC data transaction parallel.Parallel FCC data are sent to demonstration-Audio Controller 266 and process.Sometimes, demonstration-Audio Controller 266 can only receive via serial port and control data.In this case, can cancel FWD CHN and control data deserializer 247, and the corresponding position output of high speed deserializer 244 can be directly connected to the serial port of demonstration-Audio Controller 266.
REV CHN controls data serializer 250 will become serial RCC data from the parallel RCC data transaction of demonstration-Audio Controller 266.SE signal modulator 248 use RCC Data Modulation forward channel signals.SE signal modulator 248 can comprise conversion rate control, to modulate with relatively slow mode the spectral content that forward channel signal is controlled backward channel, consequently at least basically isolates backward channel from the spectral content of forward direction channel.Sometimes, demonstration-Audio Controller 266 can only be controlled data via serial port output.In this case, can cancel FWD CHN and control data serializer 250, and the corresponding position output of demonstration-Audio Controller 266 can be directly connected to SE signal modulator 248.
Fig. 2 B illustrates the signal diagrams of example forward channel data frame according to another embodiment of invention.In this example, the forward channel frame comprises whole video data word.For example, video data bit V0 is included into this forward channel frame to VN, and wherein N+1 is the length of this video data word.In addition, this forward channel frame comprises the part (for example, bit) of voice data word.Further, this forward channel frame comprises the part (for example, bit) of FCC data word.Should be appreciated that, surpass a bit in this forward channel frame and can be used to this voice data and be used for these FCC data.
Fig. 3 illustrates the block diagram for another example system 300 of transmitting data according to another embodiment of the present disclosure.System 300 is according to concept described herein, illustration spectral content and the processing of forward direction and reverse channel signals.System 300 comprises FWD CHN driver 302 and high-frequency suppressing circuit 308, and both are positioned at the first end of full duplex single ended serial link 310.System 300 comprises that further low frequency (LF) suppresses circuit 304 and REV CHN driver 306, and both are positioned at second and opposite end of full duplex single ended serial link 310.
As noted, FWD CHN data, the input that it is applied to FWD CHN driver 302 variantly has relatively high frequency, frequency band limits spectral content.Similarly, as noted, REV CHN data, the input that it is applied to REV CHN driver 306 variantly has relatively low frequency, frequency band limits spectral content.On full duplex single ended serial data link 310, forward channel signal is reversed channel signal to carry out modulating single-endedly.Thereby as noted, the spectral content of this modulated signal can comprise at least basically non-overlapped low frequency bands of a spectrum and high frequency bands of a spectrum.
As noted, LF suppresses circuit 304, and it can be that HPF, BPF or low frequency are eliminated circuit, removes reverse channel signals to produce or recovery FWD CHN data.Similarly, as noted, HF suppresses circuit 308, and it can be that LPF, BPF or high frequency are eliminated circuit, removes forward channel signal to produce or recovery REVCHN data.
Fig. 4 illustrates the block diagram for another example system 400 of transmitting data according to another embodiment of the present disclosure.The system 100 of previous description and 200 may have actual restriction on the length of the physical medium that is used for full duplex single ended serial data link.That is if the length of serial data link is oversize, forward direction and reverse channel signals may deteriorate into the level that can't recover.In order effectively to extend the length of communication link, can realize one or more repeaters (repeater) or transceiver with daisy chaining between communication link two ends.In addition, each element in encircling by configuration is as repeater or transceiver, and such system can be modified to form circulus.Yet in this example, system's 400 use repeaters or transceiver are with the length of effective prolongation serial data link.
Especially, system 400 comprises forward channel (FC) source 420, transceiver 440 and forward channel (FC) receiver 460.This system 400 further comprises full duplex single ended serial data link 435, and it is coupled to transceiver 440 with FC source 420, and comprises another full duplex single ended serial data link 455, and it is coupled to FC receiver 460 with this transceiver 440.
And FC source 420 comprises that FC data source 422, FC reflector (Tx) 424, FC suppress circuit 430, RC receiver (Rx) 428 and RC data sink 426.FC data source 422 produces the data that are used for forward channel, as previous discussion, and the data of its data that can comprise relative high speed and embedded relative low speed.FC Tx424 forms the single-ended signaling of FC data, transmits via full duplex single ended serial data link 435 being used for.FC suppresses circuit 430 and at least basically suppresses the FC data-signal, and to recover the RC data-signal, this RC data-signal is received from transceiver 440 or is received from FC receiver 460 via transceiver 440.RC Rx 428 recovers these RC data and provides it to RC data sink 426 to process.
And FC receiver 460 comprises that RC data source 470, RC Tx 468, RC suppress circuit 462, FC Rx464 and FC data sink 466.The data that RC data source 470 produces relative low speed are used for backward channel.RC Tx 468 these FC signals of use RC Data Modulation are to be used for via 455 transmission of full duplex single ended serial data link.RC suppresses circuit 462 and at least basically suppresses the RC data-signal recovering the FC data, and this FC data receiver is received from FC source 420 from transceiver 440 or via transceiver 440.FC Rx 464 recovers these FC data and it is provided to FC data sink 466 to process.As previous discussion, these FC data can comprise the data of relative high speed and the data of embedded relative low speed.
And transceiver 440 comprises that RC suppresses circuit 442, FC Tx/Rx 446, FC data sink/source 448, FC and suppresses circuit 452, RC Tx/Rx 450 and RC data sink/source 454.RC suppresses circuit 442 and at least basically suppresses RC data-signal from full duplex single ended serial data link 435, to recover to be received from the FC data-signal in FC source 420.FC Tx/Rx 446 can recover the FC data and it is provided to FC data sink/source 448 to be used for further processing.At another embodiment, perhaps in addition, the FC signal that FC Tx/Rx 446 can amplify and pass through and receive is to be used for being transferred to FC receiver 460 via full duplex single ended serial data link 455.As previous discussion, the data of the data that these FC data can comprise relative high speed and embedded relative low speed.
FC inhibition circuit 452 suppresses the FC data-signal from full duplex single ended serial data link 455 at least basically, to recover to be received from the RC data-signal of FC receiver 460.RC Tx/Rx 450 can recover the RC data and it is provided to RC data sink/source 454 to process.At another embodiment or in addition, the RC signal that this RC Tx/RX 450 can amplify and pass through and receive is to be used for being transferred to FC source 420 via full duplex single ended serial data link 435.
Fig. 5 illustrates the block diagram for another example system 500 of transmitting data according to another embodiment of the present disclosure.This system 100 and 200 previous descriptions only for example understand single forward channel receiver.Should be appreciated that such system can comprise a plurality of forward channel receivers.For example, such system can be configured to point-to-multi-point system.In this respect, system 500 uses a pair of FC receiver for the forward channel data that receives respectively from the FC source.Should be appreciated that system 500 can comprise that more FC receivers are used for receiving the forward channel data from the FC source.
Especially, system 500 comprises FC source 520, a FC receiver 540 and the 2nd FC receiver 560.System 500 further comprises full duplex single ended serial data link 535, and it is coupled to this first and second FC receiver 540,560 with FC source 520.As shown in Figure 5, full duplex single ended serial data link 535 can terminate in terminal equipment 572.In one embodiment, terminal equipment 572 can be terminating equipment, for example resistor or similar.
And FC source 520 comprises that FC data source 522, FC Tx524, FC suppress circuit 530, RCRx528 and RC data sink 526.FC data source 522 produces the data that are used for forward channel, as previous discussion, and the data of its data that can comprise relative high speed and embedded relative low speed.The single-ended signaling that FC Tx 524 forms the FC data is transmitted via full duplex single ended serial data link 535 being used for.FC suppresses circuit 530 and at least basically suppresses the FC data-signal, and to recover the RC data-signal, this RC data-signal is received from this first and/or the 2nd FC receiver 540 and 560.RC Rx 528 recovers these RC data and provides it to RC data sink 526 to process.
And a FC receiver 540 comprises that RC suppresses circuit 542, FC Rx 544, FC data sink 546, RC data source 548 and RC Tx 550.RC suppresses circuit 542 and at least basically suppresses the RC data-signal, and recovering the FC data-signal, this FC data-signal is received from FC source 520 via full duplex single ended serial data 535.FC Rx 544 recovers these FC data and it is provided to FC data sink 546 to process.As previous discussion, the data of the data that the FC data can comprise relative high speed and embedded relative low speed.The data that RC data source 548 produces relative low speed are used for backward channel.This FC signal of this RC Data Modulation of RC Tx 550 use is to be used for being transferred to FC source 520 via full duplex single ended serial data link 535.
And the 2nd FC receiver 560 can be similarly or be configured the same with FC receiver 540 at least basically.For example, FC receiver 560 comprises that RC suppresses circuit 562, FC Rx 564, FC data sink 566, RC data source 570 and RC Tx 566.RC suppresses circuit 562 and at least basically suppresses the RC data-signal, and recovering the FC data-signal, this FC data-signal is received from FC source 520 via full duplex single ended serial data 535.FC Rx 564 recovers these FC data and it is provided to FC data sink 566 to process.As previous discussion, the data of the data that the FC data can comprise relative high speed and embedded relative low speed.The data that RC data source 570 produces relative low speed are used for backward channel.This FC signal of this RC Data Modulation of RC Tx 566 use is to be used for being transferred to FC source 520 via full duplex single ended serial data link 535.
From the RC data of the 2nd FC receiver 560 can with time division multiplexing together with the RC data of a FC receiver 540, to be used for being transferred to FC source 520.For example, FC receiver 540 and FC receiver 560 can be configured to respectively main equipment and from equipment, be used for using serial data link 535 transmission RC data according to priority.In this respect, no matter when FC receiver 540 will send the RC data, and it can use serial data link 535, and can permit FC receiver 560 to send the RC data via this serial data link.Can use anti-collision or the time-multiplexed use serial data link of other type to be used for transmission RC data.
About Fig. 6 A to 7, very clear, the resistor that is associated and the component Name of capacitor only are used for identifying this assembly (for example, resistor, capacitor), and apportioning cost is not to the assembly that identifies.For example, depend on the requirement (for example frequency of signal etc. in data link) of system 600 and 700, can use various resistance and capacitance.Fig. 6 A illustrates the block diagram of example high-speed data transmission device and low speed data receiver 600 according to another embodiment of the present disclosure.System 600 is respectively FC source 420 and an example embodiment of 520 in system 400 and 500.Especially, system 600 comprises the forward channel reflector, and it comprises a pair of resistor R1, pair of differential transistor M1 and M2 (for example, mos field effect transistor (MOSFET)) and power supply 602.Resistor R1 is coupling between the drain electrode of positive voltage rail and MOSFET M1 and M2 respectively.Resistor R1 provide terminate load to serial link.In one embodiment, resistor can be configured to the to have 50 ohm resistance of (50 Ω).Yet, depend on that the requirement of system 600 can use the resistor of other different value.Power supply 602 is coupling between the source electrode and negative supply voltage rail of MOSFET M1 and M2, and it can be ground wire.Forward channel data is applied to the grid level of FET M1 and M2 variantly.As directed, pair of conductors is coupled to the drain electrode of FET M1 and M2.The first conductor (CML+) is connected to the single ended serial link.The topology that depends on system 600, this second conductor (CML-) can be floated or end at power supply or ground wire together with a suitable terminal resistance (for example 50 ohm (50 Ω)).
System 600 further comprises the backward channel receiver, and it comprises resistor R ISO, resistor R1, R3, capacitor C1, C3, LPF 604, HPF 606 and hysteresis comparator 608.As shown, this first conductor (CML+) of forward channel reflector is also by relatively large resistors in series R ISOBe connected to the positive input of LPF604 and negative input to reduce load.Very clear, relatively large resistors in series can comprise have enough large resistance value resistor to reduce the load of node.The R1-C1 filter is connected to the negative terminal of LPF604 and at least basically extracts the common-mode voltage of forward channel reflector.Thereby single-ended signal is transformed to differential signal in output place of LPF604.Yet it will be understood by those skilled in the art that the conversion of the single-ended-to-difference signal that can use other type.LPF 604 also eliminates forward channel signal at least basically to recover (perhaps producing) reverse channel signals.And comprising a pair of capacitor C3, HPF 606 is coupling in respectively between the positive input and negative input of the positive output of LPF 604 and negative output and hysteresis comparator 608.In addition, HPF 606 comprises that a pair of resistor R3 is coupled in series between the positive input and negative input of hysteresis comparator 608, and is applicable to receive common-mode voltage Vcm on a node between resistor R3.HPF 606 is applicable at least basically eliminate the DC component that receives signal.LPF 604 series coupled HPF 606 cooperations are as band pass filter (BPF).Hysteresis comparator 608 produces logic high signal and produces logic low signal in response to trailing edge by for example rising edge in response to the reception signal, and generates backchannel data from receive signal.At another embodiment, system 600 can comprise digital processing circuit, and it is configured to generate backchannel data by one or more digital filtering techniques (for example AD converter etc.).
Fig. 6 B illustrates the block diagram of example high-speed data transmission device and low speed data receiver 600 according to another embodiment of the present disclosure.As shown, system 600 comprises the separator pattern configurations, and it uses the signal (forward channel signal and reverse channel signals) of two backward channel receivers to recover to arrive at from two different single-ended channels (for example, from CML+ with from CML-).System 600 comprises the backward channel receiver, and it comprises resistor R ISO, resistor R1, R3, capacitor C1, C3, LPF 604A, 604B, HPF 606A, 606B and hysteresis comparator 608A, 608B..As mentioned above, about Fig. 6, first conductor (CML+) of forward channel reflector by first-phase to large resistors in series R ISOBe coupled to positive input and the negative input of a LPF604A, to reduce load.In the present embodiment, the second conductor (CML-) by second-phase to large resistors in series R ISOBe connected to the 2nd LPF 604B, to reduce load.The R1-C1 filter of LPF 604B is connected to the positive terminal of LPF 604B, and at least basically extracts the common-mode voltage of forward channel reflector.Very clear, the R1-C1 filter of LPF 604B can have from the R1-C1 filter of LPF 604A compares different resistance and/or capacitance.For example, the R1-C1 filter of LPF 604A can comprise the first resistance and/or capacitance, and the R1-C1 filter of LPF 604B can comprise the second resistance and/or capacitance.LPF 604B also eliminates the reverse channel signals that forward channel signal provides by the second conductor (CML-) to recover (perhaps producing) at least substantially.And HPF606B comprises a pair of capacitor C3, and it is coupling between the positive input and negative input of the positive output of LPF 604B and negative output and hysteresis comparator 608B respectively.In addition, HPF 606B comprises a pair of resistor R3, and it is coupled in series between the positive input and negative input of this hysteresis comparator 608B, and is applicable to receive common-mode voltage Vcm on a node between resistor R3.HPF 606B is applicable at least basically eliminate the DC component that receives signal.LPF 604B cooperates as band pass filter (BPF) with HPF 606B series coupled.Hysteresis comparator 608B produces logic high signal and produces logic low signal in response to trailing edge by for example rising edge in response to the reception signal, and generates backchannel data from receive signal.
Fig. 7 illustrates the block diagram of example high-speed data receiver and low speed data reflector 700 according to another embodiment of the present disclosure.System 700 is example embodiment of 540 and 560 of the FC receiver 460 of system 400 and system 500.Especially, system 700 comprises the forward channel receiver with HPF 702, and has voltage to backward channel reflector, LPF 706, current mirror 708 and the resistor R4 of electric current (V2I) transducer 704.HPF 702 comprises an input, and it is coupled to the conductor of serial link.HPF is configured at least basically eliminate the forward channel signal that reverse channel signals receives with generation.
V2I transducer 704 receives backchannel data, and based on backchannel data generation current signal.LPF 706 comprises resistor R5, and it is coupled to the output of V2I transducer 704 and the input of current mirror 708.In addition, LPF706 comprises capacitor C2, and it is coupled to output and the negative supply voltage of V2I transducer 704, and it can also be at earth potential.LPF 706 controls the switching rate of reverse channel signals, makes its spectral content disturb indistinctively the spectral content of forward channel data.The conductor of serial link is coupled in the output of current mirror 708.Resistor R4 is coupling in positive voltage rail or inner the generation between bias voltage (Vbias as shown in Figure 7) and serial link conductor.Resistor R4 provide terminate load to serial link, and can be configured to the to have 50 ohm resistance of (50 Ω).In this configuration, current mirror 708 is modulated forward channel signal in response to backchannel data.
Fig. 8 illustrates the block diagram for another example system 800 of transmitting data according to another aspect of the present disclosure.In the system 100 of formerly describing, forward channel low speed data and high-speed data are time-multiplexed, to carry out the transmission in forward direction via full duplex single ended serial data link.The backward channel low speed data is modulated on forward channel signal, to carry out the transmission in inverse direction via full duplex single ended serial data link.In system 800, the forward channel low speed data is modulated on the high-speed forward channel signal, to be modulated on the high-speed forward channel signal with the same mode of backward channel low speed.
Especially, system 800 comprises high-speed data source 802, forward channel (FWD CHN) low speed data source 804 and backward channel (REV CHN) low speed data receiver 806, and all these is positioned at an end of full duplex single ended serial data link 840.High-speed data source 802 can generate parallel high-speed (HS) data (for example video data).In another embodiment, high-speed data source 802 can be to set up the high-speed clock source of half-duplex control channel in Clock Distribution system (for example, tree).Parallel, forward direction (channel) low speed (FLS) data (for example, control and/or voice data) that FWD CHN low speed data source 804 can generate.REV CHN low speed data receiver 806 can receive parallel, reverse (channel) low speed data (for example, controlling data).
System 800 further comprises serial link interface 820, and it is used for high-speed data source 802, FWDCHN low speed data source 804 and REV CHN low speed data receiver 806 are connected to full duplex single ended serial data link 840.Serial link interface 820 comprises that high-speed serializer 822, FWD CHN SE signal modulator 824, FWD CHN low-speed serial device 826, REV CHN low speed deserializer 828 and HS CHN suppress circuit 830.High-speed serializer 822 will become serial data from the parallel HS data transaction in high-speed data source 822, and the single-ended signal that produces forward channel data is used for transmitting via full duplex single ended serial data link 840.
And FWD CHN low-speed serial device 826 will become serial data from the parallel FLS data transaction in FWD CHN low speed data source 804.FWD CHN SE signal modulator 824 use serial FLS Data Modulation forward channel signals.FWD CHN SE signal modulator 824 can comprise conversion rate control, modulating the spectral content that forward channel signal is controlled backward channel with relatively slow mode, with at least basically from the spectral content of forward direction channel with its isolation.Sometimes, FWD low speed data source 804 can generate the FLS data with serial mode.In this case, can cancel FWD CHN low-speed serial device 826, and FWD CHN low speed data source 804 can be directly coupled to FWD CHN SE signal modulator 824.
HS CHN suppresses circuit 830 and suppresses the high-speed forward channel signal, with the serial of at least basically exporting the opposite end that is received from full duplex single ended serial data link 840, reverse (channel) low speed (RLS) data.Similar previous embodiment, it can be LPF or the BPF that is applicable to filtering high frequency forward channel signal that HS CHN suppresses circuit.Equally similarly, it can be the signal abatement apparatus that HS CHN suppresses circuit 830, and it is used at least basically eliminating forward channel signal.REV CHN low speed deserializer 828 becomes parallel RLS data with serial RLS data transaction, processes by REV CHN low speed data receiver 806 being used for.
At the other end of full duplex single ended serial link 840, system 800 comprises high-speed data receiver 856, FWD CHN low speed data receiver 862 and REV CHN low speed data source 868.High-speed data receiver 856 receives and processes parallel high-speed (HS) data (for example, video data) from high-speed data source 802.FWD CHN low speed data receiver 862 receives and processes from the parallel FLS data in FWD CHN low speed data source 804 (for example, control and/or voice data).REV CHN low speed data source 868 produces parallel RLS data (for example, controlling data) to be used for being transferred to REV CHN low speed data receiver 806.
System 800 further comprises serial link interface 850, and it is used for high-speed data receiver 856, FWD CHN low speed data receiver 862 and REV CHN low speed data source 868 are connected to full duplex single ended serial data link 840.Serial link interface 850 comprises that LS CHN suppresses circuit 852, high speed deserializer 854, HS CHN inhibition circuit 858, FWD CHN low speed deserializer 860, REV CHN low-speed serial device 866 and single-ended (SE) signal modulator 864.
LS CHN inhibition circuit 852 inhibition forward directions and backward channel low speed data signal are (for example, serial FLS and RLS data), at least basically to export serial, the forward channel data (for example HS data) of the opposite end that is received from full duplex single ended serial data link 840.For example, LS CHN inhibition circuit 852 can be HPF or the BPF that is applicable to filtering low frequency forward direction and backchannel data.High speed deserializer 854 is converted into parallel forward channel data with the serial forward channel data.Forward channel data is sent to high-speed data receiver 856 and processes.
HS CHN suppresses circuit 858 and suppresses high-speed forward channel signal (for example serial HS data), at least basically to export the low-speed forward channel data (for example FLS data) of the opposite end that is received from full duplex single ended serial data link 840.For example, HS CHN inhibition circuit 858 can be LPF or the BPF that is applicable to filtering high frequency forward channel data.FWD CHN deserializer 860 becomes parallel FLS data with serial FLS data transaction.These FLS data are sent to FWD CHN low speed data receiver 862 and process.
REV CHN low-speed serial device 866 will become serial RLS data from the parallel RLS data transaction in REV CHN low speed data source 868.This RLS Data Modulation forward channel signal of SE signal modulator 864 use.SE signal modulator 864 can comprise conversion rate control, modulating the spectral content that forward channel signal is controlled backward channel with relatively slow mode, with at least basically from the spectral content of forward direction channel with its isolation.Forward direction and reverse low speed data are modulated onto on the high-speed forward channel data at different times.Thereby communicating by letter of low-speed forward and backward channel is semiduplex mode.Yet, the high-speed forward channel data can be simultaneously and low-speed forward or backchannel data transmit together.Should be appreciated that, other forward channel low speed data can be time-multiplexed together with the forward channel high-speed data; Thereby, provide two kinds of methods to be used for sending the forward channel low speed data.
Conclusion
Although in specific structural features and/or in processing the diction of operation, this theme has been described, will be appreciated that the theme that defines in accessory claim not necessary be limited to concrete as mentioned above feature or action.On the contrary, concrete feature and action are to come disclosed as the exemplary form that realizes claim as mentioned above.

Claims (20)

1. system that uses single-ended communication link to carry out full-duplex communication, it comprises:
The first LI(link interface), it is configured to generate signal and transmits via described single-ended communication link being used for, and described signal is included in coded data in forward channel; And
The second LI(link interface), it is configured to receive described signal from described the first LI(link interface) via described single-ended communication link, and modulate described signal with coded data in backward channel, make described signal comprise simultaneously described forward channel data and described backchannel data.
2. system as claimed in claim 1, wherein, described forward channel data comprises relative high-speed serial data and relative low-speed serial data.
3. system as claimed in claim 2, wherein, described relative high-speed serial data comprises video data, and described relative low-speed serial data comprise the control data.
4. system as claimed in claim 2, wherein, described backchannel data comprises relative low-speed serial data.
5. system as claimed in claim 2, wherein, described the first LI(link interface) further comprises the first serializer, wherein said the first serializer is configured to generate described relative high-speed serial data from relative high-speed parallel data.
6. system as claimed in claim 5, wherein, described the first LI(link interface) further comprises the second serializer, wherein said the second serializer is configured to generate described relative low-speed serial data from relative low-speed parallel data.
7. system as claimed in claim 1, described the first LI(link interface) comprises that further forward channel suppresses circuit, wherein said forward channel suppresses the forward channel data part that Circnit Layout becomes at least basically to suppress described signal, at least basically to export the backchannel data part of the described signal that is received from described communication link.
8. system as claimed in claim 7, wherein, described forward channel data is transmitted in the first frequency scope, and described backchannel data is transmitted in the second frequency scope, described first frequency scope is higher than described second frequency scope, and wherein, described forward channel suppresses circuit comprises the signal that filtering is transmitted in described first frequency scope low pass filter.
9. system as claimed in claim 1, further comprise single-ended communication link, and it is used for described the first LI(link interface) and described the second LI(link interface) are coupled.
10. device, it comprises:
Reflector, it is configured to generate signal and transmits via single-ended communication link being used for, described signal comprises forward channel data and backchannel data simultaneously, described forward channel data is encoded on forward channel by described reflector, and described backchannel data is encoded on backward channel by receiver, and wherein said receiver is configured to modulate the described signal from described reflector; And
Forward channel suppresses circuit, and it is configured at least basically suppress the forward channel data part of described signal, at least basically to export the backchannel data part of the described signal that is received from described communication link.
11. install as claimed in claim 10, wherein, described forward channel data comprises relative high-speed serial data, and described backchannel data comprises relative low-speed serial data.
12. install as claimed in claim 11, wherein, described relative high-speed serial data comprises video data, and described relative low-speed serial data comprise the control data.
13. install as claimed in claim 10, wherein, described backchannel data comprises relative low-speed serial data.
14. install as claimed in claim 10, wherein, described reflector further comprises the first serializer, wherein said the first serializer is configured to generate described relative high-speed serial data from relative high-speed parallel data.
15. install as claimed in claim 14, wherein, described reflector further comprises the second serializer, wherein said the second serializer is configured to generate described relative low-speed serial data from relative low-speed parallel data.
16. install as claimed in claim 10, wherein, described forward channel data is transmitted in the first frequency scope, and described backchannel data is transmitted in the second frequency scope, described first frequency scope is higher than described second frequency scope, and wherein, described forward channel suppresses circuit comprises the signal that filtering is transmitted in described first frequency scope low pass filter.
17. a device, it comprises:
Receiver, it is configured to receive the signal via single-ended communication link transmission, described signal comprises forward channel data and backchannel data simultaneously, described forward channel data is encoded in forward channel by reflector, and described backchannel data is encoded in backward channel by described receiver, and described receiver is configured to modulate the described signal from described reflector; And
Backward channel suppresses circuit, and it is configured at least basically suppress the backchannel data part of described signal, at least basically to export the forward channel data part of the described signal that is received from described communication link.
18. install as claimed in claim 17, wherein, described forward channel data comprises relative high-speed serial data, and described backchannel data comprises relative low-speed serial data.
19. install as claimed in claim 18, wherein, described relative high-speed serial data comprises video data, and described relative low-speed serial data comprise the control data.
20. install as claimed in claim 17, wherein, described forward channel data is transmitted in the first frequency scope, and described backchannel data is transmitted in the second frequency scope, described first frequency scope is higher than described second frequency scope, and wherein, described backward channel suppresses circuit comprises the signal that filtering is transmitted in described second frequency scope high pass filter.
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