CN103151385A - NMOS (N-Channel Metal Oxide Semiconductor) and PMOS (P-Channel Metal Oxide Semiconductor) device structures and design method - Google Patents
NMOS (N-Channel Metal Oxide Semiconductor) and PMOS (P-Channel Metal Oxide Semiconductor) device structures and design method Download PDFInfo
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- CN103151385A CN103151385A CN2013100988740A CN201310098874A CN103151385A CN 103151385 A CN103151385 A CN 103151385A CN 2013100988740 A CN2013100988740 A CN 2013100988740A CN 201310098874 A CN201310098874 A CN 201310098874A CN 103151385 A CN103151385 A CN 103151385A
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Abstract
The invention provides NMOS (N-Channel Metal Oxide Semiconductor) and PMOS (P-Channel Metal Oxide Semiconductor) device structures and a design method. In the NMOS device structure, the STI (Shallow Trench Isolation) width perpendicular to the channel direction has the minimum design rule dimension, and the STI width along the channel direction also has the minimum design rule dimension. In the PMOS device structure, the STI width perpendicular to the channel direction has the minimum design rule dimension, and the STI width along channel direction is from 4 to 7 times that of the minimum design rule dimension.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to a kind of NMOS and PMOS device architecture and method for designing.
Background technology
Along with the complexity of integrated circuit (IC) design is more and more higher, size is more and more less, and the effect of isolation technology in integrated circuit is made is more and more important.Isolation technology under CMOS technique mainly comprises dielectric material isolation and reverse PN junction isolation etc., and wherein dielectric material is isolated in the elimination parasitic transistor, reduces mutual capacitance, and all there is outstanding performance the aspects such as latch-up of inhibition metal-oxide-semiconductor.In the technique of 3-0.35 μ m, selective oxidation (LOCOS) technique is widely used, but this technique has the defective of self: (1) beak (bird ' s beak) structure makes a silicon dioxide invade active area (a 2) oxygen and is infused in and occurs in pyroprocess to distribute again, causes that narrow width effect (narrow width effect) (a 3) silicon dioxide of active device is in the uneven surface configuration of narrow isolated area attenuation (4).These defectives seem particularly outstanding when entering into 0.18 μ m and following process node, LOCOS technique is unavailable.Therefore, along with device is developed to nanometer by deep-submicron, shallow trench isolation has substituted from (STI) technology the isolation technology that the LOCOS technology becomes main flow.The STI technology is compared with the LOCOS technology, have complete in beak, fully planarization, good advantages such as anti-breech lock, and the STI technology can avoid high-temperature technology, reduces to finish spacing and junction capacitance, guaranteed the area of active area, improved integrated level.
Along with reducing of device active region area, STI stress will be can not ignore the impact of device performance, make performance of devices strongly relevant in the position of active area to area and the device of device active region, it not only exerts an influence to device threshold voltage, carrier mobility to device also will exert an influence, and then affect the drive current of device.Due to the difference that nmos device and PMOS device prolong the piezoresistance coefficient of channel direction and vertical-channel direction, prolong the tensile stress of channel direction and the tensile stress of vertical-channel direction and can promote the nmos device performance; Prolong the compression of channel direction and the tensile stress of vertical-channel direction and can promote the PMOS device performance.Usually STI can introduce compression in device, mainly improves STI stress to the impact of device by improving technique at present, needs high cost but improve technique.Fig. 1 has shown the schematic top plan view of the H type grate MOS device structure of prior art, and this structure can be nmos device or PMOS device, the STI isolation 120 that it generally includes source region 100, grid 110 and is surrounded by the source region.Wherein the width of STI isolated area is not optimized.
Summary of the invention
One of purpose of the present invention is to address the above problem.
In one aspect of the invention, provide a kind of nmos device structure, wherein:
The STI width of vertical-channel direction has the minimum design rule size; The STI width that prolongs channel direction also has the minimum design rule size.
In another aspect of this invention, also provide a kind of PMOS device architecture, wherein
The STI width of vertical-channel direction has the minimum design rule size; Prolong the STI width of channel direction between 4 to 7 times of minimum design rule size.
Of the present invention also have one aspect, a kind of method for designing of nmos device is provided, wherein,
Reduce nmos device vertical-channel direction and along the STI width of channel direction.
Of the present invention also have one aspect, a kind of method for designing of PMOS device is provided, wherein,
Reduce the STI width of PMOS device vertical-channel direction and increase the PMOS device along the STI width of channel direction.
Compared with prior art, the present invention has the following advantages: simple, can well improve STI stress to the impact of device performance, and increase the saturation current of device, device performance is got a promotion.
Description of drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the schematic top plan view according to the MOS device architecture of prior art;
Fig. 2 is the schematic top plan view according to nmos device structure of the present invention;
Fig. 3 is the schematic top plan view according to PMOS device architecture of the present invention;
Fig. 4 is the nmos device performance comparison schematic diagram that prolongs the different STI width of channel direction;
Fig. 5 is the PMOS device performance contrast schematic diagram that prolongs the different STI width of channel direction;
Fig. 6 is the PMOS device performance contrast schematic diagram of the different STI width of vertical-channel direction.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they are only example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or setting.In addition, the invention provides the example of various specific techniques and material, but those skilled in the art can recognize the use of applicability and/or the other materials of other techniques.Should be noted that illustrated parts are not necessarily drawn in proportion in the accompanying drawings.The present invention has omitted description to known assemblies and treatment technology and technique to avoid unnecessarily limiting the present invention.
The minimum design rule size of the STI width described in literary composition is provided by foundries, can be different according to different technique.For example the minimum design rule size of STI width can be 1 times, 1.1 times, 1.2 times, 1.3 times, 1.4 times, 1.5 times or larger of channel width.
In one aspect of the invention, provide a kind of nmos device structure, wherein:
The STI width of vertical-channel direction has the minimum design rule size; The STI width that prolongs channel direction also has the minimum design rule size.
In another aspect of this invention, also provide a kind of PMOS device architecture, wherein
The STI width of vertical-channel direction has the minimum design rule size; Prolong the STI width of channel direction between 4 to 7 times of minimum design rule size.
Of the present invention also have one aspect, a kind of method for designing of nmos device is provided, wherein,
Reduce nmos device vertical-channel direction and along the STI width of channel direction.
According to a specific embodiment of the present invention, the STI width that nmos device is designed to the vertical-channel direction has the minimum design rule size; The STI width that prolongs channel direction also has the minimum design rule size.
Of the present invention also have one aspect, a kind of method for designing of PMOS device is provided, wherein,
Reduce the STI width of PMOS device vertical-channel direction and increase the PMOS device along the STI width of channel direction.
According to a specific embodiment of the present invention, the STI width that is the vertical-channel direction with the PMOS designs has the minimum design rule size; Prolong the STI width of channel direction between 4 to 7 times of minimum design rule size.
Below in conjunction with accompanying drawing, the present invention is described in further detail.
With reference to figure 2, the STI isolation 220 that H type grid nmos device includes source region 200, grid 210 and is surrounded by the source region.Wherein, gate shapes can also be long strip type or T-shaped.Active area is divided into channel region, source region and drain region by grid, and wherein channel region is positioned under grid, and source region and drain region lay respectively at grid both sides.In the present embodiment, gate shapes is the H type, and active area also comprises body contact zone part.Compare with the sti structure of traditional devices, the sti structure of nmos device of the present invention has less width prolonging on channel direction and/or vertical-channel direction, for example according to the minimum design rule size, is for example 0.21um.As shown in Figure 4, reduce to prolong the STI width of channel direction, can improve the performance of nmos device.
With reference to figure 3, the STI isolation 320 that H type grid PMOS device includes source region 300, grid 310 and is surrounded by the source region.Wherein, gate shapes can also be long strip type or T-shaped.Active area is divided into channel region, source region and drain region by grid, and wherein channel region is positioned under grid, and source region and drain region lay respectively at grid both sides.In the present embodiment, gate shapes is the H type, and active area also comprises body contact zone part.Compare with the sti structure of traditional devices, the sti structure of PMOS device of the present invention has less width on the vertical-channel direction, according to the minimum design rule size, is for example 0.21um; And/or have larger width prolonging channel direction, for example between 4 to 7 times of minimum design rule size, for example for 0.8um between the scope of 1.5um.The consideration of comprehensive area, effect is best when 1um, and the width that also namely prolongs the sti structure of channel direction is 5 times of minimum design rule size.As shown in Figure 5, increase the STI width that prolongs channel direction, can improve the PMOS performance of devices.As shown in Figure 6, reduce the STI width of vertical-channel direction, can improve the PMOS performance of devices.
Although describe in detail about example embodiment and advantage thereof, be to be understood that and carry out various variations, substitutions and modifications to these embodiment in the situation that do not break away from the protection range that spirit of the present invention and claims limit.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, can use them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (9)
1. nmos device structure, wherein:
The STI width of vertical-channel direction has the minimum design rule size; The STI width that prolongs channel direction also has the minimum design rule size.
2. nmos device structure according to claim 1, wherein nmos device is H type grid nmos devices.
3. PMOS device architecture, wherein
The STI width of vertical-channel direction has the minimum design rule size; Prolong the STI width of channel direction between 4 to 7 times of minimum design rule size.
4. PMOS device architecture according to claim 3, the width that wherein prolongs the sti structure of channel direction is 5 times of minimum design rule size.
5. PMOS device architecture according to claim 3, wherein the PMOS device is H type grid PMOS device.
6. the method for designing of a nmos device, wherein,
Reduce nmos device vertical-channel direction and along channel direction the STI width.
7. method according to claim 6, the STI width that wherein nmos device is designed to the vertical-channel direction has the minimum design rule size; The STI width that prolongs channel direction also has the minimum design rule size.
8. the method for designing of a PMOS device, wherein,
Reduce the STI width of PMOS device vertical-channel direction and increase the PMOS device along the STI width of channel direction.
9. method according to claim 8, be wherein that the STI width of vertical-channel direction has the minimum design rule size with the PMOS designs; Prolong the STI width of channel direction between 4 to 7 times of minimum design rule size.
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| CN101819947A (en) * | 2009-02-27 | 2010-09-01 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| CN102412156A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Additional sample filling method of polysilicon gate for improving hole mobility of PMOS (P-channel Metal Oxide Semiconductor) devices |
| CN102629285A (en) * | 2011-02-07 | 2012-08-08 | 格罗方德半导体公司 | Methods for fabricating an electrically correct integrated circuit |
| CN102646147A (en) * | 2012-04-24 | 2012-08-22 | 中国科学院微电子研究所 | Modeling method of metal oxide semiconductor (MOS) device |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1574278A (en) * | 2003-05-29 | 2005-02-02 | 松下电器产业株式会社 | Semiconductor integrated circuit device |
| US20080283871A1 (en) * | 2007-05-15 | 2008-11-20 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| CN101819947A (en) * | 2009-02-27 | 2010-09-01 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
| CN102629285A (en) * | 2011-02-07 | 2012-08-08 | 格罗方德半导体公司 | Methods for fabricating an electrically correct integrated circuit |
| CN102412156A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Additional sample filling method of polysilicon gate for improving hole mobility of PMOS (P-channel Metal Oxide Semiconductor) devices |
| CN102646147A (en) * | 2012-04-24 | 2012-08-22 | 中国科学院微电子研究所 | Modeling method of metal oxide semiconductor (MOS) device |
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