CN103151346B - ESD protection circuit - Google Patents
ESD protection circuit Download PDFInfo
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- CN103151346B CN103151346B CN201110412062.XA CN201110412062A CN103151346B CN 103151346 B CN103151346 B CN 103151346B CN 201110412062 A CN201110412062 A CN 201110412062A CN 103151346 B CN103151346 B CN 103151346B
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Abstract
The present invention provides the integrated circuit with static discharge (ESD) protection circuit.Esd protection circuit does not include polysilicon resistance.Esd protection circuit can include n-channel transistor, and it is connected in parallel between output node and ground terminal, and wherein output node is connected to input/output pin.N-channel transistor can each have drain terminal and source terminal, and the former coupled to output node by the first metal path, and the latter coupled to ground terminal by the second metal path.The first and second metal path can be connected up on the gate terminal of respective n-channel transistor, thus enough resistance is provided.First and second metal path can provide desired pull down resistor in esd protection circuit, in order to ESD circuit can reduce the enough electric currents by each n-channel transistor, thus protects internal circuit to be without prejudice in esd event.
Description
Technical field
The present invention relates to electrostatic discharge (ESD) protection, and be particularly used for protecting the circuit from due to quiet
The circuit of the infringement that discharge event causes.
Background technology
Integrated circuit is frequently exposed to the electrostatic charge of potential damage.Such as, during making, integrated
Circuit chip can be exposed to electric charge.This electric charge may be from producing the plasma etching of charged particle
Technology or other technique.As another example, touch unintentionally the exposure in circuit package as workman
Pin, maybe when this encapsulation is due to the movement that is encapsulated in pallet and during static electrification electric charge, encapsulates integrated
Circuit can be exposed to electric charge.
These electrostatic charges can damage the sensitive circuit on integrated circuit.Such as, when being exposed to
During big electric current, transistor or other electric devices on integrated circuit just can suffer damage.
In order to reduce the electrostatic charge impact on sensitive circuit, integrated circuit can have static discharge to be protected
Protection circuit.Traditional ESD protection circuit includes polyresistor, and it provides desired electricity
Resistance.Along with integrating device climbs (i.e. 28nm and higher complementation towards higher level technology node
Metal-oxide semiconductor technique), make design rule and the layout of polysilicon resistance is produced restriction.
As a result, the polysilicon resistance formed in this adhesive integrated circuit can provide the biggest resistance value, and
And it is unable to provide enough electrostatic discharge (ESD) protections.
Summary of the invention
Integrated circuit can include static discharge (ESD) protection circuit.Esd protection circuit can be portion
Demultiplexing is in the output driver circuit of driving chip external signal.
Esd protection circuit can associate respective input-output pin, and electric current can be by the latter at electrostatic
IC apparatus is flow to during electric discharge event.ESP protection circuit can include multiple n-channel crystal
Pipe, it is connected in parallel between output node and ground terminal.Output node is connectable to association should
Input/output (I/O) pin of esd protection circuit.Can be formed in substrate (such as silicon substrate)
N-channel transistor.
Each n-channel transistor in esd protection circuit can have: grid；Drain terminal,
It is connected to output node by first group of metal path；Source terminal, it passes through second group of metal
Path is connected to ground terminal.First and second groups of metal path are at the drop-down electricity of esd protection circuit
Flow path provides desired resistance, in order to enough electric currents can flow through esd protection circuit, and not
Inside sensitive circuit on infringement device.
Polyresistor can not be used to form esd protection circuit.Neighbouring in esd protection circuit
N-channel transistor can share virtual architecture (dummy structure), and the latter is used for meeting density and wants
Ask.Resistance polysilicon mask (being sometimes referred to as silicide agglomeration mask) can not be used to form ESD protection
Circuit, because metal path can provide enough pull down resistors.
In a kind of suitable layout, the n-channel transistor in esd protection circuit is about mirror each other
As (such as, the drain diffusion region of neighbouring n-channel transistor is only by single virtual polysilicon structure
Separate, and the source diffusion region of neighbouring n-channel transistor is only divided by single virtual polysilicon structure
From).In this mirror-image constructions, it is usable in M1 metal wiring layer (such as, closest to substrate
Metal wiring layer) in first group of metal path being formed make the leakages of two neighbouring n-channel transistor
The pole short-circuit of terminals, and second group of metal path can be used to make the source electrode of two neighbouring n-channel transistor
The short-circuit of terminals.Metal path in first group of metal path can be connected up (folding) adjacent at two
On the grid of transistor, the drain terminal of two of which adjacent transistor is connected.Can be by second group of gold
Belong to metal path wiring (folding) in path on the grid of two adjacent transistor, wherein two
The source terminal short circuit of individual adjacent transistor.Can use and be routed in higher metal wiring layer (such as,
Metal wiring layer on M1 metal level) on metal by the short circuit of first group of metal path.Can use
Higher metal wiring layer wiring metal by second group of short circuit metal.Use this staggered metal line
Arrange that forming metal path can be that esd protection circuit provides desired pull down resistor.
In another is suitably arranged, the n-channel transistor in esd protection circuit is not in relation to mirror each other
As (such as, given transistor drain diffusion region and close on the source diffusion region of transistor by
Single virtual architecture separates).In this non-mirror-image constructions, first group of metal path be connectable to
Determine the drain diffusion region of transistor, and second group of metal path is connectable to give the source of transistor
Pole diffusion zone.Metal path in first and second groups of metal path can be connected up (folding) to exist
On the gate terminal of given transistor.It is usable on higher metal wiring layer the metal of wiring by the
One group of metal path short circuit.It is usable on higher metal wiring layer the metal of wiring by second group of gold
Belong to path short circuit.Forming metal path can be esd protection circuit to use the wiring of this folded metal to arrange
Desired pull down resistor is provided.
By accompanying drawing and described further below, further characteristic of the invention, its feature and various excellent
Point will be apparent from.
Accompanying drawing explanation
Fig. 1 illustrates have the exemplary integrated of the ESD protection circuit according to the embodiment of the present invention
Circuit diagram.
Fig. 2 is shown as the illustration of the part integrated circuit output driver according to the embodiment of the present invention
The circuit diagram of property ESD protection circuit.
Fig. 3 illustrates the top view of the conventional electrostatic discharge protection circuit with polyresistor.
Fig. 4 illustrates that the exemplary circuit of the ESD protection circuit according to the embodiment of the present invention is implemented
The schematic diagram of example.
Fig. 5 and Fig. 6 illustrates the top view of the exemplary electrostatic discharge protection circuit according to the present invention.
Fig. 7 illustrates according to embodiments of the invention, at the electrostatic discharge (ESD) protection forming Fig. 5 and Fig. 6
The exemplary block diagram comprised in circuit.
Fig. 8 illustrates, according to embodiments of the invention, how the electric current flowing through input/output pin can be made
Function change for the voltage of input/output pin.
Detailed description of the invention
Integrated circuit usually causes electrostatic charge.Such as, if people is not intended to touch the defeated of integrated circuit
Entering/export (I/O) pin, the device in integrated circuit can cause electrostatic charge by the skin of people.
Also electrostatic charge can be gradually increased during production of integrated circuits or during carrying.
During electrostatic discharge event, the big electric current of development can damage the circuit on integrated circuit.Such as,
Human body can discharge the electric current of up to 1.5A by the I/O pin of integrated circuit, and processing, surveying
The bad electrostatic charge that examination, carrying and run duration are developed by I/O pin can develop into up to
The electric current of 8A.
This is related to protection of integrated circuit from the dysgenic method of electrostatic charge, and especially,
Relating to such circuit, it is for preventing sensitive circuit and device by exposure to bad high voltage
With electric current and undermined.It can be used for protecting by any suitable integrated circuit package, as transistor,
The circuit that diode, resistance, electric capacity, inductance etc. are formed.
Fig. 1 illustrates such integrated circuit, and it includes the digital and analog circuit formed in the substrate
12 and other circuit.This substrate can be such as p-type silicon substrate.Integrated circuit 10 can include storage
Device sheet, digital signal processing circuit, microprocessor, application-specific integrated circuit, able to programme
Integrated circuit or other suitable integrated circuits.
As it is shown in figure 1, integrated circuit 10 can include input/output (I/O) circuit, such as along collection
Become the I/O circuit 16 that each edge of circuit 10 is formed.Circuit 16 can be used for making signal leave dress
Put 10, and for receiving signal by I/O pin 14 from other devices.
Circuit 16 can include static discharge (ESD) protection circuit, such as esd protection circuit 18
With other I/O circuit, it allows integrated circuit 10 by pin 14 and outside (chip is outer) assembly
Communication.Esd protection circuit 18 can be used for limiting electrostatic (noise) magnitude of current flowing through pin 14.
Restriction can flow to the magnitude of current of device 10 by pin 14 can sensitive circuit in protection device 10
The infringement that (such as digital and analog circuit 12) causes from electrostatic discharge event.Therefore, sometimes
Esd protection circuit 18 can be described as ESD clamp circuit.As shown in Figure 1, it is possible at device 10
Core (such as, at immediate vicinity and interlock with circuit 12) forms esd protection circuit 18
Striped.
Fig. 2 is the circuit diagram illustrating esd protection circuit 28.In the example in figure 2, circuit 12
Represent the sensitive internal circuit on integrated circuit 10.Circuit 19 can be phase inverter, and it is used as circuit
The output driver of 12.Phase inverter 19 can include p-channel metal-oxide semiconductor (MOS) (PMOS)
Transistor, such as transistor 30, and n-channel metal-oxide semiconductor (MOS) (NMOS) transistor,
Such as transistor 28.Transistor 28 can be used as esd protection circuit.Phase inverter 19 can be by positive supply
Terminal 24 receive positive voltage Vcc and ground power terminals 26 receive ground voltage Vss
Power supply.
In properly functioning, circuit 12 can (i.e. the input of phase inverter 19, it be even to node 22
Connect the grid of transistor 28 and 30) output signal is provided.Phase inverter 19 can convert at node 22
The output signal provided, thus the converted version of output signal is produced at output node 27.Can be at arrow
The direction shown in 32 is set being supplied to outside at 27 converted output signals provided by pin 14
Standby (for example, with reference to Fig. 2).
As shown in Figure 2, it is possible to other circuit, such as circuit 12 ' are connected to output node 27.
Circuit 28 can be used for the effect of esd protection circuit.Such as, processing, testing, removing
The electrostatic charge produced during fortune and other operations can cause the less desirable magnitude of current to pass through pin 14,
Device 10 is flow in the direction shown in arrow 34.This less desirable ESD electric current " can be inhaled by circuit 28
Receive " (such as, as shown in drop-down current path 36, it is undesirable to electric current to can flow through NMOS brilliant
Body pipe 28, and do not damage transistor 28 and circuit 12).This pull-down current path (such as, is drawn
Path between foot 14 and ground terminal 26) design can determine that whether circuit 28 can reduce foot
Enough electric currents, thus protection circuit 12 during esd event from infringement.
Device 10 can have more than one output driver 19.The each I/O pin 14 of association can be there is
Output driver 19.Circuit 28 in respective output driver 19 can be collectively referred to as ESD protect
Protection circuit 18 (Fig. 1).
Fig. 3 illustrates the top view of traditional esd protection circuit.As it is shown on figure 3, traditional ESD
Protection circuit includes the nmos pass transistor 40 being connected in parallel.Each nmos pass transistor 40 wraps
Include grid 42, drain terminal region D and source terminal region S.Any in substrate is not brilliant
The region of body pipe 40 part all has shallow trench isolation (STI) formed on a surface of the substrate
Structure (such as, any be not the region of oxide diffusion zone or transistor channel region be all STI
Region).
For each transistor 40, virtual polysilicon gate construction 44 (is sometimes referred to as " terrible " polycrystalline
Silicon) all become with distance D-shaped with grid 42, and in parallel with grid 42.Each transistor 40
Having the virtual architecture 44 groups of their own, it associates the transistor that this is special.Polyresistor 46
Region between every a pair adjacent transistors 40 is formed.
The drain terminal of transistor 40 is connected to first group of polysilicon by respective metal path 56
Resistor 46.(the most such metal wiring layer, it is at M1 metal wiring layer for metal path 56
Substrate in integrated circuit dielectric stack) middle formation.Especially, each metal path 56
Having: the first terminal, it is connected to the leakage of transistor 40 by oxide diffusion zone contact 52
Extreme son；And second terminal, its by polysilicon-M1 contact 53 (the most such contact, its
It is connected on substrate the polysilicon structure formed and the metal path formed in M1 metal wiring layer)
It is connected to the first terminal of the polyresistor 46 of association.
Each polyresistor 46 in first group of polyresistor passes through metal path 58,
It is connected at M2 metal wiring layer (metal wiring layer such as formed on M1 metal wiring layer)
The metal tape (plate) 64 of middle formation.Plate 64 is in the drain diffusion region of two adjacent transistors 40
On formed (for example, with reference to Fig. 3).Especially, each metal path 58 has: first
Terminal, it is connected to associate the second end of polyresistor 46 by polysilicon-M1 contact 53
Son；And second terminal, it is connected to metal tape 64 (i.e., so by M1-M2 through hole 54
Metal throuth hole, its be connected in M1 metal wiring layer formed metal path and at M2 hardware cloth
The metal path formed in line layer).
The source terminal of each transistor 40 uses similar wire structures and bonding ribbon 62.
The source terminal of transistor 40 is connected to second group of polyresistor 46 by metal path 56.
Especially, every metal path 56 all has: the first terminal, and it is touched by oxide diffusion zone
Point 52 is connected to source terminal；And second terminal, it is connected by polysilicon-M1 contact 53
It is connected to associate the first terminal of polyresistor 46.
Each polyresistor 46 in second group of polyresistor is by metal path 58
And it is connected to metal tape 62 (metal tape such as formed in M2 metal wiring layer).Plate 62 exists
(for example, with reference to Fig. 3) is formed on the source region of two adjacent transistors 40.Especially,
Every metal path 58 all has: the first terminal, and it is connected to by polysilicon-M1 contact 53
Second terminal of association polyresistor 46；And second terminal, it passes through M1-M2 through hole
54 and be connected to metal tape 62.
As it is shown on figure 3, represented ESD pull-down current path by dotted line 60.During esd event,
Electric current flows through I/O pin, the resistor 46 flowing through the drain terminal being connected to transistor 40, flows through
Transistor 40, flow through the source terminal being connected to transistor 40 polyresistor 46 and
Flow into ground wire.
Use polyresistor 46 thus desired resistance value is provided in pull-down current path.So
And, in higher level technology node (i.e. 28nm and higher complementary metal oxide semiconductor technique),
Make design rule and limit very much the polysilicon resistance that can be placed between every a pair adjacent transistors
The number of device 46.Especially, arrow 48 is relative with the polysilicon-polysilicon silicon space requirement shown in 50
In a upper technology node notable bigger (such as, 45nm CMOS technology).As a result, traditional E SD
The region of protection circuit will acutely increase, and pull-down current path can suffer too much resistance.Too
High pull down resistor would not allow for esd protection circuit and reduces enough electric currents in esd event.Knot
Really, internal circuit can sustain damage.
Fig. 4 illustrates that of the esd protection circuit 28 of Fig. 2 is appropriately carried out.As shown in Figure 4,
Esd protection circuit 28 can include multiple n-channel transistor, the n-channel crystal being such as connected in parallel
Pipe 28 '.Each transistor 28 ' can have source S and drain D.(source S and drain D have
Time be referred to collectively as source-drain terminal, source drain or source-drain regions at this.) transistor
28 ' are attached between output node 27 and ground wire terminal 26.Node 27 is connectable to pin 14
(the most such pin, ESD electric current flows to device 10 by it).Ground wire terminal 26 is connectable to
Ground wire pin 14 '.
Each transistor 28 ' in this parallel-connection structure can associate respective branch road 29.Each branch road
Transistor 28 ' in 29 all has: drain terminal, and it connects node 27 by conductive path, should
The line resistance of conductive path is Rd；And source terminal, it connects node 26 by conductive path, is somebody's turn to do
The line resistance of conductive path is Rs.Connect drain terminal and node 27, the Yi Jilian of transistor 28 '
The conductive path (line) of the source terminal and node 26 that connect respective transistor 28 ' can provide expectation
Resistance value, it makes circuit 28 reduce enough electric currents during electrostatic discharge event, in order to protection dress
Put the circuit 12 on 10 from infringement (such as, the Rd on every branch road 29, transistor channel electricity
The drop-down series connection of combination of resistance and Rs is not that resistance is the least, so all of ESD electric current flows only through one
Bar branch road 29, and be not too big, thus ESD circuit 28 in the esd event of worst case still
Enough electric currents can be reduced).Form esd protection circuit in like fashion to need not use polysilicon electricity
Resistance device.
Example shown in Fig. 4 is only exemplary.Optionally, esd protection circuit 28 can include
It is in parallel that more than three transistors 28 ' or less than three transistors 28 ', (such as, circuit 28 can wrap
Include the branch road 29 of any desired number).Connect in parallel in Fig. 2 that multiple transistor 28 ' is formed
Transistor 28 sometimes can be described as having " referring to " structure more.
Fig. 5 illustrates the top view (Fig. 4) of a suitable layout of esd protection circuit 28.Such as figure
Shown in 5, each n-channel transistor 28 ' may comprise: grid, as grid (area of grid) 72,
Drain terminal region D and source terminal region S.Area of grid 72 can be inserted into the special crystalline substance of association
Between drain terminal region and the source terminal region of body pipe 28 '.Grid 72 can be polysilicon gate
Structure or other suitable conductive gate structure.Drain electrode and source region can be described as defining zoneofoxidation sometimes
Territory, and can be n+ doped region (as an example).In substrate surface is not oxide definition,
And it not the region (such as, directly region) under each grid 72 of transistor channel region
Can have shallow trench isolation (STI) structure, it is formed on the surface of substrate.
Virtual architecture can be formed on substrate, such as virtual architecture 74, its from grid 72 apart from for x,
And it is in parallel with the grid 72 of each transistor 28 '.Virtual architecture 74 can be formed on sti structure.
Can be formed virtual architecture 74 by any suitable material, the density of this material is similar to transistor gate 72 (example
Such as polysilicon gate) or peripheral circuits in the density of other these class formations.Therefore, structure 74 is sometimes referred to as
For virtual polysilicon structure or ghost polysilicon structure.
Such as, polysilicon can be used to form virtual architecture 72, thus meet polysilicon density requirements (i.e.
So that it is guaranteed that the density of esd protection circuit fully mates the density of peripheral circuits).Close for meeting
Degree coupling require density complys with structure, as virtual architecture 74 sometimes can be described as virtual interstitital texture or
Dummy gate structure.
As it is shown in figure 5, single virtual architecture 74 can be formed between every a pair adjacent transistors 28 '.
This single virtual architecture can be described as " sharing " virtual architecture.Sharing virtual architecture in like fashion can be abundant
Reduce the area of esd protection circuit 28, because each there is himself with two adjacent transistors
The structure that virtual architecture is 74 groups is compared, and can place tightr by two adjacent transistors 28 '.
OD-M1 contact (such as, M1 can be formed in the drain diffusion region of given transistor 28 '
The definition oxidation of metal wiring layer contact), such as contact 76.Formed in M1 metal wiring layer leads
Power path, such as metal path 80, can every all there is the first terminal being each connected to contact 76.
Can be towards source diffusion region wiring (folding) of given transistor on the grid 72 of given transistor
(such as, metal path 80 may pass through at least some drain diffusion region, area of grid to metal path 80
72 and source diffusion region).Metal path 80 can every all have and be connected to M1-M2 through hole,
Second terminal of such as M1-M2 through hole 78.Through hole 78 is connectable to expand at the source electrode of given transistor
Dissipate the conductive plate 84 (for example, see Fig. 5) formed on region.Metal tape 84 can connect pin 14, electricity
Stream can flow to device 10 by the latter during esd event.
Use this structure, the drain diffusion region of each transistor 28 ' is connected the metal of pin 14
Path 80 collective can represent expectation resistance value Rd combining Fig. 4 description.
Similar wiring can be used to arrange the source diffusion region of each transistor 28 ' is connected ground connection
Terminal.OD-M1 contact 76 can be formed in the source diffusion region of given transistor 28 '.?
In M1 metal wiring layer formed conductive path, such as metal path 81, can every all have first
Terminal, it is connected in the source diffusion region of given transistor the contact 76 formed.Can be at given crystalline substance
On the grid 72 of body pipe towards given transistor source diffusion region wiring metal path 81 (such as,
Metal path can overlap with lower part, i.e. gives at least some source diffusion region of transistor, gives
At least some area of grid 72 of transistor and at least some drain diffusion regions of given transistor
Territory).Metal path 81 can every all there is the second terminal being connected to M1-M2 through hole 78.Through hole
78 conductive plates 82 being connectable in the drain diffusion region of given transistor to be formed (for example, with reference to
Fig. 5).Metal tape 82 can connect ground terminal.
Use this structure, the source diffusion region of each transistor 28 ' is connected the metal of ground wire terminal
Path 81 collective can represent expectation resistance value Rs combining Fig. 4 description.
Using the connection formed in higher metal wiring layer, by the leakage at each transistor 28 '
The metal tape 82 formed on the diffusion zone of pole is electrically short-circuited to each other and (such as, uses M3, M4 or M5 metal
Metal wiring in wiring layer).If the connection being usable in higher metal wiring layer being formed is by each
Transistor 28 ' is electrically short-circuited to each other, so that it may form metal tape 84 in source diffusion region.Use this structure
Bonding ribbon formation combines being connected in parallel of the branch road 29 of Fig. 4 description.
Use be wound around as shown in Figure 5 (folding) layout wiring metal path 80 and 81 can be
The drain terminal of transistor 28 ' and source terminal provide desired line resistance.Leakage at transistor 28 '
Extreme son and source terminal provide desired line resistance that esd protection circuit 28 can be made to reduce enough electricity
Stream, and do not make all of ESD electric current all flow only through a transistor 28 ' (such as, a part of ESD
Can desirably flow through each branch road 29, enter ground terminal, and not to sensitive internal circuit 12
Cause damage).
Transistor 28 ' in Fig. 5 is not in relation to mirror images of each other.Such as, the leakage of the first transistor 28 '
Pole diffusion zone is adjacent to the source diffusion region (example neighbouring with the first transistor of transistor seconds 28 '
As, the drain diffusion region of the first transistor is on the left of the grid 72 of the first transistor, and the second crystal
The drain diffusion region of pipe is also on the left of the grid 72 of transistor seconds).Virtual architecture 74 points can be passed through
Drain diffusion region and the source diffusion region of transistor seconds from the first transistor.
In the layout of Fig. 5, metal can be formed on source diffusion region or drain diffusion region
Band, the latter is formed in M2 metal wiring layer.Such as, metal tape 82 can be at given transistor 28
' drain diffusion region on formed, and metal tape 84 can be in the source diffusion region of given transistor
On formed.On given source diffusion region formed metal tape 84 non-extensible exceed neighbouring
Diffusion zone, because neighbouring diffusion zone is the drain diffusion region covered by metal tape 82.Class
As, on given drain diffusion region, the metal tape 82 of formation is non-extensible exceedes neighbouring diffusion
Region, because neighbouring diffusion zone is to have been used the source diffusion region that metal tape 84 covers.Gold
Belong to band 82 and 84 and can be perpendicular to metal path 80 and 81, and grid 72 can be parallel to, be parallel to
Different drain diffusion region and be parallel to different source diffusion region.
Another that figure 6 illustrates esd protection circuit 28 is suitably arranged.As shown in Figure 6, often
Individual n-channel transistor 28 ' may comprise grid 72, drain terminal region D and source terminal district
Territory S.Grid 72 can be polysilicon gate construction or other suitable conductive gate structure.Substrate surface
In be not oxide definition, and be not that the region of transistor channel region (such as, directly exists
Region under each grid 72) can have shallow trench isolation (STI) structure, it is at the table of substrate
Face is formed.
Virtual architecture can be formed on substrate, such as virtual architecture 74, its from grid 72 apart from for x,
And it is in parallel with grid 72.Sti structure is formed virtual architecture 74.Can be at two neighbouring crystalline substances
Share single virtual architecture 74 between body pipe 28 ', thus reduce the area of esd protection circuit 28.
Transistor 28 ' in Fig. 6 is about mirror images of each other.Such as, the drain electrode of the first transistor 28 '
Diffusion zone adjacent to transistor seconds 28 ' the drain diffusion region neighbouring with the first transistor (such as,
The drain diffusion region of the first transistor is on the left of the grid 72 of the first transistor, and transistor seconds
Drain diffusion region is on the right side of the grid 72 of transistor seconds).First can be separated by virtual architecture 74
The drain diffusion region of transistor and the drain diffusion region of transistor seconds.Similarly, first crystal
The source diffusion region of pipe can be adjacent to the source diffusion region of third transistor 28 ', and the latter is adjacent to first
Transistor.Source diffusion region and the third transistor of the first transistor can be separated by virtual architecture 74
Source diffusion region.
OD-M1 contact 76 can be formed in the drain diffusion region of given transistor 28 '.At M1
The conductive path formed in metal wiring layer, such as metal path 88, can every all have be connected to each
The first terminal from contact 76.Can be towards neighbouring given transistor on the grid 72 of given transistor
The drain diffusion region wiring metal path 88 of another transistor 28 '.Metal path 88 can every
All there is the second terminal, its be connected in the drain diffusion region of adjacent transistors formed each touch
Point 76 (for example, see Fig. 6).
M1-M2 through hole, such as M1-M2 can be formed in the centre position along every metal path 88
Through hole 78.Through hole 78 be connectable to two adjacent transistors 28 ' (such as, given transistor,
And another transistor of neighbouring this given transistor) source diffusion region on the conductive plate 92 that formed.
Metal tape 92 can connect pin 14, and electric current flows to device 10 by the latter during esd event.
Use this structure, the drain diffusion region of each transistor 28 ' is connected the metal of pin 14
Path 88 collective can represent expectation resistance value Rd combining Fig. 4 description.
Similar wiring can be used to arrange the source diffusion region of each transistor 28 ' is connected ground connection
Terminal.OD-M1 contact 76 can be formed in the source diffusion region of given transistor 28 '.?
In M1 metal wiring layer formed conductive path, such as metal path 89, can every all have first
Terminal, it is connected in the source diffusion region of given transistor the contact 76 formed.Metal path 89
Can every all on the grid 72 of given transistor, by another transistor towards neighbouring given transistor
Source diffusion region wiring (folding) of 28 '.Metal path 88 also can be by the grid in adjacent transistors
Fold on pole 72.Metal path 89 can have the second terminal, and it is connected to the source in adjacent transistors
The contact 76 (for example, with reference to Fig. 6) formed in the diffusion zone of pole.
M1-M2 through hole 78 can be formed in the centre position along every metal path 89.Through hole 78
It is connectable at two adjacent transistors 28 ' (such as, given transistor, and neighbouring this give
Another transistor of transistor) drain diffusion region on formed conductive plate 90.Metal tape 90 can connect
Connect ground terminal.
Use this structure, the source diffusion region of each transistor 28 ' is connected the metal of ground wire terminal
Path 89 collective can represent expectation resistance value Rs combining Fig. 4 description.
The metal connected up in higher metal wiring layer can be used formation on drain diffusion region
Metal tape 90 is electrically short-circuited to each other, and being wherein usable in the metal line in higher metal wiring layer will be in source
Metal tape 92 short circuit formed on the diffusion zone of pole.Use the method bonding ribbon formed about
Being connected in parallel of branch road 28 described in Fig. 4.
Use the interlaced arrangement wiring metal path 88 and 89 as shown in Figure 6 can be at transistor 28
' drain terminal and source terminal provide desired line resistance.Transistor 28 ' drain terminal and
Source terminal provides desired line resistance that esd protection circuit 28 can be made to reduce enough electric currents, and not
All of electric current is made all to flow only through a transistor 28 '.ESD electric current is made to flow only through one in like fashion
Transistor 40 can destroy this transistor undesirably, causes esd protection circuit may not operate.
In the layout of Fig. 6, can be the drain diffusion region of two adjacent transistors 28 ' or two
Forming metal tape on the source diffusion region of adjacent transistors 28 ', the latter is at M2 metal line
Formed in Ceng.The metal tape 92 formed on the source diffusion region of two adjacent transistors 28 '
Non-extensible exceed neighbouring diffusion zone, because neighbouring diffusion zone is by metal tape 90
The drain diffusion region being formed on.Similarly, in the drain diffusion of two adjacent transistors 28 '
On region, the metal tape 90 of formation is non-extensible exceedes neighbouring diffusion zone, because neighbouring diffusion
Region is to have been used the source diffusion region that metal tape 92 is formed on.Metal tape 90 and 92 can
It is perpendicular to metal path 88 and 89, and grid 72 can be parallel to.
Fig. 5 and Fig. 6 is only the exemplary configuration of esd protection circuit.Optionally, can be used other
Suitable transistor direction or metal line structure, thus desired pull down resistor value is provided.
Metal path/plate 80,81,82,84,88,89,90 and 92 is to be formed by conductor bar
Path, such as elongate rectangular metal region.
Fig. 7 illustrates and forms the making step that transistor 28 ' is comprised.Transistor 28 ' can have
The grid formed on substrate (the p trap formed the most in the substrate) and source drain diffusion zone 94
Pole 72.It not that the region in the substrate surface of portion of transistor 28 ' can include sti region.Can divide
Dummy gate structure 74 (step 91) is formed on the sti structure of a pair neighbouring transistor 28 '.
In step 93, can on wafer deposit silicide 96, wherein transistor 28 ' shape on wafer
Become.Source electrode and drain diffusion region 94 can be covered with silicide completely, thus reduce contact resistance.Can
Use silicide process (such as, autoregistration depositing operation), chemical deposition, physical deposition or other classes
The depositing operation deposit silicide 96 of type.Can need not use polysilicon against corrosion (RPO) mask (to have
Time be referred to as silicide agglomeration mask).In step 95, can form OD-M1 contact 76, it contacts transistor
The source diffusion region 94 of 28 '.
In traditional esd protection circuit, need polysilicon mask against corrosion, thus cover ESD and protect
Some part of protection circuit.The part of covering of esd protection circuit prevents from being formed silicide, thus increases
Add the resistance of the metallic conductor in contact diffusion region.Silicide agglomeration mask is used to improve contact resistance
For necessary in traditional E SD protection circuit, thus in pull-down current path, provide enough series connection
Resistance.
Fig. 8 illustrates the ability to the function as pin voltage (Vpin), flows to device by pin 14
Electric current (Ipin) figure of 10.Curve 100,102 and 104 is three single characteristic curves, its
Representing the performance of appropriately designed RSD protection circuit, its every all reflects ESD pull-down current path
In different resistance values.Such as, curve 100 can represent that the ESD with the first pull down resistor value protects
Characteristic I-V (current-voltage) of the performance of protection circuit.Curve 102 can represent have ratio first time
Characteristic I-V of the performance of the esd protection circuit of the second pull down resistor value that pull-up resistor value is big.Curve
104 can represent the esd protection circuit with the threeth pull down resistor value bigger than the second pull down resistor value
Characteristic I-V of performance.
Esd protection circuit 28 can be designed such that it is able to stand the electrostatic charge of at least 7V, thus
Meet design standard.Such as, curve 104 illustrates, esd protection circuit 28 can be by 7V electrostatic
Electric current in electric discharge event (for example, with reference to the dotted line 108 shown in Fig. 8) is down to 1.4A.Design
The pull-down current path with too high resistance can cause the bad decline of this peak point current.
Curve 100,102 and 104 also for higher levels of current (such as, for more than 0.1A
Ipin) show the positive gradient.This positive gradient reflection circuit 28 is by drop-down different of parallel resistances
Road 29 reduces the ability (Fig. 4) of electric current.Design has the pull-down current path of the lowest resistance value
The gradient that can cause higher levels of current becomes negative.In I-V characteristic curve in higher levels of current
Negative slope may result in such situation, during wherein ESD electric current flows only through drop-down branch road 29
Bar.A large amount of electric currents flow through a branch road 29 can be destroyed esd protection circuit and cause fault.
Pull-down current path in circuit 29 can show that desired resistance value is (such as, less greatly the most also
The least resistance value), in order to esd protection circuit 28 can be by different drop-down branch roads 29
Reduce enough electric currents, and so that the inside sensitive circuit of device 10 is protected in electrostatic discharge event
Hold and be without prejudice.
Additional embodiment 1. circuit, it comprises: transistor, it has source region, drain region
And area of grid；More than first conductive strips, each of which is connected to described drain region, and
Each of which all passes source region described at least some, drain region and area of grid；And the
More than two conductive strips, it is staggered with described more than first conductive strips, wherein said more than second conductions
In band be each connected in described source region, and described more than second conductive strips every
One all passes source region described at least some, drain region and area of grid.
Additional embodiment 2. comprises according to the circuit described in additional embodiment 1, wherein said transistor
N-channel transistor, described circuit comprises p-channel transistor, wherein said n-channel crystal further
Pipe and p-channel transistor are connected in parallel between positive power terminal and ground terminal, and form tool
There is the phase inverter of output.
Additional embodiment 3. according to the circuit described in additional embodiment 2, its comprise further input-
Output pin, described output connects described input-output pin.
Additional embodiment 4. is according to the circuit described in additional embodiment 3, and wherein said drain region is complete
Entirely covered by silicide, and described source region is covered by silicide completely.
Additional embodiment 5. ESD protection circuit, it comprises: the first transistor source-drain region
Territory；Transistor seconds source-drain regions；Area of grid, its described the first transistor source electrode of insertion-
Between drain region and transistor seconds source-drain regions, wherein said first and second transistors
Source-drain regions and area of grid form the part of transistor；And conductive path, it is electrically connected
Connect described first source-drain regions, and the first transistor source drain described in crossover at least some
Grid described in transistor seconds source-drain regions described in region, at least some and at least some
Region.
Additional embodiment 6. is according to the ESD protection circuit described in additional embodiment 5, Qi Zhongsuo
Stating conductive path to include: the first conductor band, it is through the first and second source electrodes-leakage described at least some
Territory, polar region and described area of grid；And, the second conductor band, it is perpendicular to described first conductor
Band.
Additional embodiment 7. is according to the ESD protection circuit described in additional embodiment 6, Qi Zhongsuo
State in first and second conductor bands different metal wiring layer in integrated circuit dielectric stack and formed.
Additional embodiment 8. is according to the ESD protection circuit described in additional embodiment 7, Qi Zhongsuo
State conductive path and include at least one through hole.
Additional embodiment 9. is according to the ESD protection circuit described in additional embodiment 8, Qi Zhongsuo
State conductive path and include at least two through hole.
Additional embodiment 10. is according to the ESD protection circuit described in additional embodiment 9, wherein
In said two through hole at least one is inserted between described first and second conductor bands, and even
Connect described first and second conductor bands.
Additional embodiment 11. is according to the ESD protection circuit described in additional embodiment 10, wherein
Described first conductor band comprises at least one in such a plurality of parallel conductor band, each of which
All pass the first and second source-drain regions described at least some and described area of grid, and
Each all uses respective through hole to be connected to described second conductor band.
Additional embodiment 12. is according to the ESD protection circuit described in additional embodiment 5, and it enters
One step comprises the 3rd source-drain regions, the 4th source-drain regions and other area of grid,
The transistor that its forming part is other, the 3rd source described in wherein said conductive path crossover at least some
Described in 4th source-drain regions described in gate-drain region, at least some and at least some other
Area of grid.
Additional embodiment 13. is according to the ESD protection circuit described in additional embodiment 12, and it enters
One step comprises dummy gate region, the latter be inserted into described transistor and described other transistor it
Between, wherein said conductive path passes described dummy gate region.
Additional embodiment 14. is according to the ESD protection circuit described in additional embodiment 6, and it enters
One step comprises other conductive path, and the latter includes the 3rd conductor band, and it is through described at least some
First and second source-drain regions and described area of grid；And, the 4th conductor band, it hangs down
Straight in described 3rd conductor band.
Additional embodiment 15. is according to the ESD protection circuit described in additional embodiment 14, and it enters
One step comprises input-output pin, and wherein said conductive path is electrically connected to described input-output and draws
Foot.
Additional embodiment 16. is according to the ESD protection circuit described in additional embodiment 15, and it enters
One step comprises: ground terminal, and wherein said other conductive path is electrically connected to described grounding pin.
Additional embodiment 17. circuit, it comprises: circuit, it has output；Integrated circuit input-
Output pin；And phase inverter, it is connected to described input and output and described IC input
Enter-output pin between, wherein said phase inverter includes p-channel transistor and the n ditch being connected in series
Road transistor, wherein said n-channel transistor comprises drain region, source region and gate regions
Territory, and wherein said phase inverter comprises at least one conductor band, drain region described in its crossover,
Described source region and described area of grid.
Additional embodiment 18. is according to the circuit described in additional embodiment 17, and wherein said conductor band is not
Comprising at least one in such first group of parallel conductor band, its each all drains described in crossover
Region, described source region and described area of grid, and its each be connected to described leakage
Territory, polar region, described circuit comprises second group of parallel conductor band further, its each all crossover drain electrode
Region, described source region and described area of grid, and its each be connected to described source
Territory, polar region.
Additional embodiment 19. is according to the circuit described in additional embodiment 18, and it comprises further: the
One conducting wire, it is parallel to described drain region, and drain region described in crossover；And,
Second conducting wire, it is parallel to described source region, and source region described in crossover, wherein
Each strip conductor band in described first group of parallel conductor band is connected to described first conducting wire,
And each strip conductor band in wherein said second group of parallel conductor band is connected to described second and leads
Electric line.
Additional embodiment 20. is according to the circuit described in additional embodiment 19, and it comprises at least further
One dummy gate, the conductor band in wherein said first group of parallel conductor band is at described dummy gate
On through.
The most only principle of the illustration present invention, and without departing from scope and spirit of the present invention, this area
Technical staff can make various change.Individually or embodiments above can be implemented with any combination.
Claims (16)
1. ESD protection circuit, it comprises:
Transistor, it has source region, drain region and the area of grid being formed on substrate；
More than first conductive strips, each of which is connected to described drain region, and each of which is all worn
Cross source region described at least some, described drain region and described area of grid；
More than second conductive strips, it is staggered with described more than first conductive strips, and wherein said more than second
Being each attached in described source region, and described more than second conductive strips in individual conductive strips
Each through source region, described drain region and described area of grid described at least some；
And
Forming bunch media over the substrate, wherein said bunch media includes alternate metal wiring layer
And via layer, and wherein said more than first conductive strips and described more than second conductive strips are formed at
In same metal wiring layer in described bunch media.
ESD protection circuit the most according to claim 1, wherein said transistor comprises
N-channel transistor, described circuit comprises p-channel transistor, wherein said n-channel crystal further
Pipe and described p-channel transistor are connected in series between positive power terminal and ground terminal, and shape
Become there is the phase inverter of output.
ESD protection circuit the most according to claim 2, its comprise further input-
Output pin, described output connects described input-output pin.
ESD protection circuit the most according to claim 3, wherein said drain region is complete
Entirely covered by silicide, and wherein said source region is covered by silicide completely.
5. ESD protection circuit, it comprises:
The first transistor source-drain regions；
Transistor seconds source-drain regions；
Area of grid, it inserts described the first transistor source-drain regions and described transistor seconds
Between source-drain regions, wherein said the first transistor source-drain regions, described second crystal
Pipe source-drain regions and described area of grid form the part of transistor；And
Conductive path, it is electrically connected to described the first transistor source-drain regions, and crossover is extremely
Transistor seconds source electrode described in fewer described the first transistor source-drain regions, at least some-
Area of grid described in drain region and at least some, wherein said conductive path includes: the first conductor
Band, it is through the first transistor source-drain regions, described transistor seconds source described at least some
Gate-drain region and described area of grid；And the second conductor band, it is perpendicular to described first conductor
Carry and through area of grid described at least some, and wherein said first conductor band has: the
One end, described first end is connected to described the first transistor source-drain regions；And second
End, described second end only uses a conductive through hole to be connected to described second conductor band.
ESD protection circuit the most according to claim 5, wherein said first conductor band
Formed with in described second conductor band different metal wiring layer in integrated circuit bunch media.
ESD protection circuit the most according to claim 5, wherein said conductive path bag
Including at least one additional vias, described the first transistor source-drain regions is connected to described by it
Two conductor bands.
ESD protection circuit the most according to claim 7, wherein said first conductor band
Comprise in a plurality of parallel conductor band, all wear for every in wherein said a plurality of parallel conductor band
Cross the first transistor source-drain regions described at least some, described transistor seconds source-drain region
In territory and described area of grid, and described a plurality of parallel conductor band every uses respective logical
Hole is connected to described second conductor band.
ESD protection circuit the most according to claim 5, comprises the 3rd crystal further
Pipe source-drain regions, four transistor sources-drain region and other area of grid, its shape
Become the part of other transistor, the 3rd crystal described in wherein said conductive path crossover at least some
Four transistor sources-drain region and at least some described in pipe source-drain regions, at least some
Described other area of grid.
ESD protection circuit the most according to claim 9, comprises dummy gate further
Region, it is inserted between described transistor and described other transistor, wherein said conductive path
Footpath passes described dummy gate region.
11. ESD protection circuits according to claim 5, comprise other leading further
Power path, it includes the 3rd conductor band, and described 3rd conductor band is brilliant through described at least some first
Body pipe source-drain regions and described transistor seconds source-drain regions and described area of grid；With
And the 4th conductor band, it is perpendicular to described 3rd conductor band.
12. ESD protection circuits according to claim 11, comprise further:
Input-output pin, wherein said conductive path is electrically connected to described input-output pin.
13. ESD protection circuits according to claim 12, comprise further:
Ground terminal, wherein said other conductive path is electrically connected to grounding pin.
14. ESD protection circuits, comprise:
Circuit, it has output；
Integrated circuit input-output pin；
Phase inverter, it is connected between described output and described integrated circuit input-output pin, its
Described in phase inverter include the p-channel transistor and the n-channel transistor that are connected in series, wherein said n
Channel transistor comprises drain region, source region and area of grid, and wherein said anti-phase
Device comprises at least one conductor band, drain region, described source region described in described conductor band crossover
And described area of grid；And
Dummy gate, it is formed on fleet plough groove isolation structure, and wherein said at least one conductor band exists
Pass through on described dummy gate.
15. ESD protection circuits according to claim 14, wherein said conductor band bag
Containing one in first group of parallel conductor band, every in wherein said first group of parallel conductor band all
Drain region, described source region and described area of grid described in crossover, and described first group also
Every in connection conductor band is connected to described drain region, and described circuit comprises second group further
Parallel conductor band, drain region described in all crossovers of every in wherein said second group of parallel conductor band,
Every in described source region and described area of grid, and described second group of parallel conductor band all
It is connected to described source region.
16. ESD protection circuits according to claim 15, comprise: first further
Conducting wire, it is parallel to described drain region, and drain region described in crossover；And second
Conducting wire, it is parallel to described source region, and source region described in crossover, wherein said
Every strip conductor band in first group of parallel conductor band is connected to described first conducting wire, and its
Described in every strip conductor band in second group of parallel conductor band be connected to described second conducting wire.
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| CN201110412062.XA CN103151346B (en) | 2011-12-07 | 2011-12-07 | ESD protection circuit |
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|---|---|---|---|---|
| CN107946294A (en) * | 2016-10-12 | 2018-04-20 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
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| JP6396834B2 (en) * | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| EP3312875A4 (en) * | 2015-06-19 | 2019-01-23 | Renesas Electronics Corporation | Semiconductor device |
| US10332871B2 (en) * | 2016-03-18 | 2019-06-25 | Intel IP Corporation | Area-efficient and robust electrostatic discharge circuit |
| KR102184449B1 (en) * | 2016-11-09 | 2020-12-01 | 삼성전자주식회사 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101226935A (en) * | 2007-01-15 | 2008-07-23 | 株式会社瑞萨科技 | Semiconductor integrated circuit device |
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| US7038280B2 (en) * | 2003-10-28 | 2006-05-02 | Analog Devices, Inc. | Integrated circuit bond pad structures and methods of making |
| TW200937607A (en) * | 2008-02-27 | 2009-09-01 | Elan Microelectronics Corp | Electrostatic discharge (ESD) protection device for high-voltage input-output pad |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946294A (en) * | 2016-10-12 | 2018-04-20 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
| CN107946294B (en) * | 2016-10-12 | 2020-10-27 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
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