CN103150427A - RAID design method based on SSD caching acceleration and backup - Google Patents
RAID design method based on SSD caching acceleration and backup Download PDFInfo
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- CN103150427A CN103150427A CN2013100533270A CN201310053327A CN103150427A CN 103150427 A CN103150427 A CN 103150427A CN 2013100533270 A CN2013100533270 A CN 2013100533270A CN 201310053327 A CN201310053327 A CN 201310053327A CN 103150427 A CN103150427 A CN 103150427A
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Abstract
The invention provides an RAID (Redundant Array of Independent Disks) design method based on SSD (Solid State Drive) caching acceleration and backup. The design method comprises the specific processes as follows: a server processor acquires data through a PCIE (Peripheral Component Interface Express) interface, wherein the data refers to calculated and processed data; a transmission route is constructed between the PCIE interface for transmitting the data acquired by the processor and the SSD; the data transmitted by the PCIE is decoded and transformed; the data obtained from the step 3 is cached in the SSD; the data in the SSD is unloaded in an external storage; and when the system is power-off, the data is unloaded again and a prompt is given. Compared with the prior art, the design method ensures the real-time performance, the reliability and the stability of the data acquired by the server, achieves the stable and effective data storage and acceleration, and improves the server performance.
Description
Technical field
The present invention relates to the computer communication technology field, specifically a kind of solve current in data transmission procedure in enormous quantities, the buffer memory of data depends on the DRAM mode of RAID card substantially, real-time, reliability, the stability of server data have been guaranteed, realize the stable valid data storage and acceleration of data, promoted the RAID method for designing of server performance.
Background technology
Current processor-server speed is more and more higher, the processor of high operational performance is used more and more extensive, when completing high operational performance, need under more susceptible condition the data after processor calculating and Internet Transmission are carried out the data storage, the data volume of especially current single file increases gradually, need to keep completing a large amount of data channel link transmission, just can complete storage and the transmission of single file, although server process performance and the network bandwidth improve constantly for many years, the main method that transmits data does not change all the time.Today, processor-server is being born whole heavy burdens such as agreement calculating of processing each data of load, access memory and processing or packet, in this case, introduce independently data buffer storage and accelerate and the backup design, have great importance for transmission and the storage of Large Volume Data.
The current buffer memory that transmission and the storage of Large Volume Data are depended on the raid card controller substantially, because the buffer memory capacity of current raid card is limited, maximum is only also 512MB, this is relatively for the data volume of current GB up to a hundred, its buffer memory capacity is still less than normal, if outage suddenly in transmitting procedure, data can't keep integrality; Because the buffer memory of raid card is on the high side, the buffer memory wires design is complicated simultaneously, and design stability control is strict, and this raid card cache way can't be realized low-cost jumbo application; On the other hand, because the raid card buffer memory is the DRAM mode, namely power failure data is lost, for keeping data in buffer memory, need to add expensive lithium battery module, the data of completing limiting time keep, when electric weight was not enough, data probably changed, and for the stability of data, certain influence were arranged.Along with server data stores and accelerated reliability are required constantly to increase, in order to guarantee the server data stable transfer, in data transmission procedure in enormous quantities, stablize the valid data storage and accelerate particularly importantly, and become one of decision server performance key element.
For the problems referred to above that run in current data transmission procedure in enormous quantities, need a kind of RAID method for designing in conjunction with key factors such as SSD storage speed, stability.
Summary of the invention
Technical assignment of the present invention is to solve the deficiencies in the prior art, provides a kind of and accelerates and the RAID method for designing that backs up based on the SSD hard disk cache.
Technical scheme of the present invention realizes in the following manner, this a kind of RAID method for designing of accelerating and back up based on the SSD hard disk cache, and its detailed process is:
Step 1, processor-server obtain data by the PCIE interface, the data after these data refer to computing and process;
Step 2, build processor data and transmit transmission path between PCIE interface and SSD hard disk;
Step 3, decoding data and conversion that PCIE is transmitted;
Step 4, will be temporary in the SSD hard disk through the data that step 3 is processed;
Step 5, the data conversion storage in the SSD hard disk is entered exterior storage;
Step 6, when outage appears in system, unloading again, and provide prompting.
Transmission path in described step 2 is built and is referred between PCIE interface and hard disk storage system, cache interface is set, and the SSD hard disk is connected to this cache interface.
Described cache interface adopts high speed FPGA to realize, namely PCIE interface and hard disk storage system interface all are connected on high speed FPGA, and SSD hard disk cache interface is also provided by this FPGA, and SSD hard disk cache interface is the SATA interface of standard.
Data decode in described step 3 refers to the data that PCIE transmits are carried out the serial data decoding, and data-switching refers to convert to SAS protocol format data stream.
Described data decode adopts high speed FPGA to realize with conversion: FPGA completes the decoding that PCIE transmits data, identifies data message, is temporary in the buffer memory of high speed FPGA; The data message that simultaneously this is identified changes SAS protocol format data stream into, and the SAS protocol format data stream transmitting after high speed FPGA will change is realized the high-speed cache of data to SSD hard disk cache interface.
The data that deposit exterior storage in SSD in described step 5 in are Large Volume Data, after extracting successively, these data write outside hard disk storage system, wherein SSD adopts first in first out, form data queue memory, new data constantly is pressed into formation, and old data constantly dump to outside hard disk storage system.
The beneficial effect that the present invention compared with prior art produces is:
A kind of RAID method for designing of accelerating and backing up based on the SSD hard disk cache of the present invention guarantees the server data stable transfer, real-time, the reliability of server data have been guaranteed, realize the stable valid data storage and acceleration of data, promoted server performance, saved the cost of transmission path.
Description of drawings
Accompanying drawing 1 is design cycle schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, a kind of RAID method for designing of accelerating and backing up based on the SSD hard disk cache of the present invention is described in detail below.
The present invention is with the data buffer storage scheduling theory strong point, solves that current the buffer memory of data depends on the DRAM mode of RAID card substantially in data transmission procedure in enormous quantities, and this mode can't guarantee the server data stable transfer.As shown in Figure 1, now provide a kind of and accelerate and the RAID method for designing that backs up based on the SSD hard disk cache, its detailed process is:
Step 1, processor-server obtain data by the PCIE interface, the data after these data refer to computing and process;
Step 2, build processor data and transmit transmission path between PCIE interface and SSD hard disk;
Step 3, decoding data and conversion that PCIE is transmitted;
Step 4, will be temporary in the SSD hard disk through the data that step 3 is processed;
Step 5, the data conversion storage in the SSD hard disk is entered exterior storage;
Step 6, when outage appears in system, unloading again, and provide prompting.
Transmission path in described step 2 is built and is referred between PCIE interface and hard disk storage system, cache interface is set, and the SSD hard disk is connected to this cache interface.
Described cache interface adopts high speed FPGA to realize, namely PCIE interface and hard disk storage system interface all are connected on high speed FPGA, and SSD hard disk cache interface is also provided by this FPGA, and SSD hard disk cache interface is the SATA interface of standard.Can be external SSD hard disk commonly used at present, improve compatible applicability; SSD hard disk cache capacity is according to the selection of can freely arranging in pairs or groups of different application scenarios, when transmitted data amount is bigger than normal, and the SSD hard disk that capable of selecting capacity is large.
Data decode in described step 3 refers to the data that PCIE transmits are carried out the serial data decoding, and data-switching refers to convert to SAS protocol format data stream.
Described data decode adopts high speed FPGA to realize with conversion: FPGA completes the decoding that PCIE transmits data, identifies data message, is temporary in the buffer memory of high speed FPGA; The data message that simultaneously this is identified changes SAS protocol format data stream into, SAS protocol format data stream transmitting after high speed FPGA will change is to SSD hard disk cache interface, realize the high-speed cache of data, the very big like this transfer rate that has improved processor efficient and data has reduced the processing latency of data.
The data that deposit exterior storage in SSD in described step 5 in are Large Volume Data, after extracting successively, these data write outside hard disk storage system, wherein SSD adopts first in first out, form data queue memory, new data constantly is pressed into formation, and old data constantly dump to outside hard disk storage system.Store Large Volume Data in SSD when the System Sudden power down, due to non-volatile, the retention performance of SSD, save data, need not the external cell support for a long time.Break in recovery, the data in SSD are write outside hard disk storage system again.
requirement according to the data transmission real-time, the high speed fpga chip is constantly accepted the data that processor-server sends over, because there is bottleneck in the storage system transmission speed of outside, the high speed fpga chip imports data stream in the SSD hard disk cache, by the data cached storage system that dumps to the outside in high speed FPGA control SSD, when quantity is larger, the spatial cache of opening up in SSD is just large, to increase the integrality of Large Volume Data, when quantity hour, the spatial cache of opening up in SSD is just less, to reduce the addressing time of SSD, the spatial cache of opening up in the actual SSD of being chosen at should be greater than the 1.5-2 of the capacity of maximum transmission data doubly, make transfer efficiency reach optimum.
Through top detailed enforcement, we can carry out the high-speed transfer of data under system very easily, not only reached the requirement of real-time of data transmission, and saved the cost of transmission path, improve data transmission efficiency and accuracy, improved the reliability and stability of server stores system.
Claims (6)
1. one kind is accelerated and the RAID method for designing that backs up based on the SSD hard disk cache, and it is characterized in that: its detailed process is:
Step 1, processor-server obtain data by the PCIE interface, the data after these data refer to computing and process;
Step 2, build processor data and transmit transmission path between PCIE interface and SSD hard disk;
Step 3, decoding data and conversion that PCIE is transmitted;
Step 4, will be temporary in the SSD hard disk through the data that step 3 is processed;
Step 5, the data conversion storage in the SSD hard disk is entered exterior storage;
Step 6, when outage appears in system, unloading again, and provide prompting.
2. according to claim 1 a kind of based on the RAID method for designing of SSD hard disk cache acceleration with backup, it is characterized in that: the transmission path in described step 2 is built and is referred between PCIE interface and hard disk storage system, cache interface is set, and the SSD hard disk is connected to this cache interface.
3. according to claim 2 a kind of based on the RAID method for designing of SSD hard disk cache acceleration with backup, it is characterized in that: described cache interface adopts high speed FPGA to realize, be that PCIE interface and hard disk storage system interface all are connected on high speed FPGA, SSD hard disk cache interface is also provided by this FPGA, and SSD hard disk cache interface is the SATA interface of standard.
4. according to claim 1 a kind of based on the RAID method for designing of SSD hard disk cache acceleration with backup, it is characterized in that: the data decode in described step 3 refers to the data that PCIE transmits are carried out the serial data decoding, and data-switching refers to convert to SAS protocol format data stream.
5. according to claim 4 a kind of based on the RAID method for designing of SSD hard disk cache acceleration with backup, it is characterized in that: described data decode adopts high speed FPGA to realize with conversion: FPGA completes the decoding that PCIE transmits data, identify data message, be temporary in the buffer memory of high speed FPGA; The data message that simultaneously this is identified changes SAS protocol format data stream into, and the SAS protocol format data stream transmitting after high speed FPGA will change is realized the high-speed cache of data to SSD hard disk cache interface.
6. according to claim 1 a kind of based on the RAID method for designing of SSD hard disk cache acceleration with backup, it is characterized in that: the data that deposit exterior storage in the SSD in described step 5 in are Large Volume Data, after extracting successively, these data write outside hard disk storage system, wherein SSD adopts first in first out, form data queue memory, new data constantly is pressed into formation, and old data constantly dump to outside hard disk storage system.
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| WO2015197027A1 (en) * | 2014-06-27 | 2015-12-30 | 华为技术有限公司 | Method for accessing nvme storage device, and nvme storage device |
| US10095445B2 (en) | 2016-03-29 | 2018-10-09 | Western Digital Technologies, Inc. | Systems and methods for offloading processing from a host to storage processing units using an interconnect network |
| CN109491934A (en) * | 2018-09-28 | 2019-03-19 | 方信息科技（上海）有限公司 | A kind of storage management system control method of integrated computing function |
| CN109933547A (en) * | 2019-01-29 | 2019-06-25 | 山东华芯半导体有限公司 | The passive accelerator of RAID and accelerated method in a kind of SSD master control |
| CN110377426A (en) * | 2019-07-19 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of data transmission method, system and associated component |
| CN110622145A (en) * | 2017-05-15 | 2019-12-27 | 莫列斯有限公司 | Reconfigurable server and server rack with reconfigurable server |
| CN113238991A (en) * | 2021-07-12 | 2021-08-10 | 湖南博匠信息科技有限公司 | Method for realizing hard RAID card function based on FPGA |
| CN113419977A (en) * | 2021-05-28 | 2021-09-21 | 济南浪潮数据技术有限公司 | PCIE equipment management system in server and server |
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