CN103137480A - Forming method of metal oxide semiconductor (MOS) device and MOS device formed through method - Google Patents
Forming method of metal oxide semiconductor (MOS) device and MOS device formed through method Download PDFInfo
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Abstract
The invention provides a forming method of a metal oxide semiconductor (MOS) device. The forming method comprises first providing a semiconductor substrate at least comprising three regions, enabling a first region to be used for forming a gate region, enabling a second region and a third region which are adjacent to the first region to be respectively used for forming a source region and a drain region; utilizing an epitaxial method to the semiconductor substrate of the first region to extend outwards to grow an epitaxial layer; then utilizing an isotropic etching method to etch the epitaxial layer to form a channel region; then utilizing the epitaxial method to grow silicon-germanium in the second region and the third region, and respectively forming a silicon-germanium source region structure and a drain region structure; and then doping the silicon-germanium source region structure and the drain region structure. The invention further provides the MOS device formed by utilizing the method. Due to the technical scheme, damage to a silicon substrate caused by etching of the source region and the drain region in a conventional method is avoided, the goal of reducing defects is achieved, and electric leakage of the formed MOS device in the using process cannot occur easily.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the MOS device that relates in particular to a kind of formation method of MOS device and utilize said method to form.
Background technology
The MOS device is one of primary element in integrated circuit.In recent years, occur employing silicon-germanium in semicon industry and improved the MOS device performance as source, drain electrode.Known, when uniaxial compressive directly put on transistorized channel region from silicon-germanium source region and drain region, the transistorized performance of PMOS can be improved.When uniaxial tensile strain was added on channel region, the performance of nmos pass transistor can be improved.
Fig. 1 is to Figure 3 shows that each structural representation that forms in the making step of employing silicon-germanium of the prior art as the MOS device of source, drain electrode.At first, with reference to figure 1, be depicted as the sectional view of common MOS structure.Particularly, this structure comprises: Semiconductor substrate 10, be formed on gate insulator 11 and grid 12 on substrate 10, the side of this gate insulator 11 and grid 12 is formed with insulative sidewall 13.Then, with reference to figure 2, utilize autoregistration, dry etching is removed the part semiconductor substrate 10 of source electrode and drain region, in order to follow-up formation silicon-germanium source electrode and drain electrode.Then, with reference to figure 3, on the zone that etching forms in above-mentioned steps, utilize epitaxy grown silicon-germanium, to form source electrode 14 and drain electrode 15 structures.
Yet the inventor finds, there are some defectives in above-mentioned way, particularly, in Fig. 2 etching process, in Semiconductor substrate 10, namely source electrode and drain region respectively with the zone at junction, the especially angle of Semiconductor substrate 10, can form some defectives.And when follow-up Implantation forms doped region, too fast for prevent that ion from spreading in silicon-germanium, need this source electrode and drain electrode are hanged down temperature control, and this defective can not be carried out fine reparation at this low temperature, is brought in the MOS device as defective.Source region and drain region leaky in the substrate in use easily occurs in this MOS device, causes the performance of devices variation.
In view of this, be necessary in fact to propose a kind of formation method of new MOS device, solve existing MOS device in manufacturing process, there are defective in source electrode and drain electrode, in use leaky can occur.
Summary of the invention
The problem that the present invention solves is a kind of formation method that proposes new MOS device, solves existing MOS device in manufacturing process, and there are defective in source electrode and drain electrode, in use leaky can occur.
For addressing the above problem, the invention provides a kind of formation method of MOS device, comprising:
Semiconductor substrate is provided; Described Semiconductor substrate comprises Three regions at least, and wherein, the first area is used to form gate regions, and second area, three zone adjacent with the first area are respectively used to form source region and drain region;
Utilize epitaxy that the Semiconductor substrate of described first area is stretched out and grow epitaxial loayer;
Utilize the described epitaxial loayer of isotropic etching method etching to form channel region;
Utilize epitaxy at second area, the 3rd region growing silicon-germanium, form respectively silicon-germanium source region structure, drain structure;
Described silicon-germanium source region structure, drain structure are adulterated.
Alternatively, described silicon-germanium source region structure, the drain structure step of adulterating is comprised light dope and heavy doping, form respectively light doping section and heavily doped region.
Alternatively, utilizing epitaxy to grow the epitaxial loayer step comprises:
Form successively the first dielectric layer and the second dielectric layer on described Semiconductor substrate; Described the first dielectric layer is different from described the second dielectric layer material;
Define area of grid on the second dielectric layer; Described the first dielectric layer and the second dielectric layer of removing described area of grid form the first opening;
Utilize the epitaxy described epitaxial loayer of growing in described the first opening, described epitaxial loayer is not filled completely described the first opening;
Deposit the 3rd dielectric layer is also removed the 3rd outer dielectric layer of described the first opening, and described the 3rd dielectric layer is different from described the second dielectric layer material;
Remove second dielectric layer in described second area and the 3rd zone.
Alternatively, after utilizing the described epitaxially grown Semiconductor substrate of isotropic etching method etching to form the channel region step, also remove the first dielectric layer step in second area, the 3rd zone, utilize afterwards epitaxy at second area, the 3rd region growing silicon-germanium, form respectively silicon-germanium source region structure, drain structure.
Alternatively, utilize epitaxy at second area, the 3rd region growing silicon-germanium, after forming respectively silicon-germanium source region structure, drain structure step, before described silicon-germanium source region structure, drain structure are carried out the heavy doping step, also carry out:
Form the 4th dielectric layer and be polished on described silicon-germanium source region structure, drain structure and described the 3rd dielectric layer and expose described the 3rd dielectric layer; Described the 4th dielectric layer is different from described the 3rd dielectric layer material;
Remove described the 3rd dielectric layer to form the second opening;
Deposit gate insulator material and grid material to be forming gate insulator and grid layer, and remove the second opening outer gate insulator material and grid material;
Remove described the 4th dielectric layer on described silicon-germanium source region structure, drain structure.
Alternatively, described silicon-germanium source region structure, the drain structure step of adulterating is comprised:
Described silicon-germanium source region structure, drain structure are carried out light dope;
Dual-side at described gate insulator and grid layer forms side wall;
Described silicon-germanium source region structure, drain structure are carried out heavy doping, make under described side wall and form light doping section, form heavily doped region in remaining described silicon-germanium source region structure, drain structure.
Alternatively, after removing described the 4th dielectric layer step on described silicon-germanium source region structure, drain structure, before described silicon-germanium source region structure, drain structure are carried out light dope, also carry out forming the sidewall step at the dual-side of described gate insulator and grid layer.
Alternatively, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all the boron Implantation.
Alternatively, described the first dielectric layer material is silicon dioxide, described the second dielectric layer material is silicon nitride, described the 3rd dielectric layer material is also silicon dioxide, described the 4th dielectric layer material is silicon nitride, utilizes phosphoric acid to carry out the second area on the described area of grid of described removal both sides, the second dielectric layer step in the 3rd zone.
Alternatively, utilize HF acid to carry out the first dielectric layer step in described removal second area, the 3rd zone.
Alternatively, utilize HF acid to carry out described the 3rd dielectric layer of described removal to form the second opening step.
Alternatively, utilize phosphoric acid to carry out described the 4th dielectric layer step on the described silicon of described removal-germanium source region structure, drain structure.
Alternatively, deposit gate insulator material and grid material are also removed in the second opening outer gate insulator material and grid material step, and described gate insulator material is silicon dioxide, and described grid material is polysilicon.
Alternatively, utilize the described epitaxially grown Semiconductor substrate of isotropic etching method etching to form in the channel region step, described isotropic etching method etching adopts wet etching, and etching agent is the mixture of HF, HNO3, acetic acid.
Alternatively, utilize the described epitaxially grown Semiconductor substrate of isotropic etching method etching to form in the channel region step, described isotropic etching method etching adopts dry etching, and etching agent is SF
6Or CF
4
The present invention also provides a kind of MOS device, is formed by the forming method of MOS device of foregoing description.
compared with prior art, the present invention has the following advantages: at first utilize epitaxy to form the epitaxial loayer that is arranged in channel region, this epitaxial loayer and Semiconductor substrate material and lattice structure are identical, utilize afterwards this epitaxial loayer of isotropic etching method etching, avoided the prior art self aligned approach to need the etching semiconductor substrate, thereby cause in source region and drain region respectively with the Semiconductor substrate junction and form the large defective (position at the angle shown in arrow in seeing Fig. 2 and Fig. 3, this angle is more sharp-pointed, around it, defective probability appears larger), reduced in Semiconductor substrate, namely in the source region, the damage that the drain region forms with the Semiconductor substrate intersection respectively, thereby, the MOS device that forms in use is not prone to leaky.
Description of drawings
Fig. 1 to Fig. 3 is each structural representation that forms in the making step of employing silicon-germanium of the prior art as the MOS device of source, drain electrode;
Fig. 4 is the flow chart of the formation method of MOS device provided by the invention;
Fig. 5 to Figure 17 is the intermediate structure schematic diagram according to the MOS device of Fig. 4 flow process formation;
Figure 18 is the final structure schematic diagram according to the MOS device of Fig. 4 flow process formation.
Embodiment
Existing MOS structure first adopts self aligned approach etching semiconductor substrate, the large defective that this process can form in Semiconductor substrate when forming silicon-germanium source electrode with drain electrode.Source region and drain region leaky in the substrate in use can appear in the MOS structure with this defective.for this problem, the present inventor proposes at first to utilize epitaxy to form the epitaxial loayer that is arranged in channel region, this epitaxial loayer and Semiconductor substrate material and lattice structure are identical, utilize afterwards this epitaxial loayer of isotropic etching method etching, avoided using the self aligned approach etching semiconductor substrate of available technology adopting, thereby, reduced in Semiconductor substrate, it is the source region, the damage that the drain region forms with the Semiconductor substrate intersection respectively, reached and reduced the defective purpose, the MOS device that forms in use is not prone to source region and drain region leaky in the substrate.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Owing to focusing on explanation principle of the present invention, therefore, drawing not in scale.
Fig. 4 is the flow chart of the formation method of MOS device provided by the invention.Fig. 5 to Figure 18 is according to the intermediate structure of the MOS device of Fig. 4 flow process formation and the schematic diagram of final structure.Below in conjunction with Fig. 4 and Fig. 5 to Figure 18, the method that forms the MOS device of the present invention is described in detail.For convenience of description, below take P type MOS device as the example introduction.
With reference to Fig. 4, at first, carry out S10, Semiconductor substrate 20 is provided, its schematic cross-section is as shown in Figure 5; This Semiconductor substrate 20 comprises Three regions at least, and wherein, first area I is used to form gate regions, and second area II, the three regional III adjacent with first area I are respectively used to form source region and drain region.In the present embodiment, Semiconductor substrate 20 is silicon, also can select as required germanium.
Then, still with reference to Fig. 4, carry out S15, utilize epitaxy that the Semiconductor substrate 20 of described first area I is stretched out and grow epitaxial loayer (not sign).In the present embodiment, because epitaxial loayer is identical with material and the lattice structure of Semiconductor substrate 20.
This step comprises the following steps S151-S155 in concrete implementation.
Carry out S151, form successively the first dielectric layer 21 and the second dielectric layer 22 on described Semiconductor substrate 20, the schematic cross-section of the structure that forms as shown in Figure 6.Wherein, described the first dielectric layer 21 is different from described the second dielectric layer 22 materials.In the present embodiment, described the first dielectric layer 21 materials are silicon dioxide, and described the second dielectric layer 22 materials are silicon nitride.In other embodiment, also can select as required material separately.
Carry out S152, define area of grid on the second dielectric layer 22; Described the first dielectric layer 21 and the second dielectric layer 22 that removal is positioned at described area of grid form the first opening 23, and the schematic cross-section of the structure that forms as shown in Figure 7.This step can adopt photoetching and etching method.Described photoetching is on photoresist with area of grid on mask plate design transfer to the second dielectric layer 22, forms the mask of patterning.Described etching be mask take this patterning as template, continue etching the first dielectric layer 21 and second dielectric layer 22 formation the first openings 23.These two kinds of methods of photoetching and etching are all the semiconductor conventional process.
Carry out S153, utilize epitaxy at described the first interior grown epitaxial layer of opening 23, form the structural section schematic diagram as shown in Figure 8.The epitaxial loayer of growth is not filled completely described the first opening 23.Epitaxy in this step can be molecular beam epitaxy, and technique can adopt existing technique.
Carry out S154, deposit the 3rd dielectric layer 24 is also removed described the first the 3rd outer dielectric layer 24 of opening 23, forms the schematic cross-section of structure as shown in Figure 9, and the remaining area of the first opening 23 is filled full.Described the 3rd dielectric layer 24 is different from described the second dielectric layer 22 materials.In the present embodiment, described the 3rd dielectric layer 24 materials are also silicon dioxide.
Carry out S155, removes the second area II on described area of grid both sides and the second dielectric layer 22 of the 3rd regional III, formation structural section schematic diagram as shown in figure 10.In this step, the second dielectric layer 22 materials are silicon nitride, and the removal method can adopt phosphoric acid, preferred hot phosphoric acid.
After above-mentioned steps was completed, the first dielectric layer 21 of second area II and the 3rd regional III still existed, and in step S20 implementation, played the purpose of the Semiconductor substrate 20 of the described second area II of protection and the 3rd regional III.
Be understandable that, the first dielectric layer 21 in this step also can adopt other layer, and the material of this layer can play a protective role in the isotropic etching process and get final product.
Then, with reference to Fig. 4, carry out S20, utilize the described epitaxial loayer of isotropic etching method etching to form channel region, form the schematic cross-section of structure as shown in figure 11.This step can adopt wet etching, and etching agent is the mixture of HF, HNO3, acetic acid; Also can adopt dry etching, etching agent is SF
6, CF
4Deng.
Adopt the isotropic etching of this step, the existence of the first dielectric layer 21 is arranged due to source region and drain region bottom, thereby, large source region, the defective of drain region substrate can not caused.
Follow again execution in step S21, the first dielectric layer 21 of removal second area II, the 3rd regional III.The first dielectric layer 21 materials are silicon dioxide, and this removal method can adopt HF acid.
Then carry out S25, utilize epitaxy at second area II, the 3rd regional III grown silicon-germanium, form respectively silicon-germanium source region structure 25, silicon-germanium drain structure 26, the schematic cross-section of the structure that forms as shown in figure 12.This epitaxy is for example also molecular beam epitaxy, can adopt technique of the prior art.
Then carry out S26, form the 4th dielectric layer 27 and be polished on described silicon-germanium source region structure 25, drain structure 26 and described the 3rd dielectric layer 24 and expose described the 3rd dielectric layer 24, the schematic cross-section of the structure that forms as shown in figure 13.Described the 4th dielectric layer 27 is different from described the 3rd dielectric layer 24 materials.In the present embodiment, described the 4th dielectric layer 27 materials are silicon nitride.
Then carry out S27, remove described the 3rd dielectric layer 24 to form the second opening 28, the schematic cross-section of the structure that forms as shown in figure 14.The 3rd dielectric layer 24 materials are silicon dioxide, adopt HF acid to remove.
Carry out S28, deposit gate insulator material and grid material are also removed the second outer gate insulator material and grid material of opening 28, to form respectively gate insulator 29 and grid 30, form the structural section schematic diagram as shown in figure 15, described the second opening 28 is filled full.In the present embodiment, described gate insulator 29 materials are silicon dioxide, and described grid 30 materials are polysilicon, and depositing technics can adopt existing technique.
Carry out S29, remove described the 4th dielectric layer 27 on described silicon-germanium source region structure 25, drain structure 26, the schematic cross-section of the structure that forms as shown in figure 16.
Afterwards, with reference to Fig. 4, carry out S30, described silicon-germanium source region structure 25, drain structure 26 are carried out light dope and heavy doping, form respectively light doping section and heavily doped region.This step comprises the following steps S301-S304 in the process of implementation.
At first carry out S301, respectively form a sidewall 31 at the dual-side of described gate insulator 29 and grid 30, shown in Figure 17.This sidewall 31 can avoid the Implantation in the S302 step that grid 30 and gate insulator 29 are impacted.In other embodiments, this step can be omitted.
Then carry out S302, described silicon-germanium source region structure 25, drain structure 26 are carried out light dope, the schematic cross-section of the structure that forms as shown in figure 17; This step plasma is injected to the boron ion.Injecting the degree of depth and concentration sets as required.
Then carry out S303, at the dual-side formation side wall 32 of described gate insulator material and grid material, shown in Figure 18.The step that forms side wall 32 can adopt eat-backs.
Carry out afterwards S304, described silicon-germanium source region structure 25, drain structure 26 are carried out heavy doping.
Through above-mentioned steps, the cross section structure of the MOS device of formation as shown in figure 18, side wall has formed light doping section 32 times, 26 li, remaining described silicon-germanium source region structure 25, drain structure form heavily doped regions.This step plasma is injected to the boron ion.Injecting the degree of depth and concentration sets as required.
In the present embodiment, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all the boron Implantation, such as boron or boron fluoride etc.In other embodiment, the MOS device also can be the N-type device, correspondingly, and Implantation N-type ion.
to sum up, compared with prior art, the method of above-mentioned formation MOS device has the following advantages: at first utilize epitaxy to form the epitaxial loayer that is arranged in channel region, this epitaxial loayer and Semiconductor substrate material and lattice structure are identical, adopt afterwards dielectric layer protection Semiconductor substrate, then utilize this epitaxial loayer of isotropic etching method etching, avoided in prior art self aligned approach etching semiconductor substrate process in source region and drain region respectively the defective that forms with the Semiconductor substrate junction, thereby, the MOS device that forms in use the source region can not occur, drain region leaky in the Semiconductor substrate.
The present invention also provides a kind of MOS device, is formed by the forming method of MOS device of foregoing description.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (16)
1. the formation method of a MOS device, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises Three regions at least, and wherein, the first area is used to form gate regions, and second area, three zone adjacent with the first area are respectively used to form source region and drain region;
Utilize epitaxy that the Semiconductor substrate of described first area is stretched out and grow epitaxial loayer;
Utilize the described epitaxial loayer of isotropic etching method etching to form channel region;
Utilize epitaxy at second area, the 3rd region growing silicon-germanium, form respectively silicon-germanium source region structure, drain structure;
Described silicon-germanium source region structure, drain structure are adulterated.
2. the formation method of MOS device according to claim 1, is characterized in that, described silicon-germanium source region structure, the drain structure step of adulterating is comprised light dope and heavy doping, forms respectively light doping section and heavily doped region.
3. the formation method of MOS device according to claim 1, is characterized in that, utilizes epitaxy to grow the epitaxial loayer step and comprise:
Form successively the first dielectric layer and the second dielectric layer on described Semiconductor substrate, described the first dielectric layer is different from described the second dielectric layer material;
Define area of grid on the second dielectric layer, remove described the first dielectric layer and second dielectric layer of described area of grid, form the first opening;
Utilize the epitaxy described epitaxial loayer of growing in described the first opening, described epitaxial loayer is not filled completely described the first opening;
Deposit the 3rd dielectric layer is also removed the 3rd outer dielectric layer of described the first opening, and described the 3rd dielectric layer is different from described the second dielectric layer material;
Remove second dielectric layer in described second area and the 3rd zone.
4. the formation method of MOS device according to claim 3, it is characterized in that, after utilizing the described epitaxial loayer of isotropic etching method etching to form the channel region step, also remove the first dielectric layer step in second area, the 3rd zone, carry out afterwards the described epitaxy of utilizing at second area, the 3rd region growing silicon-germanium, form respectively the step of silicon-germanium source region structure, drain structure.
5. the formation method of MOS device according to claim 4, it is characterized in that, utilize epitaxy at second area, the 3rd region growing silicon-germanium, after forming respectively silicon-germanium source region structure, drain structure step, described silicon-germanium source region structure, drain structure are adulterated before step, also carry out: form the 4th dielectric layer and be polished on described silicon-germanium source region structure, drain structure and described the 3rd dielectric layer and expose described the 3rd dielectric layer; Described the 4th dielectric layer is different from described the 3rd dielectric layer material;
Remove described the 3rd dielectric layer to form the second opening;
Deposit gate insulator material and grid material to be forming gate insulator and grid layer, and remove the second opening outer gate insulator material and grid material;
Remove described the 4th dielectric layer on described silicon-germanium source region structure, drain structure.
6. the formation method of MOS device according to claim 5, is characterized in that, described silicon-germanium source region structure, the drain structure step of adulterating is comprised:
Described silicon-germanium source region structure, drain structure are carried out light dope;
Dual-side at described gate insulator and grid layer forms side wall;
Described silicon-germanium source region structure, drain structure are carried out heavy doping, make under described side wall and form light doping section, form heavily doped region in remaining described silicon-germanium source region structure, drain structure.
7. the formation method of MOS device according to claim 6, it is characterized in that, after removing described the 4th dielectric layer step on described silicon-germanium source region structure, drain structure, before described silicon-germanium source region structure, drain structure are carried out light dope, also carry out forming the sidewall step at the dual-side of described gate insulator and grid layer.
8. the formation method of MOS device according to claim 2, is characterized in that, described MOS device is P type MOS device, in described light dope and described heavy doping step, is all P type Implantation.
9. the formation method of MOS device according to claim 5, it is characterized in that, described the first dielectric layer material is silicon dioxide, described the second dielectric layer material is silicon nitride, described the 3rd dielectric layer material is also silicon dioxide, described the 4th dielectric layer material is silicon nitride, utilizes phosphoric acid to carry out the step of the second dielectric layer in second area, the 3rd zone on the described area of grid of described removal both sides.
10. the formation method of MOS device according to claim 9, is characterized in that, utilizes HF acid to carry out the step of first dielectric layer in described removal second area, the 3rd zone.
11. the formation method of according to claim 9 or 10 described MOS devices is characterized in that, utilizes HF acid to carry out described the 3rd dielectric layer of described removal to form the step of the second opening.
12. the formation method of MOS device according to claim 11 is characterized in that, utilizes phosphoric acid to carry out the step of described the 4th dielectric layer on the described silicon of described removal-germanium source region structure, drain structure.
13. the formation method of MOS device according to claim 5 is characterized in that, described gate insulator material is silicon dioxide, and described grid material is polysilicon.
14. the formation method of MOS device according to claim 1 is characterized in that, utilizes the described epitaxial loayer of isotropic etching method etching to form in the channel region step, described isotropic etching method etching adopts wet etching, and etching agent is HF, HNO
3, acetic acid mixture.
15. the formation method of MOS device according to claim 1 is characterized in that, utilizes the described epitaxial loayer of isotropic etching method etching to form in the channel region step, described isotropic etching method etching adopts dry etching, and etching agent is SF
6Or CF
4
16. a MOS device is characterized in that, forms according to the formation method of the described MOS device of above-mentioned arbitrary claim.
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| JPH11163324A (en) * | 1997-11-26 | 1999-06-18 | Nec Corp | Manufacture of semiconductor device |
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| CN1787230A (en) * | 2004-12-08 | 2006-06-14 | 株式会社东芝 | Semiconductor device including field-effect transistor |
| US20110068396A1 (en) * | 2009-09-24 | 2011-03-24 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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2011
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11163324A (en) * | 1997-11-26 | 1999-06-18 | Nec Corp | Manufacture of semiconductor device |
| CN1543679A (en) * | 2002-07-12 | 2004-11-03 | ض� | Process for ultra-thin body soi devices that incorporate epi silicon tips and article made thereby |
| CN1787230A (en) * | 2004-12-08 | 2006-06-14 | 株式会社东芝 | Semiconductor device including field-effect transistor |
| US20110068396A1 (en) * | 2009-09-24 | 2011-03-24 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS |
| CN102104067A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Transistor epitaxially growing source/drain region and manufacturing method thereof |
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