CN103137461A - Forming method and device of high gate K dielectric layer and forming method of transistor - Google Patents
Forming method and device of high gate K dielectric layer and forming method of transistor Download PDFInfo
- Publication number
- CN103137461A CN103137461A CN201110398208XA CN201110398208A CN103137461A CN 103137461 A CN103137461 A CN 103137461A CN 201110398208X A CN201110398208X A CN 201110398208XA CN 201110398208 A CN201110398208 A CN 201110398208A CN 103137461 A CN103137461 A CN 103137461A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- gate dielectric
- reaction chamber
- metal
- metal level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a forming method of a high gate K dielectric layer. The forming method of the high gate K dielectric layer comprises that a semiconductor substrate which is provided, an insulating layer which is located on a surface of the semiconductor substrate and an open mouth which penetrates through the thickness of the insulating layer. A chemical vapor deposition process which is used for reducing metal chloride can be used, and a metal layer is formed at the bottom of the open mouth. The metal layer can be oxidized to form the high gate K dielectric layer. The invention further provides a forming method of a transistor. The high gate K dielectric layer which is used for forming transistors is mainly formed at the bottom of the open mouth. The number of the transistors is smaller, wherein the transistors are form in the side walls of the open mouth. A stray capacitance of each transistor is small in capacity and good in performance. Correspondingly, the invention further provides a forming device of the high gate K dielectric layer. The forming device of the high gate K dielectric layer is simple in structure and principle, and the forming device of the high gate K dielectric layer can be utilized to improve production efficiency.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of high-K gate dielectric layer and form device, transistorized formation method.
Background technology
Along with transistorized characteristic size is more and more less, the corresponding shared area of core devices is corresponding reducing also, causes the energy density of unit are significantly to increase, and the electric leakage problem highlights more, and power consumption also increases thereupon.Therefore in low process node, the technique of traditional gate dielectric layer take silicon dioxide as material has run into bottleneck, can't satisfy transistorized technological requirement.For solving above-mentioned bottleneck, adopt at present high-k (high k:k value is more than or equal to 10) dielectric material as gate dielectric layer, then, the grid of formation take metal as material is well controlled power consumption to reduce electric leakage.
The formation method of the high-K gate dielectric layer of prior art comprises:
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surfaces are formed with pseudo-gate dielectric layer 101, described pseudo-gate dielectric layer 101 surfaces form pseudo-gate electrode layer 103, described pseudo-gate electrode layer 103 surfaces are formed with photoresist layer 105, and described photoresist layer 105 has the figure that defines high-K gate dielectric layer;
Please refer to Fig. 2, described pseudo-gate electrode layer 103 and pseudo-gate dielectric layer 101, then remove described photoresist layer take described photoresist layer as mask etching;
Please refer to Fig. 3, form to cover described Semiconductor substrate 100 and with the insulating barrier 107 of described pseudo-gate electrode layer 103 flush;
Please refer to Fig. 4, remove described pseudo-gate electrode layer 103 and pseudo-gate dielectric layer 101, form opening 108;
Please refer to Fig. 5, adopt physical gas-phase deposition to form the bottom of the described opening of covering and the high-K gate dielectric layer 109 of sidewall; Fill full metal gate electrode layer 111 in described opening.
Yet, adopt prior art to form the method for high-K gate dielectric layer, the transistorized parasitic capacitance of formation is larger, has affected transistorized performance.
More formation methods about high-K gate dielectric layer please refer to publication number and are the United States Patent (USP) of " US20040266120A1 ".
Summary of the invention
The problem that the present invention solves is to provide the formation method of the little high-K gate dielectric layer of a kind of parasitic capacitance and forms device, transistorized formation method.
For addressing the above problem, embodiments of the invention provide a kind of formation method of high-K gate dielectric layer, comprising:
Provide Semiconductor substrate, the opening that is positioned at the insulating barrier of described semiconductor substrate surface and runs through the thickness of described insulating barrier;
Adopt the muriatic chemical vapor deposition method in reducing metal, form metal level in the bottom of described opening;
The described metal level of oxidation forms high-K gate dielectric layer.
Alternatively, the muriatic chemical vapor deposition method in described employing reducing metal, the step that forms metal level in the bottom of described opening comprises: metallic plate is provided, places described metallic plate in the opening top; The chlorine of plasma state and described metallic plate react, and form the metal chloride of gaseous state; Metal in the metal chloride of described gaseous state combines with silicon in the Semiconductor substrate of open bottom, forms metal silicide layer; The metal chloride of described gaseous state and the reaction of described metal silicide layer form metal level in described open bottom.
Alternatively, the material of described metallic plate is hafnium, lanthanum, zirconium, tantalum, titanium or aluminium.
Alternatively, also comprise: the chlorine plasma is changed into plasma state.
Alternatively, the technological parameter of the chlorine of the described plasma state of formation comprises: frequency is 2-4MHz; Power is 200-500W; Pressure is 0.01-0.1Torr; Cl
2Flow be 500-2000sccm.
Alternatively, also comprise: pass into inert gas as the carrier of the chlorine of plasma state.
Alternatively, described inert gas is Ar, He or N
2
Alternatively, the flow of described inert gas is 500-3000sccm.
Alternatively, the technological parameter of the described metal level of formation comprises: temperature is 250-350 ℃; Pressure is 0.01-0.1Torr.
Alternatively, also comprise repeatedly following steps: adopt the muriatic chemical vapor deposition method in reducing metal, form metal level in the bottom of described opening; The described metal level of oxidation forms high-K gate dielectric layer.Alternatively, the thickness that at every turn forms metal level in the bottom of described opening less than
The gas that passes into when alternatively, the described metal level of oxidation forms high-K gate dielectric layer is the oxygen of ozone or plasma state.
Alternatively, the technological parameter of the described metal level formation of oxidation high-K gate dielectric layer comprises: the flow of ozone is 500-2000sccm; Pressure is 0.01-0.1Torr.
Alternatively, also comprise: after metal level is formed on the bottom at described opening, described metal level is carried out purified treatment, reoxidize described metal level.
Alternatively, the method for described purified treatment comprises: pass into inert gas to described layer on surface of metal.
Alternatively, described inert gas is Ar, He or N
2The flow of described inert gas is 500-3000sccm.
Accordingly, the inventor provides a kind of transistorized formation method, comprising:
Provide Semiconductor substrate, the opening that described semiconductor substrate surface is formed with insulating barrier and runs through the thickness of described insulating barrier;
Adopt the muriatic chemical vapor deposition method in reducing metal, form metal level in the bottom of described opening;
The described metal level of oxidation forms high-K gate dielectric layer;
Form the metal gate electrode layer that covers described high-K gate dielectric layer.
Alternatively, also comprise: remove described insulating barrier, expose described semiconductor substrate surface; Formation is positioned at described metal gate electrode layer sidewall and is positioned at the side wall of described semiconductor substrate surface; Take described side wall as mask, formation source/drain electrode in described Semiconductor substrate.
Accordingly, the embodiment of the present invention also provides a kind of formation device of high-K gate dielectric layer, comprising:
The first reaction chamber is used for adopting the muriatic chemical vapor deposition method in reducing metal, at the opening part of wafer high-K gate dielectric layer to be formed, forms metal level;
The second reaction chamber, adjacent with described the first reaction chamber, be used for the described metal level of oxidation and form high-K gate dielectric layer;
Clean unit between the first reaction chamber and the second reaction chamber, is used for removing the impurity of crystal column surface;
Whirligig, comprise rotating shaft and at least one turning arm that is connected with described rotating shaft, the first reaction chamber, the second reaction chamber, clean unit are positioned at described rotating shaft as central point, on the circumference of turning arm as radius, described turning arm transports wafer in the first reaction chamber, clean unit or the second reaction chamber by the rotation of rotating shaft.
Alternatively, described the first reaction chamber comprises: the first base station, for the wafer of placing high-K gate dielectric layer to be formed; Be positioned at the clamping device of described the first base station top, be used for the clamping metallic plate.
Alternatively, described the second reaction chamber comprises: the second base station is used for placing the wafer that is formed with metal level; Be positioned at the gas tip of described the second base station top, have some apertures in described gas tip, be used for the passage when passing into ozone or oxonium ion.
Alternatively, also comprise: source coil, be used for receiving the electric power from power supply, produce uniform plasma; Plasma cavity is used for the uniform plasma that the reception sources coil produces, and will pass into the first reaction chamber or the second reaction chamber after gaseous plasma.
Alternatively, the number of described turning arm equals the number sum of the first reaction chamber and the second reaction chamber.
Alternatively, when the number of described the first reaction chamber and described the second reaction chamber is at least two, the arrangement that described the first reaction chamber and the second reaction chamber replace.
Alternatively, the distance between adjacent two the first reaction chambers, the second reaction chamber equates.
Compared with prior art, embodiments of the invention have the following advantages:
adopt the muriatic chemical vapor deposition method in reducing metal, when metal level is formed on the bottom of opening, the chlorine of plasma state and the metal in metallic plate react, form the metal chloride of gaseous state, due to the metal chloride of described gaseous state mainly in the enrichment of the bottom of opening, the metal level that forms mainly is positioned at the bottom of opening, and the metal of the side wall deposition of opening is few, the follow-up oxidized rear formation high-K gate dielectric layer of described metal level, described high-K gate dielectric layer also mainly is formed on the bottom of opening, the high-K gate dielectric material of opening sidewalls is few, and the formation technique of high-K gate dielectric layer is simple.
Further, adopt the muriatic chemical vapor deposition method in reducing metal and oxidation technology, the high-K gate dielectric layer of formation mainly is formed on the bottom of opening, and it is less that opening sidewalls forms, and transistorized parasitic capacitance is little, and performance is good.
Further, after metal level is formed on the bottom of described opening, before the described metal level of oxidation, described metal level is carried out the step of purified treatment.This step has been removed the impurity that is attached to layer on surface of metal, makes the high-K gate dielectric layer of formation comparatively pure, and quality is good, has further ensured the quality of high-K gate dielectric layer, has improved transistorized performance.
The formation device of high-K gate dielectric layer comprises the whirligig with rotating shaft and at least one turning arm that is connected with described rotating shaft, the first reaction chamber, the second reaction chamber, clean unit are positioned at described rotating shaft as central point, on the circumference of rotating shaft as radius; By the rotation of rotating shaft in described whirligig, the rotation of driven rotary arm makes it that wafer is transported in the first reaction chamber, the second reaction chamber or clean unit, principle and simple in structure, and automaticity is high.
Further, comprise a plurality of the first reaction chambers that are arranged alternately and the second reaction chamber, and described a plurality of the first reaction chamber that is arranged alternately and the second reaction chamber surround into circle, the rotating shaft of whirligig is positioned at the center of circle of described circle, compact conformation not only, can also the while form metal level in the bottom of the opening of a plurality of wafers high-K gate dielectric layer to be formed, be beneficial to and realize the production line manufacturing, improve production efficiency.
Description of drawings
Fig. 1-Fig. 5 is the cross-sectional view of forming process of the high-K gate dielectric layer of prior art;
Fig. 6 is the schematic flow sheet of formation method of the high-K gate dielectric layer of the embodiment of the present invention;
Fig. 7-Figure 11 is the cross-sectional view of forming process of the high-K gate dielectric layer of first embodiment of the invention;
Figure 12-Figure 13 is the cross-sectional view of the transistorized forming process of second embodiment of the invention;
Figure 14 is the cross-sectional view of formation device of the high-K gate dielectric layer of the embodiment of the present invention;
Figure 15 is the plan structure schematic diagram of formation device of the high-K gate dielectric layer of the embodiment of the present invention.
Embodiment
Just as stated in the Background Art, adopt prior art to form the method for high-K gate dielectric layer, the transistorized parasitic capacitance of formation is larger, transistorized poor-performing.
Through research, the inventor finds, please continue with reference to figure 5, when prior art adopts physical gas-phase deposition to form the high-K gate dielectric layer 109 of the bottom that covers described opening, sidewall at opening has formed high-K gate dielectric layer 109 simultaneously, be mainly that the described high-K gate dielectric layer 109 that is positioned at opening sidewalls has caused transistorized parasitic capacitance to increase, affected transistorized performance.
After further research, the inventor finds a kind of selectivity depositing operation, the deposit major sedimentary is in the bottom of opening, and the sidewall of opening form less, if described selectivity depositing operation is applied in the formation method of high-K gate dielectric layer, can effectively reduce the transistorized parasitic capacitance of formation, improve transistorized performance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
The first embodiment
Please refer to Fig. 6, the formation method of the high-K gate dielectric layer of the embodiment of the present invention comprises:
Step S201 provides Semiconductor substrate, the opening that described semiconductor substrate surface is formed with insulating barrier and runs through the thickness of described insulating barrier;
Step S203 adopts the muriatic chemical vapor deposition method in reducing metal, forms metal level in the bottom of described opening;
Step S205, the described metal level of oxidation forms high-K gate dielectric layer.
Specifically please refer to Fig. 7-Figure 11, Fig. 7-Figure 11 shows the cross-sectional view of forming process of the high-K gate dielectric layer of first embodiment of the invention.
Please refer to Fig. 7, Semiconductor substrate 300 is provided, the opening 308 that described Semiconductor substrate 300 surfaces are formed with insulating barrier 307 and run through the thickness of described insulating barrier 307.
Described Semiconductor substrate 300 is used to subsequent technique that platform is provided, and the material of described Semiconductor substrate 300 is monocrystalline silicon.
Described insulating barrier 307 is used for isolating adjacent metal gates.The material of described insulating barrier 307 is SiO
2, the formation technique of described insulating barrier 307 is oxidation or depositing operation, because the technique that forms insulating barrier 307 is well known to those skilled in the art, does not repeat them here.
Described opening 308 defines the position of high-K gate dielectric layer, is used for follow-up formation high-K gate dielectric layer.In an embodiment of the present invention, the formation step of described opening 308 please refer to the description of Fig. 1-Fig. 4 in background technology, does not repeat them here.
Need to prove, not damaged when forming opening 308 in order to protect described Semiconductor substrate 300 in other embodiments of the invention, described Semiconductor substrate 300 surfaces also are formed with etching barrier layer (not shown).
Please refer to Fig. 8, adopt the muriatic chemical vapor deposition method in reducing metal, form the first metal layer 3091 in the bottom of described opening 308.
The inventor finds, when in Fig. 5, prior art adopts physical gas-phase deposition to form the high-K gate dielectric layer 109 of the bottom that covers described opening, sidewall at opening has formed high-K gate dielectric layer 109 simultaneously, be mainly that the described high-K gate dielectric layer 109 that is positioned at opening sidewalls has caused transistorized parasitic capacitance to increase, affected transistorized performance.
After further research, the inventor finds, when adopting the muriatic chemical vapor deposition method in reducing metal to form deposit in opening, due to the metal chloride of gaseous state in the open bottom enrichment, and the metal chloride at opening sidewalls place is rare than the bottom, described deposit major sedimentary is in the bottom of opening, and the sidewall of opening form less, if described selectivity depositing operation is applied in the formation method of high-K gate dielectric layer, can effectively reduce the transistorized parasitic capacitance of formation, improve transistorized performance.
Therefore, in an embodiment of the present invention, adopt the muriatic chemical vapor deposition method in reducing metal, form the first metal layer 3091 in the bottom of described opening 308.
The muriatic chemical vapor deposition method in described employing reducing metal, the step that forms the first metal layer 3091 in the bottom of described opening 308 comprises: metallic plate (not shown) is provided, and described metallic plate is positioned over opening 308 tops; The chlorine of plasma state and described metallic plate react, and form the metal chloride of gaseous state; The metal chloride of described gaseous state is in opening 308 bottom enrichments, and the silicon in the Semiconductor substrate 300 of the metal in the metal chloride of described gaseous state and opening 308 bottoms combines, and forms metal silicide layer (not shown); The metal chloride of described gaseous state and the reaction of described metal silicide layer are at described opening 308 bottoms formation the first metal layers 3091.
Please refer to Figure 14, the muriatic chemical vapor deposition method in described reducing metal is carried out in muriatic the first reaction chamber 410 in reducing metal, muriatic the first reaction chamber 410 in described reducing metal comprises: the first base station 401, for the wafer 403 of placing high-K gate dielectric layer to be formed; Be positioned at the clamping device (not shown) of described the first base station 401 tops, be used for clamping metallic plate 405.
Please in conjunction with reference to figure 8 and Figure 14, described metallic plate 405 is used for as the source material that forms the first metal layer 3091, because the rear extended meeting of described the first metal layer 3091 is oxidized to the first high-K gate dielectric film, therefore should to select the oxide of its metal be the material of high K dielectric to described metallic plate 405, for example hafnium (Hf), lanthanum (La), zirconium (Zr), tantalum (Ta), titanium (Ti) or aluminium (Al).In an embodiment of the present invention, the material of described metallic plate 405 is hafnium (Hf).For the ease of at the interior formation the first metal layer 3091 of described opening 308, described metallic plate 405 is placed on the top of described opening 308, directly over being preferably.And the size of described metallic plate 405 is greater than the size of described opening 308.
Need to prove, usually wafer (Semiconductor substrate) surface has a plurality of openings 308, in order to form several metal gates, the area of the described opening that the size of described metallic plate 405 can have according to crystal column surface is decided, and perhaps selects the metallic plate 405 of suitable dimension according to the size of wafer.
Please continue with reference to Figure 14, the chlorine of described plasma state is in the interior formation of plasma cavity 407, described plasma cavity 407 is connected with source coil 408, the electric power that described source coil 408 receives from power supply, produce uniform plasma, the uniform plasma that described plasma cavity 407 reception sources coils 408 produce, plasma chlorine makes it become plasma state.For making the structure that forms device compacter, in embodiments of the invention, described source coil 408 is arranged on the surface of the first reaction chamber 410 roofs.The technological parameter that forms the chlorine of described plasma state comprises: frequency is 2-4MHz; Power is 200-500W; Pressure is 0.01-0.1Torr; Cl
2Flow be 500-2000sccm.
The inventor finds, although when adopting the muriatic chemical vapor deposition method in reducing metal to form the first metal layer 3091, described the first metal layer 3091 major sedimentary are in the bottom of opening 308, and less in the side wall deposition of opening 308, but, suitable technological parameter also can make the metal level more concentrated bottom that is formed on opening 308, and the metal that is formed on opening 308 sidewalls is few, is beneficial to the little transistor of follow-up formation parasitic capacitance.In embodiments of the invention, the technological parameter that the chlorine of plasma state and described metallic plate react comprises: temperature is 250-350 ℃; Pressure is 0.01-0.1Torr.
The inventor finds, it is slower that the chlorine of described plasma state enters the speed of the first reaction chamber 410, the speed that enters the first reaction chamber 410 in order to accelerate it, when passing into the chlorine of described plasma state to described the first reaction chamber 410, also comprise: pass into inert gas as the carrier of the chlorine of plasma state.Described inert gas is Ar, He or N
2In an embodiment of the present invention, the flow of described inert gas is 500-3000sccm.
In one embodiment of the invention, the muriatic chemical vapor deposition method in described employing reducing metal, the step that forms the first metal layer 3091 in the bottom of described opening 308 comprises: chlorine by plasma, forms the chlorine of plasma state in plasma cavity 407; The chlorine of described plasma state is by Ar, He or N as carrier
2Bring in the first reaction chamber 410; At first the chlorine of described plasma state react with metallic plate 405, forms the hafnium chloride (HfCl) of gaseous state; The pasc reaction of the hafnium chloride of described gaseous state and opening 308 bottoms forms hafnium suicide (HfSi) film (not shown) in the bottom of described opening 308; The hafnium chloride of described gaseous state continues and described hafnium suicide (HfSi) film reacts, and forms the first metal layer 3091 in the bottom of described opening 308.
Consider if the thickness of described the first metal layer 3091 is too large, during the described the first metal layer 3091 of subsequent oxidation, only with the part metals oxidation on the first metal layer 3091 surfaces, still can't oxidation away from the metal on described the first metal layer 3091 surfaces, the poor quality of the high-K gate dielectric layer of follow-up formation affects transistorized performance.Through research, the inventor finds, when the thickness of described the first metal layer 3091 less than
The time, the metal in follow-up whole the first metal layer 3091 all can be oxidized, and the quality of the high-K gate dielectric layer of formation is good, and transistorized performance is good.Therefore, in an embodiment of the present invention, the thickness of the first metal layer 3091 less than
Please refer to Fig. 9, the described the first metal layer of oxidation forms the first high-K gate dielectric film 3111.
Described the first high-K gate dielectric film 3111 is used for follow-up formation high-K gate dielectric layer.Described the first high-K gate dielectric film 3111 is metal oxide, and in embodiments of the invention, the material of described the first high-K gate dielectric film 3111 is hafnium oxide (HfO).
The gas that the described metal level of oxidation passes into when forming the first high-K gate dielectric film 3111 is ozone (O
3) or the oxygen of plasma state.In an embodiment of the present invention, the technological parameter of the described the first metal layer formation of oxidation the first high-K gate dielectric film comprises: the flow of ozone is 500-2000sccm; Pressure is 0.01-0.1Torr.
Need to prove, for the quality of the first high-K gate dielectric film 3111 of making formation good, the formation method of high-K gate dielectric layer of the present invention, also comprise: after the first metal layer is formed on the bottom of described opening 308, before the described the first metal layer of oxidation forms the first high-K gate dielectric film 3111, described the first metal layer is carried out purified treatment.
The method of described purified treatment comprises: pass into inert gas to described layer on surface of metal, for example Ar, He or N
2In embodiments of the invention, when the flow of described inert gas is 500-3000sccm, can be with the Impurity removal on described the first metal layer surface.
Need to prove, in actual process, the thickness of transistorized high-K gate dielectric layer has specific requirement, usually greater than
In order to form the high-K gate dielectric layer that satisfies process requirements, need to repeat repeatedly usually that " the muriatic chemical vapor deposition method in reducing metal forms metal level in the bottom of described opening; The described metal level of oxidation " step, form the high-K gate dielectric layer comprise a plurality of high-K gate dielectric films, the thickness of the final described high-K gate dielectric layer that forms equals the thickness sum of described a plurality of high-K gate dielectric films.
Please refer to Figure 10, continue to adopt the muriatic chemical vapor deposition method in reducing metal, namely form the second metal level 3092 in the surface of the first high-K gate dielectric film 3111 in the bottom of described opening.
Described the second metal level 3092 is used for follow-up formation the second high-K gate dielectric film.The thickness of described the second metal level 3092 less than
The formation method of described the second metal level 3092 and step can with reference to formation method and the step of the first metal layer of the embodiment of the present invention, not repeat them here.
Need to prove, in an embodiment of the present invention, after forming the second metal level 3092, in clean unit, described the second metal level 3092 is carried out purified treatment, remove its surperficial impurity, be beneficial to measured the second high-K gate dielectric film of follow-up formation matter.Specifically please refer to the method for the impurity of removing the first metal layer surface.
Please refer to Figure 11, described the second metal level of oxidation forms the second high-K gate dielectric film 3112.
Described the second high-K gate dielectric film 3112 is used for and the common formation high-K gate dielectric layer of the first high-K gate dielectric film 3111.
The formation method of described the second high-K gate dielectric film 3112 and step please refer to formation method and the step of the first high-K gate dielectric film 3111, do not repeat them here.
Need to prove, when the thickness sum of a plurality of high-K gate dielectric films that form equals the thickness of the final high-K gate dielectric layer that need to form in embodiments of the invention, the manufacturing of high-K gate dielectric layer is completed, the bottom of the opening that the high-K gate dielectric layer that forms mainly forms, the high-K gate dielectric layer of opening both sides is less.
Accordingly, the inventor of the embodiment of the present invention provides a kind of formation device of high-K gate dielectric layer through after studying, and please refer to Figure 14, comprising:
The first reaction chamber 410 is used for adopting the muriatic chemical vapor deposition method in reducing metal, and metal level (not shown) is formed on opening (not shown) bottom at wafer 403 high-K gate dielectric layers to be formed;
The second reaction chamber 420, adjacent with described the first reaction chamber, be used for the described metal level of oxidation and form high-K gate dielectric layer (not shown);
Clean unit (not shown) above zone between the first reaction chamber 410 and the second reaction chamber 420, is used for being transported to the second reaction chamber 420 at wafer 403 by the first reaction chamber 410 and removes the impurity on wafer 403 surfaces on the way;
Wherein, described the first reaction chamber 410 comprises: the first base station 401, for the first wafer 403 of placing high-K gate dielectric layer to be formed; Be positioned at the clamping device (not shown) of described the first base station 401 tops, be used for clamping metallic plate 405.
Described the second reaction chamber 420 comprises: the second base station 409 is used for placing the second wafer 411 that has been formed with metal level (for example the first metal layer or the second metal level); Be positioned at the gas tip 413 of described the second base station 409 tops, have some apertures (not shown) in described gas tip 413, passage when passing into gas for conduct, and the ozone or the oxonium ion that pass in the present embodiment are dispersed in the second reaction chamber 420, help to react uniformly with the metal level on the second wafer 411 surfaces, form the measured high-K gate dielectric layer of matter.
Described clean unit is used for described metal level is carried out purified treatment.Described clean unit carries out purified treatment by passing into the mode of inert gas to the wafer in clean unit.
Need to prove, the formation device of the embodiment of the present invention also comprises: source coil 408, be used for receiving the electric power from power supply, and produce uniform plasma; Plasma cavity 407 is connected with the first reaction chamber 410, is used for the uniform plasma that reception sources coil 408 produces, with gaseous plasma.In an embodiment of the present invention, described source coil 408 is arranged on the surface of the first reaction chamber 410 roofs, and described plasma cavity 407 is used for plasma chlorine, makes it become plasma state, and the chlorine that transports plasma state arrives metal sheet surface.
Need to prove, in other embodiments of the invention, described plasma cavity 407 also can be integrated in the inside of the first reaction chamber 410.And described the second reaction chamber 420 inside also can integrated another plasma cavity; Another plasma cavity perhaps is set is connected with described the second reaction chamber 420, plasma oxygen makes it become oxonium ion, is beneficial to form high-K gate dielectric layer.
Consider when forming the thickness of the high-K gate dielectric layer that finally needs, usually need to form several times described metal level, after the described metal level of each formation, the metal level of this time of oxidation formation forms high-K gate dielectric layer, and then form next metal level, until till can form the thickness of high-K gate dielectric layer of final needs the time.The inventor finds, when if the number of described the first reaction chamber, the second reaction chamber and clean unit is one, the wafer of high-K gate dielectric layer to be formed need to move in described the first reaction chamber, the second reaction chamber and clean unit repeatedly, be unfavorable for forming production line in factory, production efficiency is low.
The inventor finds, if arrange described the first reaction chamber, the second reaction chamber and the clean unit of suitable quantity in the formation device of described high-K gate dielectric layer, can form production line in factory, greatly improves transistorized production efficiency.
In the embodiment of the present invention, the inventor provides a kind of formation device of high-K gate dielectric layer, comprise: at least two the first reaction chambers and at least two the second reaction chambers, the arrangement that described the first reaction chamber and the second reaction chamber replace, be provided with clean unit between each described first reaction chamber and the second reaction chamber, be used for wafer from a reaction chamber before next reaction chamber, remove the impurity of described crystal column surface.
Described turning arm also can have a plurality of, and a plurality of described turning arms all are fixedly connected on rotating shaft, rotate with the rotation of rotating shaft.
In an embodiment of the present invention, the number of described turning arm equals the number sum of the first reaction chamber and the second reaction chamber, and the length of described turning arm and height are as the criterion with the center that the wafer that transports just arrives the base station of each reaction chamber.Therefore, each reative cell can be worked simultaneously, and efficient is high, is beneficial to the formation production line.
Please refer to Figure 15, in embodiments of the invention, carry out exemplary illustrated as example when being three take the number of described the first reaction chamber and the second reaction chamber.
In the embodiment of the present invention, described the first reaction chamber 4101, the second reaction chamber 4201, the first reaction chamber 4102, the second reaction chamber 4202, the first reaction chamber 4103 and the second reaction chamber 4203 are arranged centered by described whirligig 415 successively clockwise or counterclockwise, and the distance between adjacent two reaction chambers is equal, and namely adjacent two reaction chambers equate with the angle that the center of described circle consists of; Described whirligig 415 comprise rotary body and with described a plurality of the first reaction chambers and a plurality of the second reaction chamber turning arm one to one, the number of described turning arm is 6, the angle between two adjacent turning arms equates; And be provided with clean unit 430 between each described first reaction chamber and the second reaction chamber, the number of described clean unit 430 is 6.
The course of work of the formation device with a plurality of the first reaction chambers and second reaction chamber shown in Figure 15 is: the first wafer of high-K gate dielectric layer to be formed is transported to by turning arm 415 on first base station (not shown) of the first reaction chamber 4101 chambers, at the open bottom formation the first metal layer of the first crystal column surface high-K gate dielectric layer to be formed; The turning arm of whirligig 415 transports described the first wafer in clean unit 430 between the first reaction chamber 4101 and the second reaction chamber 4201, and purified treatment is carried out on the first metal layer surface of described the first wafer; The first wafer after with purified treatment is transported on second base station (not shown) of the second reaction chamber 4201 by the turning arm of described whirligig 415 again, and the described the first metal layer of oxidation forms the first high-K gate dielectric layer; The turning arm of described whirligig 415 is transported to described the first wafer in clean unit 430 between the second reaction chamber 4201 and the first reaction chamber 4102, and purified treatment is carried out on the first high-K gate dielectric layer surface of described the first wafer; Described the first wafer is transported on the first base station of the first reaction chamber 4102 by the turning arm of whirligig 415 more afterwards, form the second metal level that covers described the first high-K gate dielectric layer, the like, until oxidation the 3rd metal level forms third high K gate dielectric layer in the second reaction chamber 4203.
Need to prove, when the first wafer is transported to the second reaction chamber 4201, can the second wafer be transported in the first reaction chamber 4101 by another turning arm in whirligig 415, begin the formation step of the high-K gate dielectric layer of described the second crystal column surface.Accordingly, can transport simultaneously six wafers on six turning arms of described whirligig 415 in first reaction chamber or the second reaction chamber of correspondence, to form production line.
Need to prove, in other embodiments of the invention, can be according to the thickness of the high-K gate dielectric layer of final formation, and every thickness through the high-K gate dielectric layer that forms after first reaction chamber and the second reaction chamber, determine the number of the first reaction chamber and the second reaction chamber and the number of clean unit, and with the circle that is arranged at described a plurality of the first reaction chambers, the second reaction chamber and clean unit interval, make the thickness of the high-K gate dielectric layer of the wafer that transports out from last the second reaction chamber just reach requirement.
As the above analysis, the principle of described formation device with a plurality of the first reaction chambers and second reaction chamber is simple, and compact conformation can be realized higher production efficiency.
The second embodiment
Specifically please refer to Figure 12-Figure 13, Figure 12-Figure 13 shows the cross-sectional view of the transistorized forming process of first embodiment of the invention.
Please refer to Figure 12, the inventor of the embodiment of the present invention provides a kind of transistorized formation method, comprising:
Provide Semiconductor substrate 500, the opening (not shown) that described Semiconductor substrate 500 surfaces are formed with insulating barrier 60 and run through the thickness of described insulating barrier 60;
Adopt the muriatic chemical vapor deposition method in reducing metal, form metal level (not shown) in the bottom of described opening;
The described metal level of oxidation forms high-K gate dielectric layer 501;
Form the metal gate electrode layer 503 that covers described high-K gate dielectric layer 501.
Concrete formation method and the step of described high-K gate dielectric layer 501 please refer to formation method and the step of the high-K gate dielectric layer of first embodiment of the invention, do not repeat them here.
Described metal gate electrode layer 503 is used to form transistorized grid, and the formation technique of described metal gate electrode layer 503 is physics or chemical vapor deposition method, does not repeat them here.
Please refer to Figure 13, described transistorized formation method also comprises: remove described insulating barrier, expose described Semiconductor substrate 500 surfaces; Formation is positioned at described metal gate electrode layer 503 sidewalls and is positioned at the side wall 505 on described Semiconductor substrate 500 surfaces; Take described side wall 505 as mask, in the interior formation of described Semiconductor substrate 500 source/drain electrode 507.
Wherein, the technique of removing described insulating barrier is etching technics, for example dry method or wet etching; The material of described side wall 505 is SiN, forms source/drain electrode 507 for follow-up as mask, and the formation technique of described side wall 505 is depositing operation and etching technics; The mode of doping is adopted in described source/drain electrode 507, and for example Implantation forms.
After above-mentioned steps is completed, the transistorized of high-K gate dielectric layer that have that second embodiment of the invention forms completes, and in described transistor, high-K gate dielectric layer mainly is formed on the bottom of opening, and it is less that opening sidewalls forms, transistorized parasitic capacitance is little, and performance is good.
to sum up, adopt the muriatic chemical vapor deposition method in reducing metal, when metal level is formed on the bottom of opening, the chlorine of plasma state and the metal in metallic plate react, form the metal chloride of gaseous state, due to the metal chloride of described gaseous state mainly in the enrichment of the bottom of opening, the metal level that forms mainly is positioned at the bottom of opening, and the metal of the side wall deposition of opening is few, the follow-up oxidized rear formation high-K gate dielectric layer of described metal level, described high-K gate dielectric layer also mainly is formed on the bottom of opening, the high-K gate dielectric material of opening sidewalls is few, and the formation technique of high-K gate dielectric layer is simple.
Further, adopt the muriatic chemical vapor deposition method in reducing metal and oxidation technology, the high-K gate dielectric layer of formation mainly is formed on the bottom of opening, and it is less that opening sidewalls forms, and transistorized parasitic capacitance is little, and performance is good.
Further, after metal level is formed on the bottom of described opening, before the described metal level of oxidation, described metal level is carried out the step of purified treatment.This step has been removed the impurity that is attached to layer on surface of metal, makes the high-K gate dielectric layer of formation comparatively pure, and quality is good, has further ensured the quality of high-K gate dielectric layer, has improved transistorized performance.
The formation device of high-K gate dielectric layer comprises the whirligig with rotating shaft and at least one turning arm that is connected with described rotating shaft, the first reaction chamber, the second reaction chamber, clean unit are positioned at described rotating shaft as central point, on the circumference of rotating shaft as radius; By the rotation of rotating shaft in described whirligig, the rotation of driven rotary arm makes it that wafer is transported in the first reaction chamber, the second reaction chamber or clean unit, principle and simple in structure, and automaticity is high.
Further, comprise a plurality of the first reaction chambers that are arranged alternately and the second reaction chamber, and described a plurality of the first reaction chamber that is arranged alternately and the second reaction chamber surround into circle, the rotating shaft of whirligig is positioned at the center of circle of described circle, compact conformation not only, can also the while form metal level in the bottom of the opening of a plurality of wafers high-K gate dielectric layer to be formed, be beneficial to and realize the production line manufacturing, improve production efficiency.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (22)
1. the formation method of a high-K gate dielectric layer comprises:
Provide Semiconductor substrate, the opening that described semiconductor substrate surface is formed with insulating barrier and runs through the thickness of described insulating barrier;
It is characterized in that, also comprise:
Adopt the muriatic chemical vapor deposition method in reducing metal, form metal level in the bottom of described opening;
The described metal level of oxidation forms high-K gate dielectric layer.
2. the formation method of high-K gate dielectric layer as claimed in claim 1, it is characterized in that, the muriatic chemical vapor deposition method in described employing reducing metal, the step that forms metal level in the bottom of described opening comprises: metallic plate is provided, and described metallic plate is positioned over above opening; The chlorine of plasma state and described metallic plate react, and form the metal chloride of gaseous state; Metal in the metal chloride of described gaseous state combines with silicon in the Semiconductor substrate of open bottom, forms metal silicide layer; The metal chloride of described gaseous state and the reaction of described metal silicide layer form metal level in described open bottom.
3. the formation method of high-K gate dielectric layer as claimed in claim 2, is characterized in that, the material of described metallic plate is hafnium, lanthanum, zirconium, tantalum, titanium or aluminium.
4. the formation method of high-K gate dielectric layer as claimed in claim 2, is characterized in that, the technological parameter that forms the chlorine of described plasma state comprises: frequency is 2-4MHz, and power is 200-500W, and pressure is 0.01-0.1Torr, Cl
2Flow be 500-2000sccm.
5. the formation method of high-K gate dielectric layer as claimed in claim 2, is characterized in that, also comprises: pass into inert gas as the carrier of the chlorine of plasma state.
6. the formation method of high-K gate dielectric layer as claimed in claim 5, is characterized in that, described inert gas is Ar, He or N
2
7. the formation method of high-K gate dielectric layer as claimed in claim 5, is characterized in that, the flow of described inert gas is 500-3000sccm.
8. the formation method of high-K gate dielectric layer as claimed in claim 1, is characterized in that, the technological parameter that forms described metal level comprises: temperature is 250-350 ℃, and pressure is 0.01-0.1Torr.
9. the formation method of high-K gate dielectric layer as claimed in claim 1, is characterized in that, the gas that the described metal level of oxidation passes into when forming high-K gate dielectric layer is the oxygen of ozone or plasma state.
10. the formation method of high-K gate dielectric layer as claimed in claim 1, is characterized in that, the technological parameter that the described metal level of oxidation forms high-K gate dielectric layer comprises: the flow of ozone is 500-2000sccm, and pressure is 0.01-0.1Torr.
11. the formation method of high-K gate dielectric layer as claimed in claim 1 is characterized in that, also comprises: after metal level is formed on the bottom at described opening, described metal level is carried out purified treatment, reoxidize described metal level.
12. the formation method of high-K gate dielectric layer as claimed in claim 1 is characterized in that, the method for described purified treatment comprises: pass into inert gas to described layer on surface of metal.
13. the formation method of high-K gate dielectric layer as claimed in claim 1 is characterized in that, described inert gas is Ar, He or N
2, the flow of described inert gas is 500-3000sccm.
14. a transistorized formation method comprises:
Provide Semiconductor substrate, the opening that described semiconductor substrate surface is formed with insulating barrier and runs through the thickness of described insulating barrier;
It is characterized in that, also comprise:
Adopt the muriatic chemical vapor deposition method in reducing metal, form metal level in the bottom of described opening;
The described metal level of oxidation forms high-K gate dielectric layer;
Form the metal gate electrode layer that covers described high-K gate dielectric layer.
15. transistorized formation method as claimed in claim 14 is characterized in that, also comprises: remove described insulating barrier, expose described semiconductor substrate surface; Formation is positioned at described metal gate electrode layer sidewall and is positioned at the side wall of described semiconductor substrate surface; Take described side wall as mask, formation source/drain electrode in described Semiconductor substrate.
16. the formation device of a high-K gate dielectric layer is characterized in that, comprising:
The first reaction chamber is used for adopting the muriatic chemical vapor deposition method in reducing metal, in the open bottom of wafer high-K gate dielectric layer to be formed, forms metal level;
The second reaction chamber, adjacent with described the first reaction chamber, be used for the described metal level of oxidation and form high-K gate dielectric layer;
Clean unit between the first reaction chamber and the second reaction chamber, is used for removing the impurity of crystal column surface;
Whirligig, comprise rotating shaft and at least one turning arm that is connected with described rotating shaft, the first reaction chamber, the second reaction chamber, clean unit are positioned at described rotating shaft as central point, on the circumference of turning arm as radius, described turning arm transports wafer in the first reaction chamber, clean unit or the second reaction chamber by the rotation of rotating shaft.
17. the formation device of high-K gate dielectric layer as claimed in claim 16 is characterized in that, described the first reaction chamber comprises: the first base station, for the wafer of placing high-K gate dielectric layer to be formed; Be positioned at the clamping device of described the first base station top, be used for the clamping metallic plate.
18. the formation device of high-K gate dielectric layer as claimed in claim 16 is characterized in that, described the second reaction chamber comprises: the second base station is used for placing the wafer that is formed with metal level; Be positioned at the gas tip of described the second base station top, have some apertures in described gas tip, be used for the passage when passing into ozone or oxonium ion.
19. the formation device as claim 17 or 18 described high-K gate dielectric layers is characterized in that, also comprises: source coil, be used for receiving the electric power from power supply, produce uniform plasma; Plasma cavity is used for the uniform plasma that the reception sources coil produces, and will pass into the first reaction chamber or the second reaction chamber after gaseous plasma.
20. the formation device of high-K gate dielectric layer as claimed in claim 16 is characterized in that, the number of described turning arm equals the number sum of the first reaction chamber and the second reaction chamber.
21. the formation device of high-K gate dielectric layer as claimed in claim 16 is characterized in that, when the number of described the first reaction chamber and described the second reaction chamber is at least two, and the arrangement that described the first reaction chamber and the second reaction chamber replace.
22. the formation device of high-K gate dielectric layer as claimed in claim 16 is characterized in that, the distance between adjacent two the first reaction chambers, the second reaction chamber equates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110398208.XA CN103137461B (en) | 2011-12-02 | 2011-12-02 | The formation method of the formation method of high-K gate dielectric layer and forming apparatus, transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110398208.XA CN103137461B (en) | 2011-12-02 | 2011-12-02 | The formation method of the formation method of high-K gate dielectric layer and forming apparatus, transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103137461A true CN103137461A (en) | 2013-06-05 |
| CN103137461B CN103137461B (en) | 2015-10-14 |
Family
ID=48497114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110398208.XA Active CN103137461B (en) | 2011-12-02 | 2011-12-02 | The formation method of the formation method of high-K gate dielectric layer and forming apparatus, transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103137461B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1961096A (en) * | 2004-06-30 | 2007-05-09 | 英特尔公司 | Forming high-K dielectric layers on smooth substrates |
| CN101027770A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | A metal gate electrode semiconductor device |
| CN101298663A (en) * | 2007-04-30 | 2008-11-05 | 应用材料股份有限公司 | Methods for depositing a high-k dielectric material using chemical vapor deposition process |
| TW201106430A (en) * | 2009-08-04 | 2011-02-16 | United Microelectronics Corp | Manufcaturing method of semiconductor device |
| US20110195570A1 (en) * | 2010-02-09 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of bottom-up metal film deposition |
| CN102174708A (en) * | 2006-04-14 | 2011-09-07 | 应用材料股份有限公司 | Epitaxial growth of compound nitride semiconductor structures |
| US8053849B2 (en) * | 2005-11-09 | 2011-11-08 | Advanced Micro Devices, Inc. | Replacement metal gate transistors with reduced gate oxide leakage |
-
2011
- 2011-12-02 CN CN201110398208.XA patent/CN103137461B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1961096A (en) * | 2004-06-30 | 2007-05-09 | 英特尔公司 | Forming high-K dielectric layers on smooth substrates |
| CN101027770A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | A metal gate electrode semiconductor device |
| US8053849B2 (en) * | 2005-11-09 | 2011-11-08 | Advanced Micro Devices, Inc. | Replacement metal gate transistors with reduced gate oxide leakage |
| CN102174708A (en) * | 2006-04-14 | 2011-09-07 | 应用材料股份有限公司 | Epitaxial growth of compound nitride semiconductor structures |
| CN101298663A (en) * | 2007-04-30 | 2008-11-05 | 应用材料股份有限公司 | Methods for depositing a high-k dielectric material using chemical vapor deposition process |
| TW201106430A (en) * | 2009-08-04 | 2011-02-16 | United Microelectronics Corp | Manufcaturing method of semiconductor device |
| US20110195570A1 (en) * | 2010-02-09 | 2011-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of bottom-up metal film deposition |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103137461B (en) | 2015-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8967082B2 (en) | Plasma processing apparatus and gas supply device for plasma processing apparatus | |
| TWI521629B (en) | Film forming method, manufacturing method of semiconductor device using the same, film forming apparatus, and semiconductor device | |
| US9054037B2 (en) | Method of fabricating semiconductor device | |
| CN105304565B (en) | Semiconductor devices and forming method thereof | |
| TWI454600B (en) | Pattern formation method | |
| JP2009027134A (en) | Mos semiconductor memory device | |
| CN104124210A (en) | Method for forming semiconductor structure | |
| TW201535510A (en) | Fine pattern forming method, semiconductor device manufacturing method, substrate processing device, and recording medium | |
| CN100550387C (en) | Form the method for dielectric film and utilize this method in semiconductor devices, to form the method for capacitor | |
| US10141454B2 (en) | Field-effect transistors having black phosphorus channel and methods of making the same | |
| JP2011124240A (en) | Mos semiconductor memory device, method of manufacturing the same, and computer readable storage medium | |
| TW201432781A (en) | Substrate processing apparatus and method of manufacturing semiconductor device | |
| JP2007528602A (en) | Silicon germanium surface layer for high dielectric constant integration | |
| TWI400793B (en) | A semiconductor device, and a semiconductor device | |
| US20230018127A1 (en) | Microelectronic devices with channel sub-regions of differing microstructures, and related methods and systems | |
| CN114093927A (en) | Complementary field effect transistor based on ferroelectric doping and manufacturing method thereof | |
| CN103137461B (en) | The formation method of the formation method of high-K gate dielectric layer and forming apparatus, transistor | |
| US10128112B2 (en) | Method of fabricating semiconductor device | |
| WO2021204289A1 (en) | Semiconductor structure and method for forming same | |
| WO2008156215A1 (en) | Mos semiconductor memory device | |
| US20090203198A1 (en) | Semiconductor manufacturing apparatus and semiconductor manufacturing method using the same | |
| CN103632945A (en) | Formation method for fin-type field effect transistor | |
| CN103137857B (en) | The formation method of runnel insulator material layer and forming apparatus | |
| US20140287593A1 (en) | High throughput multi-layer stack deposition | |
| KR101533846B1 (en) | Semiconductor device manufacturing apparatus and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |