CN103135660A - Network signal output circuit - Google Patents
Network signal output circuit Download PDFInfo
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- CN103135660A CN103135660A CN 201110392889 CN201110392889A CN103135660A CN 103135660 A CN103135660 A CN 103135660A CN 201110392889 CN201110392889 CN 201110392889 CN 201110392889 A CN201110392889 A CN 201110392889A CN 103135660 A CN103135660 A CN 103135660A
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- voltage signal
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Abstract
The invention discloses a network signal output circuit. The network signal output circuit comprises a time-delay circuit, an amplifying circuit, a south bridge chip and a network chip, wherein the amplifying circuit is electrically connected with the time-delay circuit. The time-delay circuit receives a first direct current voltage signal and the time-delay circuit can output the first direct current voltage signal after the first direct current voltage signal is delayed. The amplifying circuit receives the first direct current voltage signal which is output delayed. The amplifying circuit can be converted into the output first direct current voltage signal which is delayed to a second direct current voltage signal so as to output to the south bridge chip. The south bridge chip outputs a network clock signal to drive the network chip after the south bridge chip receives the second direct current voltage signal.
Description
Technical field
The present invention relates to a kind of signal output apparatus, refer to especially the network signal output circuit in a kind of computer system.
Background technology
The networking-on-motherboard card chip has referred to integrate the integrated network card chip of mainboard of network function, by IMVP_PWRGD (the central processing unit power supply is normal) signal is amplified rear output PCH_PWROK (the South Bridge chip power supply is normal) signal, export the network clocking signal of 100MHZ to network card chip thereby drive South Bridge chip on traditional computer main board.Traditional PCH_PWROK signal usually output is too fast and sequential is ahead of other signal, makes network card chip can't normally receive the network clocking signal of 100MHZ when the computer system boot-strap self check, and then causes computer system to can't detect network after start.
Summary of the invention
In view of above content, be necessary to provide a kind of signal sequence normal network signal output circuit.
a kind of network signal output circuit, comprise a delay circuit, one is electrically connected the amplifying circuit of described delay circuit, one South Bridge chip and a network chip, described delay circuit receives one first d. c. voltage signal, and with output after described the first d. c. voltage signal time-delay, described amplifying circuit receives the first d. c. voltage signal through time-delay output, and the first d. c. voltage signal of the output of delaying time is converted to one second d. c. voltage signal and exports to described South Bridge chip, described South Bridge chip is exported a described network chip of network clocking signal driver after receiving the second d. c. voltage signal.
compared to prior art, above-mentioned network signal output circuit receives the first d. c. voltage signal by described delay circuit, and with output after described the first d. c. voltage signal time-delay, described amplifying circuit receives the first d. c. voltage signal through time-delay output, and the first d. c. voltage signal of the output of delaying time is converted to the second d. c. voltage signal and exports to described South Bridge chip, described South Bridge chip output network clock signal after receiving the second d. c. voltage signal drives described network chip, because described delay circuit is exported the first d. c. voltage signal time-delay, described South Bridge chip time-delay output network clock signal makes signal sequence meet system requirements, computer system can normally detect network.
Description of drawings
Fig. 1 is the system block diagram of a preferred embodiment of network signal output circuit of the present invention.
Fig. 2 is the circuit diagram of the network signal output circuit of Fig. 1.
The main element symbol description
| |
10 |
| Amplifying |
20 |
| |
30 |
| South Bridge |
40 |
| |
60 |
| The first resistance | R1 |
| The first electric capacity | C1 |
| Integrated operational amplifier | A |
| The second resistance | R2 |
| The second electric capacity | C2 |
| Schottky diode | D |
| The 3rd resistance | R3 |
| The 3rd electric capacity | C3 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
See also Fig. 1 and Fig. 2, a preferred embodiment of network signal output circuit of the present invention comprises that a delay circuit 10, is electrically connected dormant circuit 30, a South Bridge chip 40 and a network chip 60 that the amplifying circuit 20 of described delay circuit 10, is electrically connected described delay circuit 10 and amplifying circuit 20.Described delay circuit 10 receives one first d. c. voltage signal, and with output after described the first d. c. voltage signal time-delay.The first d. c. voltage signal that described amplifying circuit 20 receives through time-delay output, and the first d. c. voltage signal exported of delay time is converted to one second d. c. voltage signal and exports to described South Bridge chip 40.Described South Bridge chip 40 is exported a described network chip 60 of network clocking signal driver after receiving the second d. c. voltage signal.Described dormant circuit 30 receives a system power supply normal signal, and exports a system hibernates signal to South Bridge chip 40 according to this system power supply normal signal.Described South Bridge chip 40 enters dormant state after receiving the system hibernates signal.
Described delay circuit 10 comprises one first resistance R 1 and one first capacitor C 1.Described the first resistance R 1 one terminations are received the first d. c. voltage signal, and described first resistance R 1 other end is via the first capacitor C 1 ground connection.Wherein, the resistance size of described the first resistance R 1 is 10 kilohms, and the amount of capacity of described the first capacitor C 1 is 1 microfarad.
Described amplifying circuit 20 comprises an integrated operational amplifier A, one second resistance R 2 and one second capacitor C 2.Described integrated operational amplifier A comprises an input end, an output terminal and a power end.The input end of described integrated operational amplifier A is electrically connected first resistance R 1 other end.Output terminal output the second d. c. voltage signal of described integrated operational amplifier A, the output terminal of described integrated operational amplifier A is also via the second resistance eutral grounding.The power end of described integrated operational amplifier A receives one the 3rd d. c. voltage signal VCC, and the power end of described integrated operational amplifier A is also via the second capacitor C 2 ground connection.Wherein, described the first d. c. voltage signal is a central processing unit power supply normal signal IMVP_PWRGD, and described the second d. c. voltage signal is a South Bridge chip power supply normal signal PCH_PWROK.
Described dormant circuit 30 comprises a schottky diode D, one the 3rd resistance R 3 and one the 3rd capacitor C 3.Described schottky diode D comprises a first anode, a second anode and a negative electrode.The first anode of described schottky diode D is electrically connected the input end of integrated operational amplifier A.The second anode of described schottky diode D receives described system power supply normal signal ALL_SYS_PWRGD.The negative electrode of described schottky diode D is according to the described system hibernates signal SLP_3#_3R of system power supply normal signal output.Described the 3rd resistance R 3 one terminations are received a system voltage signal S_PG.Described the 3rd resistance R 3 other ends are via the 3rd capacitor C 3 ground connection, and described the 3rd resistance R 3 other ends also are electrically connected the second anode of schottky diode D.
During work, described central processing unit power supply normal signal IMVP_PWRGD is through the input end of the delay circuit 10 described integrated operational amplifier A of time-delay input.Described delay circuit 10 is according to the described South Bridge chip power supply of the central processing unit power supply normal signal IMVP_PWRGD output normal signal PCH_PWROK after delaying time.Described South Bridge chip 40 is receiving the described network clocking signal driver network chip 60 of South Bridge chip power supply normal signal PCH_PWROK output.Simultaneously, receive the system power supply normal signal ALL_SYS_PWRGD of noble potential when the second anode of described schottky diode D, described system hibernates signal SLP_3#_3R by electronegative potential to the noble potential saltus step.Described South Bridge chip 40 receives the system hibernates signal SLP_3#_3R of noble potential and controls computer system and enters dormant state.
network signal output circuit of the present invention receives the first d. c. voltage signal by described delay circuit 10, and with output after described the first d. c. voltage signal time-delay, the first d. c. voltage signal that described amplifying circuit 20 receives through time-delay output, and the first d. c. voltage signal of the output of delaying time is converted to the second d. c. voltage signal and exports to described South Bridge chip 40, described South Bridge chip 40 output network clock signal after receiving the second d. c. voltage signal drives described network chip 60, because described delay circuit 10 is exported the first d. c. voltage signal time-delay, described South Bridge chip 40 time-delay output network clock signals make signal sequence meet system requirements, computer system can normally detect network.
Claims (8)
1. network signal output circuit, comprise an amplifying circuit that is electrical connected in turn, one South Bridge chip and a network chip, it is characterized in that: described network signal output circuit comprises that also one is electrically connected the delay circuit of described amplifying circuit, described delay circuit receives one first d. c. voltage signal, and with output after described the first d. c. voltage signal time-delay, described amplifying circuit receives the first d. c. voltage signal through time-delay output, and the first d. c. voltage signal of the output of delaying time is converted to one second d. c. voltage signal and exports to described South Bridge chip, described South Bridge chip is exported a described network chip of network clocking signal driver after receiving the second d. c. voltage signal.
2. network signal output circuit as claimed in claim 1, it is characterized in that: described delay circuit comprises one first resistance and one first electric capacity, described the first resistance one termination is received the first d. c. voltage signal, and the described first resistance other end is via the first capacity earth.
3. network signal output circuit as claimed in claim 2, it is characterized in that: described amplifying circuit comprises an integrated operational amplifier, one second resistance and one second electric capacity, described integrated operational amplifier comprises an input end, an output terminal and a power end, the input end of described integrated operational amplifier is electrically connected the first resistance other end, output terminal output second d. c. voltage signal of described integrated operational amplifier, the power end of described integrated operational amplifier receives one the 3rd d. c. voltage signal.
4. network signal output circuit as claimed in claim 3, it is characterized in that: described amplifying circuit also comprises one second resistance and one second electric capacity, the output terminal of described integrated operational amplifier is also via the second resistance eutral grounding, and the power end of described integrated operational amplifier is also via the second capacity earth.
5. network signal output circuit as claimed in claim 3, it is characterized in that: described network signal output circuit comprises that also one is electrically connected the dormant circuit of described delay circuit and amplifying circuit, described dormant circuit comprises a schottky diode, described schottky diode comprises a first anode, one second anode and a negative electrode, the first anode of described schottky diode is electrically connected the input end of integrated operational amplifier, the second anode of described schottky diode receives a system power supply normal signal, the negative electrode of described schottky diode is given described South Bridge chip according to system power supply normal signal output one system hibernates signal.
6. network signal output circuit as claimed in claim 5, it is characterized in that: described dormant circuit also comprises one the 3rd resistance and one the 3rd electric capacity, described the 3rd resistance one termination is received a system voltage signal, described the 3rd resistance other end is via the 3rd capacity earth, and described the 3rd resistance other end also is electrically connected the second anode of schottky diode.
7. network signal output circuit as described in any one in claim 1 to 6 is characterized in that: described the first d. c. voltage signal is a central processing unit power supply normal signal, and described the second d. c. voltage signal is a South Bridge chip power supply normal signal.
8. network signal output circuit as described in any one in claim 2 to 6, it is characterized in that: the resistance size of described the first resistance is 10 kilohms, the amount of capacity of described the first electric capacity is 1 microfarad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110392889 CN103135660A (en) | 2011-12-01 | 2011-12-01 | Network signal output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110392889 CN103135660A (en) | 2011-12-01 | 2011-12-01 | Network signal output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103135660A true CN103135660A (en) | 2013-06-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110392889 Pending CN103135660A (en) | 2011-12-01 | 2011-12-01 | Network signal output circuit |
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| Country | Link |
|---|---|
| CN (1) | CN103135660A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914976A (en) * | 2014-03-12 | 2015-09-16 | 中兴通讯股份有限公司 | Data processing method, data processing device and terminal |
| CN105653296A (en) * | 2014-11-10 | 2016-06-08 | 鸿富锦精密工业(武汉)有限公司 | Electronic device awaken system |
-
2011
- 2011-12-01 CN CN 201110392889 patent/CN103135660A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914976A (en) * | 2014-03-12 | 2015-09-16 | 中兴通讯股份有限公司 | Data processing method, data processing device and terminal |
| CN105653296A (en) * | 2014-11-10 | 2016-06-08 | 鸿富锦精密工业(武汉)有限公司 | Electronic device awaken system |
| CN105653296B (en) * | 2014-11-10 | 2018-12-18 | 鸿富锦精密工业(武汉)有限公司 | Electronic equipment wakes up system |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130605 |