CN103135021A

CN103135021A - Wafer level mass production testing method for chips with ultra-small dimensions

Info

Publication number: CN103135021A
Application number: CN2011103747179A
Authority: CN
Inventors: 朱渊源
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-22
Filing date: 2011-11-22
Publication date: 2013-06-05
Anticipated expiration: 2031-11-22
Also published as: CN103135021B

Abstract

The invention discloses a wafer level mass production testing method for chips with ultra-small dimensions. The method comprises a first step of enabling one wafer to be provided with a plurality of chips with ultra-small dimensions and the same structure, enabling the plurality of adjacent chips with ultra-small dimensions to form assemblies, and enabling both the length and the width of each assembly to be larger than 0.5mm; a second step of utilizing a probe station to scan the wafer, manufacturing a variety parameter diagram for the assemblies on the wafer, enabling the variety parameter diagram to at least comprise the length and the width of each assembly and relative coordinates of every chip with the ultra-small dimensions in the assemblies relative to the assemblies; a third step of utilizing a tester connected with the probe station to call the variety parameter diagram of the assemblies, testing every chip with the ultra-small dimensions in every assembly on the wafer, and generating a testing result diagram of every assembly; a fourth step of utilizing the tester to integrate the testing result diagrams of all the assemblies on the wafer, and generating a testing result diagram of the whole wafer. The wafer level mass production testing method can effectively meet the requirements for wafer level mass production testing for the chips with the ultra-small dimensions.

Description

The silicon chip level volume production method of testing of extra small size chip

Technical field

The present invention relates to a kind of chip detecting method, particularly relate to a kind of method of extra small size chip being carried out the test of silicon chip level volume production.

Background technology

Have a plurality of chips (chip) on a silicon chip (wafer), each chip is needed to test.When all chips on a silicon chip all are same structure, just can test all chips on it take silicon chip as unit, this is called the silicon chip level volume production test of chip.

See also Fig. 1, the existing method that chip is carried out the test of silicon chip level volume production comprises the steps:

In the 1st step, probe station scans silicon chip 10, has the chip 11 of a plurality of same structures on described silicon chip 10.Probe station is that the chip 11 on silicon chip 10 is made Cultivar parameter Figure 12.Cultivar parameter Figure 12 of described chip comprises length and the width of chip 11 at least.

In the 2nd step, the tester of linking probe platform calls Cultivar parameter Figure 12 of chip 11, and each chip 11 on silicon chip 10 is tested, and then generates test result Figure 13 of whole silicon chip 10.Test result Figure 13 of this silicon chip is used for follow-up getting classification ready or produce and analyze.

Said method also is not suitable for extra small size chip, and namely length and width are all at the chip below 0.5 millimeter.This is due to the extra small size chip of probe station None-identified, also just can't be extra small size chip manufacturing Cultivar parameter figure, causes extra small size chip can't carry out the test of silicon chip level volume production.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of method of extra small size chip being carried out the test of silicon chip level volume production, thereby improves the test performance of extra small size chip, reduces testing cost.

For solving the problems of the technologies described above, the silicon chip level volume production method of testing of the extra small size chip of the present invention comprises the steps:

In the 1st step, has the extra small size chip of a plurality of same structures on silicon chip; Adjacent a plurality of extra small size chip is formed set, and the length of described set and width are all greater than 0.5 millimeter;

In the 2nd step, probe station scans silicon chip, and is the set making Cultivar parameter figure on silicon chip; Described Cultivar parameter figure comprises length and the width of set at least, and in set each extra small size chip with respect to the relative coordinate of this set;

In the 3rd step, the tester of linking probe platform calls the Cultivar parameter figure of set, each the extra small size chip in each set on silicon chip is tested, and generated the test result figure of each set;

In the 4th step, tester is integrated into one with the test result figure of all set on silicon chip, namely generates the test result figure of whole silicon chip.

The present invention can satisfy the silicon chip level volume production testing requirement to extra small size chip effectively.Reduce the expense of the new system of exploitation and purchase new equipment, reduce testing cost.

Description of drawings

Fig. 1 is the schematic diagram that existing chip carries out the test of silicon chip level volume production;

Fig. 2 is the schematic diagram that the extra small size chip of the present invention carries out the test of silicon chip level volume production.

Description of reference numerals in figure:

10 is silicon chip; 11 is chip; 11a is extra small size chip; 21 are set; 12 is the Cultivar parameter figure of chip; The 22 Cultivar parameter figure for set; The 23 test result figure for set; 13 is the test result figure of whole silicon chip.

Embodiment

See also Fig. 2, the silicon chip level volume production method of testing of the extra small size chip of the present invention comprises the steps:

The 1st goes on foot, and has the extra small size chip 11a of a plurality of same structures on silicon chip 10, and the length of each extra small size chip 11a and width are all below 0.5 millimeter.Adjacent a plurality of extra small size chip 11a is formed a set 21, and the length of described set 21 and width are all greater than 0.5 millimeter.

Preferably, under the prerequisite that set 21 length and width all meet the demands, make set 21 have the extra small size chip 11a of minimum number.

For example, 2 * 2 adjacent extra small size chip 11a are formed a set 21.

In the 2nd step, probe station scans silicon chip 10, and is the set 21 making Cultivar parameter Figure 22 on silicon chip 10.Cultivar parameter Figure 22 of described set comprises set 21 length and width at least, and gathers in 21 each extra small size chip 11a with respect to the relative coordinate of this set 21.

All greater than 0.5 millimeter, so probe station can identify set 21, do not gather 21 and makes Cultivar parameter figure due to set 21 length and width.

Described relative coordinate is used for facilitating tester that each the extra small size chip 11a in a set 21 is tested separately.

In the 3rd step, the tester of linking probe platform calls Cultivar parameter Figure 22 of set, each the extra small size chip 11a in each set 21 on silicon chip 10 is tested, and generate test result Figure 23 of each set.

In the 4th step, tester is integrated into one with test result Figure 23 of all set on silicon chip 10, namely generates test result Figure 13 of whole silicon chip.

These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. the silicon chip level volume production method of testing of an extra small size chip, described extra small size chip refer to that the length of chip and width are all below 0.5 millimeter; It is characterized in that, comprise the steps:

2. the silicon chip level volume production method of testing of extra small size chip according to claim 1, is characterized in that, described method is in the 1st step, under the prerequisite that length and the width of set all meets the demands, makes set have the extra small size chip of minimum number.

3. the silicon chip level volume production method of testing of extra small size chip according to claim 1, is characterized in that, described method forms a set with 2 * 2 adjacent extra small size chips in the 1st step.