CN103123801A - Memory device and negative-bit line signal generation device thereof - Google Patents

Abstract

The invention discloses a memory device and a negative-bit line signal generation device thereof. The negative-bit line signal generation device comprises a capacitor, a discharge channel and a voltage generator, wherein the capacitor generates a negative-bit line signal on a terminal point coupled to a bit line; the discharge channel is connected or disconnected according to a voltage drive enable signal; and the voltage generator determines whether to provide a voltage to a negative drive terminal point or not according to the voltage drive enable signal. In the negative-bit line signal generation device, when the voltage generator provides the voltage to the negative drive terminal point, the discharge channel is disconnected, and the capacitor correspondingly generates the negative bit line signal on the terminal point coupled to the bit line.

Description

Storage arrangement and negative bit line signal generation device thereof

Technical field

The present invention relates to a kind of storage arrangement, particularly relate to a kind of negative bit line signal generation device of storage arrangement.

Background technology

Along with progressing greatly of electronic technology, electronic product becomes instrument indispensable in people's daily life.And be used for the storage arrangement of recorded information at electronic product, also become one of them important part.

With static RAM (Static Random Access Memory, SRAM) be example, the operating voltage that receives at electronic installation is more and more lower, in the more and more faster situation of the requirement of access speed, when carrying out access for static RAM, for promoting the voltage difference between its bit line (bit line) and word line (word line), so a kind of technology that makes negative bit line signal be reduced to the following negative bit line signal of zero voltage level is suggested.

When existing negative bit line signal generating technique often occurs in high operation voltage, can correspondingly produce the negative bit line signal with larger absolute value of voltage.Thus, can make the voltage difference between the transistorized grid source electrode that receives bit line signal and word-line signal excessive.Under using for a long time, this transistor may be damaged and produce the phenomenon that electric leakage maybe can't work.Also caused the phenomenon of the fiduciary level decline of static RAM.

Summary of the invention

The invention provides multiple negative bit line signal generation device, in order to produce the negative bit line signal that does not significantly change with the variation of operating voltage.

The invention provides the multiple memorizers device, a plurality of negative bit line signal generation devices are set, and in order to produce the negative bit line signal that does not significantly change with the variation of operating voltage.

The present invention proposes a kind of negative bit line signal generation device, comprises electric capacity, discharge channel and voltage generator.Electric capacity is coupled to negative the promotion between end points and bit line, and produce on the end points of bit line should negative bit line signal being coupled to for electric capacity.Discharge channel is coupled in reference voltage and the negative end points that promotes, and promotes enable signal with conducting or disconnection according to voltage.Voltage generator promotes enable signal to determine whether provide voltage to the negative end points that promotes according to voltage.Wherein, when voltage generator provided voltage to negative promotion end points, discharge channel was disconnected, and electric capacity is being coupled to the negative bit line signal of corresponding generation on the end points of bit line.

The present invention also proposes a kind of negative bit line signal generation device, comprises the first electric capacity, discharge channel, the second electric capacity, voltage generator and switch.The first electric capacity is coupled to negative the promotion between end points and bit line, and electric capacity is being coupled to the negative bit line signal of generation on the end points of bit line.Discharge channel is coupled to the negative end points that promotes, and promotes enable signal to determine whether provide reference voltage to the negative end points that promotes according to voltage.Voltage generator is coupled to the second electric capacity, promotes enable signal to determine whether provide a voltage that the second electric capacity is charged according to voltage.Switch series is connected on coupling a little of voltage generator and the second electric capacity and between bit line, according to voltage promote enable signal with conducting or disconnect the second electric capacity and the first electric capacity between annexation.

The present invention also proposes a kind of storage arrangement, has multiple bit lines.Storage arrangement comprises a plurality of negative bit line signal generation devices.Negative bit line signal generation device is coupled to bit line, and each negative bit line signal generation device comprises electric capacity, discharge channel and voltage generator.Electric capacity is coupled to negative the promotion between end points and bit line, and produce on the end points of bit line should negative bit line signal being coupled to for electric capacity.Discharge channel is coupled in reference voltage and the negative end points that promotes, and promotes enable signal with conducting or disconnection according to voltage.Voltage generator promotes enable signal to determine whether provide voltage to the negative end points that promotes according to voltage.Wherein, when voltage generator provided voltage to negative promotion end points, discharge channel was disconnected, and electric capacity is being coupled to the negative bit line signal of corresponding generation on the end points of bit line.

The present invention also proposes a kind of storage arrangement, has multiple bit lines.Storage arrangement comprises a plurality of negative bit line signal generation devices.Negative bit line signal generation device is coupled to bit line, and each negative bit line signal generation device comprises the first electric capacity, discharge channel, the second electric capacity, voltage generator and switch.The first electric capacity is coupled to negative the promotion between end points and bit line, and electric capacity is being coupled to the negative bit line signal of generation on the end points of bit line.Discharge channel is coupled to the negative end points that promotes, and promotes enable signal to determine whether provide reference voltage to the negative end points that promotes according to voltage.Voltage generator is coupled to the second electric capacity, promotes enable signal to determine whether provide a voltage that the second electric capacity is charged according to voltage.Switch series is connected on coupling a little of voltage generator and the second electric capacity and between bit line, according to voltage promote enable signal with conducting or disconnect the second electric capacity and the first electric capacity between annexation.

Based on above-mentioned, the invention provides voltage generator comes one of them of two end points of the electric capacity that pairs of bit line connects that voltage is provided, and the variation of the voltage that passes through to provide and operating voltage is without the characteristic that is associated, and negative bit line signal that negative bit line signal generation device produces can not produced significantly along with the rising of operating voltage or reduction change.

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.

Description of drawings

Fig. 1 illustrates the schematic diagram of a negative bit line signal generation device 100 of the embodiment of the present invention.

Fig. 2 A illustrates the schematic diagram of the negative bit line signal generation device 200 of another embodiment of the present invention.

Fig. 2 B illustrates another embodiment of the negative bit line signal generation device 200 of the embodiment of the present invention.

Fig. 3 illustrates the schematic diagram of the negative bit line signal generation device 300 of another embodiment of the present invention.

Fig. 4 illustrates the schematic diagram of the negative bit line signal generation device 400 of another embodiment of the present invention.

Fig. 5 illustrates the schematic diagram of the negative bit line signal generation device 500 of another embodiment of the present invention.

Fig. 6 illustrates the schematic diagram of the negative bit line signal generation device 600 of yet another embodiment of the invention.

Fig. 7 illustrates the schematic diagram of the negative bit line signal generation device 700 of an embodiment more of the present invention.

Fig. 8 illustrates the schematic diagram of the storage arrangement 800 of one embodiment of the invention.

The reference numeral explanation

100,200,300,400,500,600: negative bit line signal generation device

110,210,310,410,510,610,710: discharge channel

120,220,320,420: voltage generator

520: the band gap voltage generation circuit

620,720: voltage generator

222: voltage drop element

223: the discharge current source

630: switch

NFB: current controling signal

FB: reverse signal

INV0～INV6: reverser

C _bst, C1: electric capacity

BL: bit line

GND: reference voltage

MN1, MN2, M1～M6: transistor

NBST: the negative end points that promotes

NSBL: negative bit line signal

V1: fixed voltage

BSTEN: voltage promotes enable signal

VCC: operating voltage

WCLK: enabling signal

VNBST: end-point voltage

VNBST1: feedback voltage

D1: diode

C _blc: electric capacity of voltage regulation

PC: end points

B1, B2: signal

TG0: transmission gate

Embodiment

Below please refer to Fig. 1, Fig. 1 illustrates the schematic diagram of a negative bit line signal generation device 100 of the embodiment of the present invention.Negative bit line signal generation device 100 comprises capacitor C _bst, discharge channel 110 and voltage generator 120.Capacitor C _bstBe coupled between the negative end points NBST of promotion and bit line BL capacitor C _bstProduce negative bit line signal NSBL on the end points that is coupled to bit line BL.Discharge channel 110 is coupled in reference voltage GND and negative the promotion between end points NBST, promotes enable signal BSTEN with conducting or disconnection according to voltage.Voltage generator 120 promotes enable signal BSTEN to determine whether provide voltage V1 to the negative end points NBST that promotes according to voltage.

In the integrated operation of negative bit line signal generation device 100, voltage generator 120 is according to for example providing voltage V1 to promote end points NBST to negative for the voltage of low voltage level promotes enable signal BSTEN, and the negative voltage level that promotes on end points NBST is charged to equal voltage V1.Then, negative promote that voltage level on end points NBST is stable and equal voltage V1 after, promote enable signal BSTEN by transition to for example high-voltage level, and make discharge channel 110 conductings, and make simultaneously voltage generator 120 stop providing voltage V1 to the negative end points NBST that promotes.Thus, promote voltage fast-descending on end points NBST to the reference voltage GND that equals ground voltage due to negative, then pass through capacitor C _bstThe Promoting effect that produces, the voltage on bit line BL be synchronous decline, and use and produce negative bit line signal NSBL.

Please pay special attention to, the voltage V1 that produces due to voltage generator 120 is that the increase of understanding the operating voltage that uses along with negative bit line signal generation device 100 and affiliated storage arrangement reduces, therefore, the magnitude of voltage of the negative bit line signal NSBL that produces of negative bit line signal generation device 100 also will descend because the increase of operating voltage is corresponding.

In the present embodiment, the discharge channel 110 of negative bit line signal generation device 100 is that transistor MN1 by N-type comes construction.The grid receiver voltage of transistor MN1 promotes enable signal BSTEN, and its source electrode and drain electrode are serially connected between the negative end points NBST of promotion and reference voltage GND.

Below please refer to Fig. 2 A, Fig. 2 A illustrates the schematic diagram of the negative bit line signal generation device 200 of another embodiment of the present invention.Negative bit line signal generation device 200 comprises capacitor C _bst, discharge channel 210 and voltage generator 220.Voltage generator 220 comprises by the switch of transistor M5 construction, charging current source 221, switch, voltage drop element 222 and discharge current source 223 by transistor M2 construction.

The first end of transistor M5 receives operating voltage VCC, and its control end receives its second end of enabling signal WCLK and is coupled to discharge current source 223, and in order to current controling signal NFB to be provided.Charging current source 221 comes construction by transistor M1, wherein, the control end of transistor M1 receives the reverse signal FB of the current controling signal NFB that produces according to reverser INV0, and the first end of transistor M1 receives operating voltage VCC, and its second end is coupled to the first end of transistor M2.The control end of transistor M2 receives the reverse signal of the enabling signal WCLK that is produced by reverser INV1, and the second end of transistor M2 is coupled to an end of voltage drop element 222.The other end of voltage drop element 222 is coupled to discharge current source 223.When transistor M2 conducting, the charged electrical that charging current source 221 produces fails to be convened for lack of a quorum the negative end points NBST that promotes is charged, and produces according to this end-point voltage VNBST.222 of voltage drop elements carry out step-down for end-point voltage VNBST, and produce feedback voltage VNBST1.In the present embodiment, voltage drop element 222 is by the construction of transistor M3 institute, and the control end of transistor M3 receives operating voltage VCC.Therefore, feedback voltage VNBST1 equals the critical voltage that end-point voltage VNBST deducts transistor M3.

223, discharge current source is serially connected between the second end and reference voltage GND of transistor M5, and discharge current source 223 produces discharge current according to feedback voltage VNBST1, and uses the voltage swing of adjusting current controling signal NFB.In the present embodiment, discharge current source 223 is by the construction of transistor M4 institute, and the control end of transistor M4 receives feedback voltage VNBST1, and its first end is coupled to the second end of transistor M5, and its second end is coupled to reference voltage GND.The control end of transistor M6 receives the reverse signal of enabling signal WCLK, its first and second end is coupled to respectively the negative end points NBST of promotion and reference voltage GND, and transistor M6 is in order to provide the negative path that end points NBST discharges that promotes when voltage generator 220 does not need to provide voltage.

Aspect integrated operation, enabling signal WCLK by the voltage low level transition during the rising edge of voltage high level, transistor M2 can be switched on gradually, and transmit the extremely negative promotion end points of the charging current NBST that charging current source 221 produces, and use the end-point voltage VNBST that generation raises gradually.At the same time, voltage drop element 222 carries out for end-point voltage VNBST corresponding rising of feedback voltage VNBST1 that step-down produces, and makes discharge current source 223 provide discharge current to downgrade current controling signal NFB.

If when being relatively low voltage as operating voltage VCC, discharge current source 223 can be because the feedback voltage VNBST1 that receives be too low, and very large discharge current can't be provided, negative to promote that end points NBST charge be slowly with respect to 221 pairs of charging current sources to make speed that current controling signal NFB downgraded.Also therefore, end-point voltage VNBST will be charged to and equal operating voltage VCC.

Opposite, if when being relatively high voltage as operating voltage VCC, 223, discharge current source can provide larger discharge current, and turns down fast current controling signal NFB.That is to say, the time that 221 couples of negative promotion end points NBST of charging current source charge will significantly shorten in the situation that current controling signal NFB is turned down fast, therefore, end-point voltage VNBST will can not be charged to the operating voltage VCC that equals higher, and can be limited in certain voltage level (less than operating voltage VCC).

Subsidiary one carries, the rising edge of enabling signal WCLK can occur in voltage promote enable signal be enabled (namely produce negative bit line signal) front.

Below please refer to Fig. 2 B, Fig. 2 B illustrates another embodiment of the negative bit line signal generation device 200 of the embodiment of the present invention.Wherein, voltage drop element 222 can utilize diode P1 to replace, and the anode of diode P1 is coupled to the negative end points NBST that promotes, and its negative electrode is coupled to the control end of transistor M4.And under this state, feedback voltage VNBST1 equals the critical voltage that end-point voltage VNBST deducts diode P1.

Below please refer to Fig. 3, Fig. 3 illustrates the schematic diagram of the negative bit line signal generation device 300 of another embodiment of the present invention.Negative bit line signal generation device 300 comprises capacitor C _bst, discharge channel 310, voltage generator 320 and electric capacity of voltage regulation C _blcIn the present embodiment, the circuit structure of discharge channel 310 and voltage generator 320 is identical with the embodiment that mode of operation and Fig. 2 A illustrate, and below seldom gives unnecessary details.And the present embodiment also arranges electric capacity of voltage regulation C between bit line BL and reference voltage GND _blcBy this electric capacity of voltage regulation C _blcSetting, the voltage V on bit line BL _BLCan be expressed as shown in mathematical expression (1):

$V_{\mathrm{BL}}=\frac{\mathrm{VNBSST}\×C_{\mathrm{bst}}}{C_{\mathrm{bst}}+C_{\mathrm{bl}}+C_{\mathrm{blc}}}---\left(1\right)$

C wherein _blBe the capacitance on bit line BL.

Can be learnt by above-mentioned mathematical expression (1), the different capacitance that the load that the bit line BL of corresponding different storage arrangements bears produces, the embodiment of the present invention can be by setting electric capacity of voltage regulation C _blcThe capacitance size obtain compensation, make bit line BL voltage V when producing negative bit line signal _BLCan stablize and not have excessive drift.

Below please refer to Fig. 4, Fig. 4 illustrates the schematic diagram of the negative bit line signal generation device 400 of another embodiment of the present invention.Negative bit line signal generation device 400 comprises capacitor C _bst, discharge channel 410, voltage generator 420, reverser INV2 and electric capacity of voltage regulation C _blcIn the present embodiment, the circuit structure of discharge channel 410 and voltage generator 420 is identical with the embodiment that mode of operation and Fig. 2 A illustrate, and below seldom gives unnecessary details.And the present embodiment also promotes between enable signal BSTEN, reverser INV2 and electric capacity of voltage regulation C to be set at bit line BL and voltage _blcWherein, the input end receiver voltage of reverser INV2 promotes enable signal BSTEN, and its output terminal couples electric capacity of voltage regulation C _blcElectric capacity of voltage regulation C _blcThe other end be coupled to bit line BL.When voltage promotion enable signal BSTEN was voltage high level (equaling operating voltage VCC), the output terminal of reverser INV2 provided the signal of voltage low level (for example ground voltage) to electric capacity of voltage regulation C _blcBy this electric capacity of voltage regulation C _blcSetting, the voltage V on bit line BL _BLCan be expressed as shown in mathematical expression (2):

$V_{\mathrm{BL}}=\frac{\mathrm{VNBST}\×C_{\mathrm{bst}}-\mathrm{VCC}\×C_{\mathrm{blc}}}{C_{\mathrm{bst}}+C_{\mathrm{bl}}+C_{\mathrm{blc}}}---\left(2\right)$

Same, by electric capacity of voltage regulation C _blcSetting, can make bit line BL voltage V when producing negative bit line signal _BLCan stablize and not have excessive drift.And, due in the molecule of mathematical expression (2), electric capacity of voltage regulation C _blcCapacitance be exaggerated VCC doubly, therefore, the electric capacity of voltage regulation C in the present embodiment _blcCapacitance can not need excessive, the voltage V of the negative bit line signal of also can playing stably _BL

Below please refer to Fig. 5, Fig. 5 illustrates the schematic diagram of the negative bit line signal generation device 500 of another embodiment of the present invention.Negative bit line signal generation device 500 comprises capacitor C _bst, discharge channel 510, band gap voltage generation circuit 520, reverser INV4 and electric capacity of voltage regulation C _blcIn the present embodiment, the variation of the fixed voltage that produces of band gap voltage generation circuit 520 and operating voltage VCC is irrelevant.And band gap voltage generation circuit 520 receiver voltages promote enable signal BSTEN to determine whether provide fixed voltage to the negative end points NBST that promotes.In addition, the embodiment of the negative bit line signal generation device 400 that the present embodiment and Fig. 4 illustrate is similar, below seldom gives unnecessary details.

Wherein, the band gap voltage generation circuit 520 that illustrates of Fig. 5 can be replaced by other voltage generator.At this, the voltage VNBST that produces in order to the voltage generator that replaces band gap voltage generation circuit 520 is associated with operating voltage VCC, the voltage V on itself and bit line BL _BLRelation can be expressed as mathematical expression (3):

$\left|V_{\mathrm{BL}}\right|=\frac{\mathrm{VNBST}\left(\mathrm{VCC}\right)\×C_{\mathrm{bst}}-\mathrm{VCC}\×C_{\mathrm{blc}}}{C_{\mathrm{blc}}+C_{\mathrm{bst}}+C_{\mathrm{bl}}}---\left(3\right)$

Wherein, C _blBe the capacitance on bit line.According to mathematical expression (3), can calculate mathematical expression (4) again:

$\frac{\∂\left|V_{\mathrm{BL}}\right|}{\∂\mathrm{VCC}}=\frac{C_{\mathrm{bst}}}{C_{\mathrm{blc}}+C_{\mathrm{bst}}+C_{\mathrm{bl}}}\frac{\∂\mathrm{VNBST}\left(\mathrm{VCC}\right)}{\∂\mathrm{VCC}}-\frac{C_{\mathrm{bl}}}{C_{\mathrm{blc}}+C_{\mathrm{bst}}+C_{\mathrm{bl}}}---\left(4\right)$

Can satisfy under the requirement of mathematical expression (5) at the voltage VNBST that voltage generator produces, under the state that operating voltage VCC rises, the voltage V on bit line BL _BLCan be effectively suppressed and do not increase.Satisfy mathematical expression (5) as follows:

$\frac{C_{\mathrm{bst}}}{C_{\mathrm{blc}}+C_{\mathrm{bst}}+C_{\mathrm{bl}}}\frac{\&PartialD;\mathrm{VNBST}\left(\mathrm{VCC}\right)}{\&PartialD;\mathrm{VCC}}<\frac{C_{\mathrm{bl}}}{C_{\mathrm{blc}}+C_{\mathrm{bst}}+C_{\mathrm{bl}}}---\left(5\right)$

Then please refer to Fig. 6, Fig. 6 illustrates the schematic diagram of the negative bit line signal generation device 600 of yet another embodiment of the invention.Negative bit line signal generation device 600 comprises capacitor C _bst, C1, discharge channel 610, voltage generator 620 and switch 630, wherein, capacitor C 1 is by the construction of transistor MN3 institute.Capacitor C _bstBe coupled between the negative end points NBST of promotion and bit line BL, and produce negative bit line signal NSBL on the end points that is coupled to bit line BL.Discharge channel 610 is coupled to the negative end points NBST that promotes.Discharge channel 610 promotes enable signal BSTEN to determine whether provide reference voltage GND to the negative end points NBST that promotes, in the present embodiment, reference voltage GND is ground voltage according to voltage.Voltage generator 620 is coupled to capacitor C 1, produces output voltage V N according to operating voltage VCC, and promotes enable signal BSTEN to determine whether provide output voltage V N that capacitor C 1 is charged according to voltage.630, switch is serially connected between coupling a little of voltage generator 620 and capacitor C 1 and bit line BL.Switch 630 promotes enable signal BSTEN with conducting or disconnects capacitor C 1 and capacitor C according to voltage _bstBetween annexation.

On details of operation, voltage generator 620 first provides the voltage that produces so that capacitor C 1 is charged.Wherein, the voltage that produces of voltage generator 620 is less than operating voltage VCC (for example equaling 1/3VCC).And after this charging operations was completed, switch 630 promoted enable signal BSTEN conducting electric capacity C1 and capacitor C according to voltage _bstBetween connection.Simultaneously, 620 of voltage generators stop providing the voltage that produces to capacitor C 1 according to voltage promotion enable signal BSTEN.Thus, capacitor C 1 and capacitor C _bstBetween carry out the operation that electric charge distributes.When if the voltage level of operating voltage VCC is higher, the electric charge that is stored in capacitor C 1 will be transferred into capacitor C _bstIn, and use the decline degree of the voltage that suppresses to make the negative bit line signal NSBL that the conducting because of discharge channel 610 descends.

In the present embodiment, discharge channel 610 comes construction by transistor MN1, and wherein, the control end receiver voltage of transistor MN1 promotes enable signal BSTEN, and its first end is coupled to the negative end points NBST that promotes, and its second end is coupled to reference voltage GND.630, switch is by the construction of transistor MN2 institute, and the control end receiver voltage of transistor MN2 promotes enable signal BSTEN, and its first end is coupled to bit line BL, and its second end is coupled to capacitor C 1.Subsidiary one carry be, MN2 is switched at transistor, and the magnitude of voltage of the output voltage V N that produces according to operating voltage VCC is during less than the critical voltage of transistor MN3, the capacitance of the capacitor C 1 of transistor MN3 institute construction is very little relatively, therefore can lower in the situation that the operating voltage VCC of low-voltage the repressed degree of decline degree of the voltage of negative bit line signal NSBL.Relative, the magnitude of voltage of the output voltage V N that produces at foundation operating voltage VCC is during greater than the critical voltage of transistor MN3, and capacitor C 1 rises, and the electric charge that is sent to bit line BL also rises thereupon.So the decline degree of the voltage of negative bit line signal NSBL can be effectively suppressed.

Please refer to Fig. 7, Fig. 7 illustrates the schematic diagram of the negative bit line signal generation device 700 of an embodiment more of the present invention.Negative bit line signal generation device 700 comprises capacitor C _bst, C1, discharge channel 710, voltage generator 720, switch 730 and reverser INV1, INV2 and INV3.In the present embodiment, discharge channel 710 is formed by a plurality of reverser INV4～INV6 serial connection, the input end receiver voltage of reverser INV4 wherein promotes enable signal BSTEN, and the output terminal of reverser INV6 transmits voltage and promotes the reverse signal of enable signal BSTEN to the negative end points NBST that promotes.That is to say, when voltage promotion enable signal BSTEN is high level voltage (for example equaling operating voltage VCC), discharge channel 710 provides and for example equals reference voltage GND (ground voltage) to the negative end points NBST that promotes.Switch 730 is made of transistor M3, and wherein, the control end of transistor M3 promotes enable signal BSTEN by reverser INV2, INV3 receiver voltage, and its first end coupling capacitance C1, and the second end is coupled to bit line BL.1 of capacitor C is for utilizing the transistor capacitance of transistor M1 institute construction, and its control end promotes the reverse signal of enable signal BSTEN by reverser INV1 receiver voltage, and its first end and the second end couple mutually with first end and the voltage generator 720 of transistor M3.

720 of voltage generators comprise the electric capacity of transistor M2, transmission gate TG0 and the construction of transistor M4 institute.The control end receiver voltage of transistor M2 promotes enable signal BSTEN, and its first end receives operating voltage VCC, and its second end is coupled to transmission gate TG0 and capacitor C 1.The first end of transistor M4 and the second termination are coupled to operating voltage VCC, and its control end is coupled to transmission gate TG0.When transmission gate according to the signal B1 that is produced by reverser INV2 and INV3 and B2 during conducting, operating voltage VCC can be by transmission gate TG0 to the formed electric capacity of transistor M4, and directly capacitor C 1 is charged, and the magnitude of voltage that makes the output voltage on end points PC equals n times of operating voltage VCC, wherein, the numerical value of n is determined by the grid capacitance value of transistor M1 and transistor M4.

In integrated operation, at first, make voltage generator 720 produce output voltage, namely the magnitude of voltage VPC of the output voltage on end points PC according to operating voltage VCC.Then, making voltage promote enable signal BSTEN transition is enabled status (high-voltage level), and disconnects the path of the output voltage that capacitor C 1 receiver voltage generator 720 produces, and turn-on transistor M3 simultaneously.When operating voltage VCC is the voltage of higher voltage value, and the magnitude of voltage VPC of the output voltage on end points PC (=n * VCC) can be higher than the critical voltage of transistor M1, part electric charge stored in capacitor C 1 can flow to capacitor C via transistor M3 _bstCouple on the end points of bit line BL the amplitude that descends to suppress negative bit line signal NSBL.Opposite, when operating voltage VCC is the voltage of lower voltage value, the magnitude of voltage VPC of the output voltage on end points PC (=n * VCC) can be lower than the critical voltage of transistor M1, this moment, the capacitance of capacitor C 1 can be very little, the fall of the negative bit line signal NSBL of unlikely impact.

Please refer to Fig. 8, Fig. 8 illustrates the schematic diagram of the storage arrangement 800 of one embodiment of the invention.Storage arrangement 800 can be static RAM, and storage arrangement 800 comprises a plurality of storage unit 801～80M and a plurality of negative bit line signal generation device 810～81N.Wherein, negative bit line signal generation device 810～81N is coupled to respectively bit line BL1～BLN and the BL1B～BLNB that storage unit 801～80M connects.Negative bit line signal generation device 610～61N can utilize arbitrary enforcement wherein of the negative bit line signal generation device 100～700 that earlier figures 1～Fig. 7 illustrates.And about bearing the implementation detail of bit line signal generation device 100～700, detailed explanation is arranged in the aforementioned embodiment, be not repeated.

In sum, the present invention provides a voltage negative the promotion on end points or bit line by voltage generator is set, and the voltage level when coming the stable negative bit line signal to produce by this voltage, make negative bit line signal not because of rising or the decline of operating voltage, change and produce significantly.

Although the present invention discloses as above with embodiment; so it is not to limit the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, therefore protection scope of the present invention is to be as the criterion with claim of the present invention.

Claims (19)

1. negative bit line signal generation device comprises:

One electric capacity is coupled between a negative promotion end points and a bit line, and this electric capacity is being coupled to generation one negative bit line signal on the end points of bit line;

One discharge channel is coupled in a reference voltage and should negatively promotes between end points, promotes enable signal with conducting or disconnection according to a voltage; And

One voltage generator promotes enable signal to determine whether provide a voltage to should negatively promoting end points according to this voltage;

Wherein, this is negative when promoting end points when this voltage generator provides the voltage to, and this discharge channel is disconnected, and on the end points of bit line, corresponding the generation should negative bit line signal being coupled to for this electric capacity.

2. negative bit line signal generation device as claimed in claim 1, wherein this voltage generator comprises a band gap voltage generation circuit.

3. negative bit line signal generation device as claimed in claim 1, wherein this voltage generator comprises:

One first switch, the one termination is received an operating voltage, and its other end provides a current controling signal, conducting or the disconnection according to an enabling signal of this first switch;

One charging current source couples this first switch, and a charging current that produces according to this current controling signal adjustment;

One second switch, one end couple this charging current source receiving this charging current, and its other end produces an end-point voltage, are controlled by the reverse signal of this enabling signal and conducting or disconnection;

One voltage drop element couples this second switch, receives and carries out step-down to produce a feedback voltage for this end-point voltage; And

One discharge current source, being serially connected in this first switch provides between the end points and this reference voltage of this current controling signal, is controlled by this feedback voltage to adjust a discharge current that is produced, and goes forward side by side to adjust this current controling signal.

4. negative bit line signal generation device as claimed in claim 3, wherein this first switch is a first transistor, has control end, first end and the second end, and its control end receives this enabling signal, its first end is connected to this operating voltage, and its second end produces this current controling signal.

5. negative bit line signal generation device as claimed in claim 3, wherein this charging current source comprises:

One transistor seconds has control end, first end and the second end, and its control end receives the reverse signal of this current controling signal, and its first end is connected to this operating voltage, and its second end produces this charging current.

6. negative bit line signal generation device as claimed in claim 3, wherein this second switch is one the 3rd transistor, has control end, first end and the second end, and its control end receives the reverse signal of this enabling signal, its first end is connected to this charging current source, and its second end produces this end-point voltage.

7. negative bit line signal generation device as claimed in claim 3, wherein this voltage drop element comprises:

One the 4th transistor has control end, first end and the second end, and its control end receives this operating voltage, and its first end receives this end-point voltage, and its second end produces this feedback voltage.

8. negative bit line signal generation device as claimed in claim 3, wherein this voltage drop element comprises:

One diode, its negative electrode produces this feedback voltage, and its anode receives this end-point voltage.

9. negative bit line signal generation device as claimed in claim 3, wherein this discharge current source is one the 5th transistor, has control end, first end and the second end, and its control end receives this feedback voltage, its first end is coupled to this first switch, and its second end is coupled to this reference voltage.

10. negative bit line signal generation device as claimed in claim 1 wherein also comprises:

One electric capacity of voltage regulation is serially connected between this bit line and this reference voltage.

11. negative bit line signal generation device as claimed in claim 1 wherein also comprises:

One reverser, its input end receive this voltage and promote enable signal; And

One electric capacity of voltage regulation is serially connected between the output terminal and this bit line of this reverser.

12. a negative bit line signal generation device comprises:

One first electric capacity is coupled between a negative promotion end points and a bit line, and this electric capacity is being coupled to this negative bit line signal of generation on the end points of this bit line;

One discharge channel is coupled to this negative end points that promotes, and promotes enable signal to determine whether provide a reference voltage to should negatively promoting end points according to a voltage;

One second electric capacity;

One voltage generator is coupled to this second electric capacity, produces an output voltage according to an operating voltage, and promotes enable signal to determine whether provide this output voltage that this second electric capacity is charged according to this voltage; And

One switch, be serially connected in this voltage generator and this second electric capacity couple a little and this bit line between, according to this voltage promote enable signal with conducting or disconnect this second electric capacity and this first electric capacity between annexation.

13. negative bit line signal generation device as claimed in claim 12, wherein this voltage generator comprises:

One the first transistor has first end, the second end and control end, and its first end receives an operating voltage, and its control end receives this voltage and promotes enable signal;

One transmission gate, one end are coupled to the second end of this first transistor, promote enable signal with conducting or disconnection according to this voltage; And

One the 3rd electric capacity is coupled in the end points that this operating voltage and this transmission gate do not couple this first transistor.

14. negative bit line signal generation device as claimed in claim 13, wherein the state of the conducting of this first transistor and this transmission gate or disconnection is identical.

15. negative bit line signal generation device as claimed in claim 12, wherein this discharge channel comprises:

N impact damper is serially connected in this negative promotion end points and this voltage and promotes between enable signal, and the reverse signal that described impact damper transmits this voltage promotion enable signal promoted end points to bearing, and wherein N is positive integer.

16. negative bit line signal generation device as claimed in claim 12, wherein this second electric capacity is a transistor seconds, have first end, the second end and control end, its first end and the second end are coupled to this voltage generator jointly, and its control end receives the reverse signal that this voltage promotes enable signal.

17. negative bit line signal generation device as claimed in claim 12, wherein this switch comprises:

One the 3rd transistor has first end, the second end and control end, and its first end is coupled to this second electric capacity, and its second end is coupled to this bit line, and its control end receives this voltage and promotes enable signal.

18. a storage arrangement has multiple bit lines, comprising:

A plurality of negative bit line signal generation devices, described negative bit line signal generation device is coupled to described bit line, respectively should comprise by negative bit line signal generation device:

One electric capacity is coupled to a negative promotion end points and respectively between this bit line, this electric capacity be coupled on the end points of bit line this generation should negative bit line signal;

One discharge channel is coupled in a reference voltage and should negatively promotes end points, promotes enable signal with conducting or disconnection according to a voltage;

One voltage generator promotes enable signal to determine whether provide a voltage to should negatively promoting end points according to this voltage;

Wherein, this is negative when promoting end points when this voltage generator provides the voltage to, and this discharge channel is disconnected, and on the end points of bit line, corresponding the generation should negative bit line signal being coupled to for this electric capacity.

19. a storage arrangement has a plurality of bit lines, comprising:

A plurality of negative bit line signal generation devices, described negative bit line signal generation device is coupled to described bit line, respectively should comprise by negative bit line signal generation device:

One first electric capacity is coupled to a negative promotion end points and respectively between this bit line, this electric capacity be coupled on the end points of this bit line this generation should negative bit line signal;

One discharge channel is coupled to this negative end points that promotes, and promotes enable signal to determine whether provide a reference voltage to should negatively promoting end points according to a voltage;

One second electric capacity;

One voltage generator is coupled to this second electric capacity, promotes enable signal to determine whether provide a voltage that this second electric capacity is charged according to this voltage;

One switch, be serially connected in this voltage generator and this second electric capacity couple a little and this bit line between, according to this voltage promote enable signal with conducting or disconnect this second electric capacity and this first electric capacity between annexation.

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