CN103117266A - Electric conduction plug and forming method - Google Patents
Electric conduction plug and forming method Download PDFInfo
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- CN103117266A CN103117266A CN2011103660739A CN201110366073A CN103117266A CN 103117266 A CN103117266 A CN 103117266A CN 2011103660739 A CN2011103660739 A CN 2011103660739A CN 201110366073 A CN201110366073 A CN 201110366073A CN 103117266 A CN103117266 A CN 103117266A
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Abstract
An electric conduction plugs comprises a semiconductor substrate, a gate structure which is positioned on the surface of the semiconductor substrate, a plurality of nanowire active areas and a dielectric layer, grooves, dielectric materials, and electric conduction plugs, wherein the plurality of nanowire active areas are penetrated through the gate structure and are parallel to the semiconductor substrate, the dielectric layer is positioned on the surface of the semiconductor substrate and covers the gate structure and the nanowire active areas, the interval spaces among the nanowire active areas are fully filled by the dielectric layer, the grooves are positioned on two sides of the gate structure, inclined angles are arranged on the side walls of the grooves, the grooves are enables the nanowire active areas to be provided with etched sections, the dielectric materials are used for filling the grooves, the electric conduction plugs are arranged in the dielectric materials, and each electric conduction plug is connected with the corresponding nanowire active area. Due to the fact that the etched sections, with the different heights, of the nanowire active areas are arrayed in a ladder mode, the electric conduction plugs are connected between two ends of each nanowire active area and a metal mutual-connection layer, voltages and currents at two ends of each nanowire active area can be controlled, and improvement of device performance is benefited.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of conductive plunger that is connected with the nano wire active area and formation method.
Background technology
Along with the development of semiconductor process techniques, rear grid (gate-last) technique is widely applied, and obtains desirable threshold voltage, improves device performance.But the characteristic size (CD when device, Critical Dimension) when further descending, even grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also can't satisfy the demand to device performance, and multigate device is paid close attention to widely as alternative having obtained of conventional device.
Multiple gate field effect transistor (Multi-Gate Field Effect Transistor, MuGFET) is a kind of common multigate device, and Fig. 1 shows the perspective view of a kind of multiple gate field effect transistor of prior art.As shown in Figure 1, comprise: Semiconductor substrate (not shown), be positioned at a plurality of parallel grid 10 on described Semiconductor substrate, some are passed described grid 10 with the parallel plane nano wire active area 12 of Semiconductor substrate, the nano wire active area 12 that is positioned at grid 10 is enclosed with gate dielectric layer (not shown), covers the dielectric layer 20 on described Semiconductor substrate, grid 10 surfaces.For described multiple gate field effect transistor, each root nano wire active area 12, grid 10 and gate dielectric layer consist of a MOS transistor, and namely a multiple gate field effect transistor has several channel regions that equate with nano wire active area quantity.Because channel thickness and the width of nano wire active area are very little, the grid that makes multiple gate field effect transistor is more near the various piece of raceway groove, help the enhancing of transistor gate modulation capability, and adopt and enclose the grid structure, grid is modulated raceway groove from all directions, improve Sub-Threshold Characteristic, therefore can well suppress short-channel effect.And for the raceway groove of nano wire, due to quantum limitation effect, the charge carrier in raceway groove is away from surface distributed, carrier transport be subjected to surface scattering and the channel laterally electric field influence little, can obtain higher mobility, be conducive to increase drive current, improve device performance.
About more detailed contents of multigate device, see also the american documentation literature that publication number is US2006/0216897A1 and US2010/0068862A1.
But nano wire active area and Semiconductor substrate plane parallel due to described multiple gate field effect transistor, the metal interconnecting layer of described nano wire active area and existing technique is carried out electricity interlinkage need to be perpendicular to the conductive plunger of nano wire active area, can make the nano wire active area electricity of differing heights link together but directly form conductive plunger, can not independently control MOS transistor corresponding to each root nano wire active area.
Summary of the invention
The problem that the present invention solves is to provide a kind of conductive plunger that is connected with the nano wire active area and formation method, makes the two ends of each root nano wire active area all be connected with the metal interconnecting layer electricity of existing technique.
For addressing the above problem, the embodiment of the present invention provides a kind of conductive plunger, comprising:
Semiconductor substrate, be positioned at the grid structure of described semiconductor substrate surface, run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be positioned at the dielectric layer of described semiconductor substrate surface and overlies gate structure and nano wire active area, described dielectric layer is filled the clearance space between full nano wire active area;
Be positioned at the groove of described grid structure both sides, the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section;
Fill the dielectric material of full described groove;
Be positioned at the conductive plunger of described dielectric material, each conductive plunger is connected with corresponding nano wire active area.
Optionally, be positioned at the stepped arrangement of etching section of nano wire active area of the differing heights of recess sidewall.
Optionally, the length of the described nano wire active area of differing heights is up constantly successively decreased from Semiconductor substrate, makes the conductive plunger that is connected with the nano wire active area of described differing heights not overlap each other.
Optionally, in described nano wire active area doped with foreign ion.
Optionally, described groove cross section is class semicircle or inverted trapezoidal.
Optionally, the bottommost of described groove is larger to the distance on dielectric layer surface than minimum nano wire active area to the distance on dielectric layer surface
Optionally, also comprise, be positioned at the etching barrier layer of described groove surfaces.
Optionally, the material of described etching barrier layer is silicon nitride or silicon oxynitride.
Optionally, described etching barrier layer has compression or tension stress.
Optionally, the scope of the difference in height between the described nano wire active area of adjacent height and described nano wire active area diameter ratio is 1: 1～5: 1.
Optionally, described nano wire active area is positioned at 0%～50% position of dielectric layer gross thickness.
Optionally, the profile graphics of described nano wire active area is circle, triangle, square, rectangle.
The embodiment of the present invention also provides a kind of formation method of conductive plunger, comprising:
Semiconductor substrate is provided, be formed with grid structure on described Semiconductor substrate and run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be formed with the dielectric layer that covers described grid structure and nano wire active area at described semiconductor substrate surface, described dielectric layer is filled the clearance space between full nano wire active area;
Dielectric layer and nano wire active area to described grid structure both sides carry out etching, form groove, and the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section;
Fill full dielectric material in described groove;
Form through hole in dielectric material in described groove, described through hole exposes the etching section of corresponding nano wire active area;
Form conductive plunger in described through hole.
Optionally, the cross section of described groove is class semicircle or inverted trapezoidal.
Optionally, the technique that forms described groove comprises: form mask layer on described dielectric layer surface, form opening in described mask layer, take mask layer with described opening as mask, described dielectric layer and nano wire active area are carried out etching.
Optionally, the length of described opening is equal to or greater than the described Breadth Maximum that runs through all nano wire active areas of same grid structure.
Optionally, when the cross section of described groove is class when semicircle, described opening is to the distance of the grid structure radius greater than described groove.
Optionally, described cross section is the semicircular groove of class etching technics is isotropic etching.
Optionally, described isotropic etching technics is wet-etching technology.
Optionally, described isotropic etching technics is plasma etching.
Optionally, described wet-etching technology specifically comprises: described dielectric layer is carried out the first wet etching, and Formation cross-section is the semicircular groove of class; The described nano wire active area that exposes in described groove is carried out the second wet etching; Dielectric layer in described groove is carried out the 3rd wet etching, until expose the etching section of described nano wire active area.
Optionally, described wet-etching technology specifically comprises: utilizing etching selection ratio to described dielectric layer and nano wire active area is that the etching solution of 1: 1 carries out wet etching to described dielectric layer and nano wire active area simultaneously, and Formation cross-section is the semicircular groove of class.
Optionally, described etching selection ratio to dielectric layer and nano wire active area is that the etching solution of 1: 1 is the wherein mixed solution of at least two kinds of hydrofluoric acid, ammoniacal liquor, ammonium fluoride, nitric acid.
Optionally, described etching selection ratio to dielectric layer and nano wire active area is that the etching solution of 1: 1 is the mixed solution of hydrofluoric acid and nitric acid, and the scope of the volume ratio of described hydrofluoric acid and nitric acid is 1: 3～1: 9.
Optionally, also comprise: form etching barrier layer in described groove surfaces.
Optionally, the method that forms described through hole comprises: dry etching is for the first time carried out in the position to the etching section of described nano wire active area corresponding dielectric layer surface, until expose described etching barrier layer; Described etching barrier layer is carried out dry etching for the second time, until expose the etching section of described nano wire active area.
Optionally, the etching barrier layer of described formation has tension stress or compression.
Optionally, the method for the described opening of formation comprises that photoetching process, nano-imprint process, self-assembly process are wherein a kind of.
Optionally, described mask layer is that photoresist layer, hard mask layer, copolymer, polymer are wherein a kind of.
Optionally, in described nano wire active area doped with foreign ion.
Compared with prior art, the embodiment of the present invention has the following advantages:
In embodiments of the present invention, utilize etching technics to form the groove that sidewall has the angle of inclination in the dielectric layer of described grid structure both sides, described groove makes described nano wire active area have the etching section, then fill full dielectric material in described groove, and forming conductive plunger in dielectric material, each conductive plunger is connected with corresponding nano wire active area.Because the sidewall of groove has the angle of inclination, the stepped arrangement of etching section of the described nano wire active area of differing heights, there is conductive plunger electricity to be connected between every nano wire active area two ends and metal interconnecting layer, can control voltage, the electric current at every nano wire active area two ends, be conducive to improve device performance.
Further, described groove surfaces is formed with etching barrier layer, when dielectric layer being carried out etching formation through hole, due to the barrier effect of etching barrier layer, all can stop at described etching barrier layer surface corresponding to the first dry etching of different depth, recycling the second dry etching carries out etching to described etching barrier layer surface, form through hole, only need to carry out a photoetching process, twice dry etching, reduced processing step, and etch period be controlled easily.
Description of drawings
Fig. 1 is the perspective view of a kind of multiple gate field effect transistor of prior art;
Fig. 2 to Fig. 8 is the structural representation of forming process of the multiple gate field effect transistor of prior art;
Fig. 9 is the schematic flow sheet of the conductive plunger formation method of the embodiment of the present invention;
Figure 10 to Figure 18 is the cross-sectional view of the conductive plunger forming process of the embodiment of the present invention.
Embodiment
The method that prior art forms described multiple gate field effect transistor specifically comprises:
Please refer to Fig. 2, Semiconductor substrate 30 be provided, alternately form germanium silicon layer 31, silicon layer 32 on described Semiconductor substrate 30, in described silicon layer 32 doped with foreign ion;
Please refer to Fig. 3 and 4, described Fig. 4 is the perspective view of Fig. 3, and germanium silicon layer 31, the silicon layer 32 of subregion carried out etching, forms the germanium silicon layer 31 of fin-shaped, the laminated construction of silicon layer 32;
Please refer to Fig. 5, described germanium silicon layer 31 is carried out wet etching, remove the germanium silicon layer 31 in the laminated construction of germanium silicon layer 31, silicon layer 32 of fin-shaped, the silicon layer between described germanium silicon layer 31 forms nano wire active area 33, forms gate dielectric layers (not shown) on described nano wire active area 33 surfaces;
Please refer to Fig. 6, form polycrystalline silicon material 34 in the zone with nano wire active area 33, described polycrystalline silicon material 34 covers nano wire active area 33 and fills the completely clearance space between nano wire active area 33;
Please refer to Fig. 7, utilize chemical wet etching technique to carry out etching to part polycrystalline silicon material 34, and polycrystalline silicon material 34 and the gate dielectric layer on nano wire active area 33 surfaces that utilize wet etching to remove not to be covered by grid structure, expose nano wire active area 33, form grid structure 35;
Please refer to Fig. 8, at described grid structure 35, nano wire active area 33 surface formation interlayer dielectric layers 36, described interlayer dielectric layer 36 is filled the interval region between full described nano wire active areas 33.
nano wire active area and Semiconductor substrate plane parallel due to the multiple gate field effect transistor that utilizes said method to form, described nano wire active area is not easy to be connected with the metal interconnecting layer electricity that has technique now, even utilize conductive plunger to be connected, the nano wire active area two ends that each root runs through grid structure can not independently be connected with metal interconnecting wires, need several nano wire active areas to share same conductive plunger, for this reason, the inventor is through research, a kind of conductive plunger and formation method are provided, described conductive plunger comprises: Semiconductor substrate is provided, be formed with grid structure on described Semiconductor substrate and run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be formed with the dielectric layer that covers described grid structure and nano wire active area at described semiconductor substrate surface, described dielectric layer is filled the clearance space between full nano wire active area, dielectric layer and nano wire active area to described grid structure both sides carry out etching, form groove, and the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section, fill full dielectric material in described groove, form through hole in dielectric material in described groove, described through hole exposes the etching section of corresponding nano wire active area, form conductive plunger in described through hole.Because the sidewall of described groove has the angle of inclination, and the described groove of etching makes described nano wire active area have the etching section, when the height of described nano wire active area not simultaneously, the stepped arrangement of etching section of described nano wire active area, make described etching section not overlapping in the position of the surperficial correspondence of dielectric layer, carry out etching in position corresponding to described dielectric layer surface and form conductive plunger, described conductive plunger can electricity connect described nano wire active area and the metal interconnecting layer that is positioned at described dielectric layer surface.Utilize conductive plunger formation method and the corresponding conductive plunger of the embodiment of the present invention that described nano wire active area is connected with the metal interconnecting layer electricity of existing technique, and because every nano wire active area two ends all are connected with metal interconnecting layer electricity, can control voltage, the electric current at every nano wire active area two ends, be conducive to improve device performance.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
In embodiments of the present invention, described height is on the direction perpendicular to described semiconductor substrate surface, the distance between object and described semiconductor substrate surface.Wherein, the higher position is relative position away from described semiconductor substrate surface, and lower position is the position of relatively close described semiconductor substrate surface.
At first the embodiment of the present invention provides a kind of conductive plunger formation method, please refer to Fig. 2, and the schematic flow sheet for the conductive plunger formation method of the embodiment of the present invention comprises:
Step S101, Semiconductor substrate is provided, be formed with grid structure on described Semiconductor substrate and run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be formed with the dielectric layer that covers described grid structure and nano wire active area at described semiconductor substrate surface, described dielectric layer is filled the clearance space between full nano wire active area;
Step S102 carries out etching to dielectric layer and the nano wire active area of described grid structure both sides, forms groove, and the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section;
Step S103 fills full dielectric material in described groove;
Step S104 forms through hole in the dielectric material in described groove, and described through hole exposes the etching section of corresponding nano wire active area;
Step S105 forms conductive plunger in described through hole.
Figure 10 to Figure 18 is the cross-sectional view of the conductive plunger forming process of the embodiment of the present invention.
Please refer to Figure 10, Semiconductor substrate 100 is provided, be formed with grid structure 110 on described Semiconductor substrate 100 and run through described grid structure 110 and the some nano wire active areas 120 parallel with Semiconductor substrate 100, be formed with the dielectric layer 130 that covers described grid structure 110 and nano wire active area 120 on described Semiconductor substrate 100 surfaces, described dielectric layer 130 is filled the clearance space between full nano wire active areas 120.
Described Semiconductor substrate 100 is wherein a kind of of silicon substrate, silicon-Germanium substrate, germanium substrate, and described Semiconductor substrate 100 surfaces can also form some epitaxial loayers or strained silicon layer to improve the electric property of semiconductor device.
Described Semiconductor substrate 100 surfaces are formed with several grid structures 110, the bottom of described grid structure 110 and described Semiconductor substrate 100 Surface Contacts, and some nano wire active areas 120 parallel with Semiconductor substrate 100 run through described grid structure 110.In the present embodiment, described adjacent grid structure 110 is parallel, makes described nano wire active area 120 vertical with grid structure 110, is conducive to control the length of channel region.Described nano wire active area 120 runs through between the part of described grid structure 110 and described grid structure 110 and is formed with gate dielectric layer (not shown), gate dielectric layer, the grid structure 110 on described nano wire active area 120, described nano wire active area 120 surfaces consist of a MOS transistor, the nano wire active area 120 that is positioned at described grid structure 110 both sides forms the source of MOS transistor/drain electrode, and the part that described nano wire active area 120 runs through described grid structure 110 is the channel region of MOS transistor.Part and described nano wire active area 120 that described nano wire active area 120 runs through described grid structure 110 run through the part of dielectric layer 130 all doped with foreign ion, to reduce the resistance of channel region, improve the threshold voltage of MOS transistor, improve the mobility of charge carrier.In other embodiments, the part that described nano wire active area 120 runs through described grid structure 110 can undope, to reduce the discrete distribution of impurity and Coulomb scattering in raceway groove.And pass through the type of the doping ion of the described nano wire active area 120 of change, controlling the final multiple gate field effect transistor that forms is nmos pass transistor or PMOS transistor.Wherein, the profile graphics of described nano wire active area 120 is circle, triangle, square, rectangle etc.
Described dielectric layer 130 is positioned at described Semiconductor substrate 100 surfaces and covers described grid structure 110 and nano wire active area 120, and described dielectric layer 130 is filled the clearance space between full nano wire active area 120.In subsequent technique, at described dielectric layer 130 surface formation metal interconnecting layers.Described nano wire active area 120 utilizes described conductive plunger, metal interconnecting layer to be connected with external circuit electricity.
The material of described grid structure 110 is the compound of polysilicon, metal or polysilicon and metal, the material of described gate dielectric layer is silica or high K dielectric material, the material of described nano wire active area 120 is silicon, germanium silicon or germanium etc., the material of described dielectric layer 130 is silica, tetraethoxysilane, silicon nitride, wherein one or more of low-K material, and described low-K material comprises agraphitic carbon, porous material etc.
In other embodiments, described grid structure is positioned at described dielectric layer, make the bottom of described grid structure not contact with Semiconductor substrate, some nano wire active areas parallel with Semiconductor substrate run through described grid structure and are positioned at the dielectric layer of described grid structure both sides.
In other embodiments, described grid structure sidewall also is formed with side wall, and described side wall can avoid that described grid structure sidewall by Implantation or injury, affects device performance when forming the nano wire active area of impurity doping.
Please refer to Figure 11, at described dielectric layer 130 surface formation mask layers 140, at the interior formation opening 145 of described mask layer 140.
Described mask layer 140 with opening 145 is used to follow-up etching Formation cross-section to provide mask for the semicircular groove of class, described cross section is that the class semicircle comprises semicircle, half elliptic etc., in embodiments of the present invention, described groove is that the cross section is semicircular groove.
In other embodiments, the groove of follow-up formation is that the cross section is the groove of inverted trapezoidal, and is corresponding, forms mask layer with opening on described dielectric layer surface and provides mask for the etching Formation cross-section for the groove of inverted trapezoidal.
In the present embodiment, the length of described opening 145 and grid structure 110 equal in length, make and utilize described opening 145 to be equal to or greater than the length of described grid structure 110 for the length of the semicircular groove of class for the cross section that mask carries out wet etching formation, the nano wire active area 120 that the is positioned at described grid structure 110 both sides disconnection that can all be etched makes described nano wire active area 120 have the etching section.Wherein, the length of the grid structure of mentioning in the embodiment of the present invention and the length of opening refer to the distance on direction with the channel region perpendicular direction, i.e. length on grid structure longer sides direction.
In other embodiments, the length of described opening 145 is equal to or greater than the Breadth Maximum of all nano wire active areas 120 that run through same grid structure 110, described width is the distance on grid structure 110 length directions, make and utilize described opening 145 to be equal to or greater than the described Breadth Maximum that runs through all nano wire active areas 120 of same grid structure 110 for mask carries out cross section that wet etching forms for the length of the semicircular groove of class, the nano wire active area 120 that the is positioned at described grid structure 110 both sides disconnection that can all be etched.
Easy for accompanying drawing, described opening 145 shown in Figure 11 is the position between adjacent grid structure 110 only, but in specific embodiment, described opening 145 is positioned at the both sides of a grid structure 110, make the conductive plunger of follow-up formation be connected with the two ends of the described nano wire active area 120 that runs through described grid structure 110, realize voltage, the electric current at every nano wire active area two ends are controlled.
Due to the mask layer 140 with described opening 145 be Formation cross-section be the semicircular groove of class, described opening 145 is to the distance of the grid structure 110 of any side radius greater than described groove, make after forming described cross section and being the semicircular groove of class, the edge of described recess edge and grid structure also has certain distance, avoids etching technics to described grid structure 110 injuries.
Described mask layer 140 can be wherein a kind of for photoresist layer, hard mask layer, copolymer, polymer.
When described mask layer 140 is photoresist layer, the formation technique of described mask layer 140 is photoetching process, comprise: at described dielectric layer surface formation photoresist film (not shown), described photoresist film is carried out exposure imaging, form the mask layer 140 with opening 145.
When described mask layer 140 was hard mask layer, the formation technique of described mask layer 140 was photoetching and etching technics, comprising: at the described dielectric layer 130 hard mask films of surface formation, described hard mask film is silicon nitride, silicon oxynitride, metal etc.; Form photoresist film at described hard mask film surface, described photoresist film is carried out exposure imaging, form the photoresist layer of the figure with opening 145; Take the photoresist layer of described figure with opening 145 as mask, described hard mask film is carried out dry etching, until expose described dielectric layer 130, form the mask layer 140 with opening 145.
when described mask layer 140 is polymer, the formation technique of described mask layer 140 is nano-imprint process, be specially: at described dielectric layer 130 surface formation thin polymer films, described thin polymer film is polymethyl methacrylate (PMMS), the mould that utilization is formed with the figure of opening 145 carries out hot padding to described polymethyl methacrylate film, carry out figure and shift, then form the polymeric layer with opening 145 with dry etching, perhaps at described dielectric layer 130 surface formation polymer, described polymer is the monomer solution of dimethyl silicone polymer (PDMS), the printing opacity die marks that utilization is formed with the figure of opening 145 arrives described polymer surfaces, described polymer is carried out ultraviolet exposure, the ultraviolet ray that sees through described mould makes polymer generation polymerization and the curing molding of imprinting area, carry out figure and shift, then form the polymeric layer with opening 145 with dry etching, perhaps described polymer is poured in the mould with certain figure, described polymer is the monomer solution of dimethyl silicone polymer (PDMS), by solidifying to form the thin polymer film with opening 145 figures, in described dielectric layer 130 surface gold-plating, described thin polymer film with opening 145 figures is placed on described gold-plated dielectric layer 130 surfaces, speckle with thiol solution between described thin polymer film with opening 145 figures and described gold-plated dielectric layer 130 surfaces, due to described thiol solution and the living reaction of golden hair, make the described described dielectric layer of formation 130 surfaces, thin polymer film self assembly ground with opening 145, and the gold thin film of utilizing wet etching to remove to expose.
When described mask layer 140 is copolymer, the formation technique of described mask layer 140 is self assembly (DSA) technique, comprise: at described dielectric layer 130 surface formation block copolymers, described copolymer comprises bi-material, a kind of shape and size of material are corresponding to the figure of described opening 145, the shape and size of another kind of material realize self assembly corresponding to all the other zones of described mask layer 140 by certain reaction condition, form the copolymer film with opening 145.in the present embodiment, described copolymer is polystyrene and 4-vinylpridine block copolymer (PS-b-P4VP), described polystyrene and 4-vinylpridine block copolymer layer comprise poly 4 vinyl pyridine and polystyrene, the shape and size of described polystyrene are corresponding to described opening 145, the shape and size of described poly 4 vinyl pyridine are corresponding to all the other zones of described mask layer 140, described polystyrene and 4-vinylpridine block copolymer layer are exposed in the atmosphere of tetraethoxysilane (TEOS) and steam, because the pyridine of poly 4 vinyl pyridine is easy to by protonated (protonated), and protonated poly 4 vinyl pyridine can be used as the catalyst of TEOS hydrolysis, therefore at described poly 4 vinyl pyridine surface formation silicon oxide layer, take described silicon oxide layer as mask, described polystyrene is carried out etching, formation has the mask layer 140 of opening 145.
Please refer to Figure 12, dielectric layer 130 and the nano wire active area 120 of described grid structure 110 both sides carried out etching, Formation cross-section is the semicircular groove 135 of class, and described groove 135 makes described nano wire active area 120 have the etching section.
In order to make described nano wire active area 120 to be connected with metal interconnecting layer electricity, described nano wire active area 120 need to be connected with conductive plunger, make described nano wire active area 120 be connected with metal interconnecting layer electricity by described conductive plunger.And for make each root nano wire active area 120 can with metal interconnecting layer independently electricity be connected, the two ends that each root need to be run through the nano wire active area 120 of described grid structure 110 are connected with conductive plunger, but because multiple gate field effect transistor of the prior art is formed with many nano wire active areas 120, described nano wire active area 120 is matrix usually to be arranged, and makes to exist some nano wire active areas 120 to be positioned on same longitudinal direction.Please refer to Figure 12, in the present embodiment, nano wire active area 121,122,123 is positioned on same direction perpendicular to semiconductor substrate surface, if when being connected with nano wire active area 121 by the conductive plunger perpendicular to the dielectric layer plane, described conductive plunger also can be connected with nano wire active area 122,123, make a conductive plunger be connected with 3 nano wire active areas 121,122,123 electricity, can not control independently MOS transistor corresponding to each root nano wire active area.Therefore described nano wire active area 120 need to be formed the etching section of diverse location, described etching section is used for being connected with conductive plunger electricity in subsequent technique.When described nano wire active area 120 is positioned at differing heights, the stepped arrangement of etching section of the nano wire active area 120 of described differing heights.The nano wire active area that is positioned at the higher position is shorter in the length of the dielectric layer 130 of described grid structure both sides than the nano wire active area that is positioned at lower position, when corresponding nano wire active area was connected, the conductive plunger that is connected with the nano wire active area of described differing heights did not overlap each other when described conductive plunger.
In order to obtain described stair-stepping etching section, need to carry out etching to dielectric layer and the nano wire active area of described grid structure both sides, form the groove that sidewall has the angle of inclination.Described groove 135 is that the semicircular groove of class or cross section are the groove of inverted trapezoidal for the cross section.In embodiments of the present invention, described groove 135 is semicircular groove for the cross section.
In embodiments of the present invention, adopt isotropic etching technics to carry out etching to described dielectric layer 130 and nano wire active area 120, Formation cross-section is the semicircular groove 135 of class, described cross section is that sidewall and the Semiconductor substrate plane of the semicircular groove 135 of class has the angle of inclination, makes the stepped arrangement of etching section of described nano wire active area 120.
In other embodiments, adopt wet etching, dry etching or both immixtures to carry out etching to described dielectric layer and nano wire active area, Formation cross-section is the groove of inverted trapezoidal, described cross section is that sidewall and the Semiconductor substrate plane of the groove of inverted trapezoidal has the angle of inclination, makes the stepped arrangement of etching section of described nano wire active area.
In the present embodiment, described isotropic etching technics is wet etching, and in other embodiments, described isotropic etching technics is plasma etching.Because the etching group of wet etching solution or plasma can only contact with dielectric layer 130 by described opening 145, horizontal and vertical etching is carried out in position take described opening 145 as the center of circle, forming a cross section is semicircular groove 135, described groove 135 comprises half cylindrical part and 1/4th spherical parts that are positioned at described half-cylindrical two bottom surfaces, and wherein the position of the profile graphics in Figure 12 is corresponding to described half-cylindrical part.Disconnect formation etching section in order to make described nano wire active area 120 all be etched, the etching radius of described groove 135 is greater than the distance of minimum nano wire active area to the dielectric layer surface, in the present embodiment, to be the minimum nano wire active area 121 of the radius ratio of the semicircular groove 135 of class large to the distance on dielectric layer 130 surfaces in described cross section
In other embodiments, the bottommost of described groove 135 is larger to the distance on dielectric layer 130 surfaces than minimum nano wire active area 120 to the distance on dielectric layer 130 surfaces
Too little for fear of the distance between the conductive plunger of follow-up formation, particularly when the difference in height of the nano wire active area 120 that is positioned at same longitudinal direction is large not, more easily make the distance between the conductive plunger of follow-up formation too little, make the location overlap of conductive plunger, therefore, be positioned at the difference in height of nano wire active area 120 of same longitudinal direction greater than the diameter of described nano wire active area 120, the difference in height between the described nano wire active area of adjacent height and the scope of described nano wire active area diameter ratio are 1: 1～5: 1.
When described nano wire active area 120 is positioned at 50%～100% position of dielectric layer 130 gross thickness, even the difference in height between the described nano wire active area of described adjacent height is enough large, distance between the conductive plunger of follow-up formation is still too little, make the location overlap of conductive plunger, therefore, described nano wire active area 120 is positioned at 0%～50% position of dielectric layer 130 gross thickness.0% position of described dielectric layer 130 gross thickness is described Semiconductor substrate 100 surfaces, and 100% position of described dielectric layer 130 gross thickness is described dielectric layer 130 surfaces.
Utilizing wet etching to form described cross section comprises for the concrete technology of the semicircular groove 135 of class: utilizing etching selection ratio to described dielectric layer 130 and nano wire active area 120 is that the etching solution of 1: 1 carries out wet etching to described dielectric layer 130 and nano wire active area 120 simultaneously, and Formation cross-section is semicircular groove 135.Because described etching solution is 1: 1 to the etching selection ratio of described dielectric layer 130 and nano wire active area 120, make described dielectric layer 130 and nano wire active area 120 to be etched away simultaneously, the described groove 135 that forms makes described nano wire active area 120 have the etching section, makes final described different nano wire active areas 120 and the link position of conductive plunger be positioned at described semi-cylindrical arc-shaped surface.Described etching selection ratio to dielectric layer 130 and nano wire active area 120 is that the etching solution of 1: 1 is hydrofluoric acid, ammoniacal liquor, ammonium fluoride (NH
4F), the nitric acid mixed solution of at least two kinds wherein.In the present embodiment, described etching selection ratio to dielectric layer 130 and nano wire active area 120 is that the etching solution of 1: 1 is the mixed solution of hydrofluoric acid and nitric acid, and the scope of the volume ratio of described hydrofluoric acid and nitric acid is 1: 3～1: 9.
In another embodiment, utilizing wet etching to form described cross section comprises for the concrete technology of the semicircular groove 135 of class: please refer to Figure 13, described dielectric layer 130 is carried out the first wet etching, Formation cross-section is the semicircular groove 135 of class, and the described nano wire active area 120 of part is exposed in described groove 135; Please refer to Figure 14, the described nano wire active area 120 that exposes in described groove 135 is carried out the second wet etching; Please refer to Figure 12, the inner surface of described groove 135 is carried out the 3rd wet etching, until expose the etching section of described nano wire active area 120.utilize the first wet etching form described cross section for the semicircular groove 135 of class after, the described nano wire active area 120 of part is exposed and across at described groove 135 inner surfaces, when carrying out the second wet etching, because described the second wet etching is isotropism, the described nano wire active area 120 that comes out except etching, also can carry out etching to the nano wire active area 120 that contacts with groove 135 inner surfaces, after the described nano wire active area 120 that comes out is etched away, the described nano wire active area 120 of groove 135 inner surfaces that is positioned at is by over etching, the etching section of described nano wire active area 120 is in dielectric layer 130.When utilizing conductive plunger to be connected with described nano wire active area 120, may make described nano wire active area 120 not contact with conductive plunger, affect electricity and connect.For this reason, after carrying out the second wet etching, the inner surface of described groove 135 is carried out the 3rd wet etching, expose the etching section of described nano wire active area 120, be conducive to that in subsequent technique, conductive plunger is connected with nano wire active area electricity.Described the first wet etching is identical with the etching solution of the 3rd wet etching, is the etching solution that described dielectric layer 130 and nano wire active area 120 are had high etching selection ratio, for example hydrofluoric acid.The etching solution of the etching solution of described the second wet etching for described nano wire active area 120 and dielectric layer 130 are had high etching selection ratio, such as nitric acid, potassium hydroxide etc.In the present embodiment, using volume ratio is that the solution of the HF/HNO3 of 1: 6 carries out etching to described nano wire active area at the temperature of 23 ℃.
Please in the lump with reference to Figure 12 and Figure 15, remove described mask layer 140, form etching barrier layer 150 at described groove 135 inner surfaces.
The technique of removing described mask layer 140 comprises ashing, etching technics etc., after removing described mask layer 140, exposes described groove 135 and dielectric layer 130.
acting as of described etching barrier layer 150: follow-up when forming the through hole of different depth, all can stop at described etching barrier layer 150 surfaces when formerly the etching dielectric layer forms through hole, do not need the etch period of considering that different depth is corresponding, only need to guarantee that etching barrier layer 150 surfaces corresponding to the darkest through hole have exposed, then the etching barrier layer 150 of same thickness carried out etching, expose the etching section of corresponding described nano wire active area 120, only need to carry out one time photoetching process, twice dry etching, less processing step, and etch period is easily controlled.
Because described groove with sloped sidewall is that the cross section is that the semicircular groove of class or cross section are the groove of inverted trapezoidal, the cross sectional shape that is formed at the etching barrier layer of described groove surfaces also is class semicircle or inverted trapezoidal.Utilize depositing operation to form etching barrier layer on the surface of described groove, make the etching section of described nano wire active area be positioned at the lower surface of described etching barrier layer, to make the link position of the described different nano wire active areas of final formation and conductive plunger be positioned at described cross section be the lower surface of semicircular etching barrier layer or be positioned at the lower surface that the cross section is the etching barrier layer of inverted trapezoidal.Described depositing operation comprises low-pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD) etc., the material of described etching barrier layer 150 be silicon nitride, silicon oxynitride wherein one or both.In other embodiments, can also form the etching barrier layer 150 with compression or tension stress, by the carrier mobility in the described nano wire active area 120 of the crystal lattice constant change that changes described nano wire active area 120, can promote the performance of semiconductor device.
Please in the lump with reference to Figure 15 and Figure 16, at the full dielectric material 132 of the interior filling of described groove 135.
The material of described dielectric material 132 and dielectric layer 130 can be identical, also can be different.In the present embodiment, described dielectric material 132 is identical with the material of dielectric layer 130, is wherein a kind of of silica, tetraethoxysilane, low-K material.The formation technique of described dielectric material 132 comprises: adopt depositing operation to form dielectric material 132 in described groove 135 and dielectric layer 130 surfaces, described dielectric material 132 is filled completely described grooves 135; Described dielectric material 132 is carried out chemico-mechanical polishing, make described dielectric layer 130 have an even surface, described dielectric layer 130 comprises the dielectric material 132 that is positioned at described groove 135.
In another embodiment, after removing described mask layer, directly fill full dielectric material in described groove, need to not form etching barrier layer in described groove.
Please refer to Figure 17, form through hole 160 in the dielectric material 132 in described groove, described through hole 160 exposes the etching section of corresponding nano wire active area 120.
The stepped arrangement of etching section due to the nano wire active area 120 of described differing heights, the etching section of different nano wire active areas 120 position corresponding on dielectric layer 130 surface is different, by dry etching is carried out in described dielectric layer 130 corresponding positions, surface, form through hole 160, the bottom-exposed of described through hole 160 goes out the etching section of described nano wire active area 120.Because described through hole 160 is vertical with nano wire active area 120, the conductive plunger of follow-up formation can connect parallel metal interconnecting layer and nano wire active area 120, realizes that metal interconnecting layer is connected electricity and connects with the nano wire active area.
In the present embodiment, the technique that forms described through hole 160 comprises: at described dielectric layer 130 surface formation patterned photoresist layers (not shown), described photoetching offset plate figure is corresponding to the position of through hole 160 in dielectric layer 130; Take described patterned photoresist layer as mask, described dielectric layer 130 is carried out the first dry etching, described the first dry etching ends at described etching barrier layer 150; Described etching barrier layer 150 is carried out the second dry etching, form through hole 160, described through hole 160 exposes the etching section of described nano wire active area 120.Distance between the shape of the position of through hole and groove in described photoetching offset plate figure, the degree of depth, nano wire active area and dielectric layer surface, the Range-based between the nano wire active area, distance between the degree of depth by controlling described groove, nano wire active area and dielectric layer surface, the distance between the nano wire active area are determined the position of through hole in described photoetching offset plate figure.Although the degree of depth of the through hole 160 of different nano wire active area 120 correspondences is different, but owing to being formed with etching barrier layer 130 in the present embodiment medium layer 130, described the first dry etching all can stop at the surface of etching barrier layer 150, and then described etching barrier layer 150 is carried out the second dry etching, expose the etching section of described nano wire active area 120, only need to carry out a photoetching process, twice dry etching, reduced processing step, and etch period be controlled easily.
In other embodiments, when not being formed with etching barrier layer in described dielectric layer, because the degree of depth of through hole corresponding to the nano wire active area of differing heights is different, the through hole of different depth need to carry out respectively dry etching, and each through hole exposes the etching section of corresponding nano wire active area.
Please in the lump with reference to Figure 17 and Figure 18, at the interior formation conductive plunger 165 of described through hole 160.
The technique that forms described conductive plunger 165 comprises: adopt chemical vapor deposition method or physical gas-phase deposition described through hole 160 in and dielectric layer 130 surface formation conductive material layers, and described conductive material layer is carried out chemico-mechanical polishing until expose described dielectric layer 130, form conductive plunger 165.The material of described conductive material layer is the electric conducting materials such as copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride.Because the technique of described formation conductive plunger is those skilled in the art's known technology, be not described further at this.
Follow-up, at described dielectric layer 130 and conductive plunger 165 surface formation metal interconnecting layers, make the two ends of described each root nano wire active area to be connected with metal interconnecting layer electricity.Because every nano wire active area two ends all are connected with metal interconnecting layer electricity, can control voltage, the electric current at every nano wire active area two ends, be conducive to improve device performance.
In other embodiments, described metal interconnecting layer can utilize dual damascene process to form simultaneously together with conductive plunger, is those skilled in the art's known technology due to dual damascene process, is not described further at this.
Accordingly, the embodiment of the present invention also provides a kind of conductive plunger, please refer to Figure 18, comprising:
Be positioned at the groove 135 (please refer to Figure 12) of described grid structure 110 both sides, the sidewall of described groove 135 has the angle of inclination, and described groove 135 makes described nano wire active area 120 have the etching section;
Fill the dielectric material 132 of full described groove 135;
Be positioned at the conductive plunger 165 of described dielectric material 132, each conductive plunger 165 is connected with corresponding nano wire active area 120.
Concrete, described Semiconductor substrate 100 be wherein a kind of of silicon substrate, silicon-Germanium substrate, germanium substrate, and described Semiconductor substrate 100 surfaces can also form some epitaxial loayers or strained silicon layer with the electric property of raising semiconductor device.
Described Semiconductor substrate 100 surfaces are formed with several grid structures 110.The material of described grid structure 110 is the compound of polysilicon, metal or polysilicon and metal.The bottom of described grid structure 110 and described Semiconductor substrate 100 Surface Contacts, some nano wire active areas 120 parallel with Semiconductor substrate 100 run through described grid structure 110, and the material of described nano wire active area 120 is silicon, germanium silicon or germanium.The profile graphics of described nano wire active area 120 is circle, triangle, square, rectangle etc.
In other embodiments, described grid structure is positioned at described dielectric layer, make the bottom of described grid structure not contact with Semiconductor substrate, some nano wire active areas parallel with Semiconductor substrate run through described grid structure and are positioned at the dielectric layer of described grid structure both sides.
In other embodiments, described grid structure sidewall also is formed with side wall, and described side wall can avoid that described grid structure sidewall by Implantation or injury, affects device performance when forming the nano wire active area of impurity doping.
The two ends that some nano wire active areas 120 run through described grid structure 110 and the described nano wire active area 120 of each root are connected with conductive plunger 165.The difference in height of the nano wire active area 120 of adjacent height is greater than the diameter of described nano wire active area 120, and the difference in height between the described nano wire active area of adjacent height and the scope of described nano wire active area diameter ratio are 1: 1～5: 1.And described nano wire active area 120 is positioned at 0%～50% position of dielectric layer 130 gross thickness, and wherein, 0% position of described dielectric layer 130 gross thickness is described Semiconductor substrate 100 surfaces.
Described nano wire active area 120 runs through between the part of described grid structure 110 and described grid structure 110 and is formed with gate dielectric layer (not shown), and the material of described gate dielectric layer is silica or high K dielectric material.Gate dielectric layer, the grid structure 110 on described nano wire active area 120, described nano wire active area 120 surfaces consist of a MOS transistor, the nano wire active area 120 that is positioned at described grid structure 110 both sides forms the source of MOS transistor/drain electrode, and the part that described nano wire active area 120 runs through described grid structure 110 is the channel region of MOS transistor.Part and described nano wire active area 120 that described nano wire active area 120 runs through described grid structure 110 run through the part of dielectric layer 130 all doped with foreign ion, to reduce the resistance of channel region, improve the threshold voltage of MOS transistor, improve the mobility of charge carrier.In other embodiments, the part that described nano wire active area 120 runs through described grid structure 110 can undope, to reduce the discrete distribution of impurity and Coulomb scattering in raceway groove.And pass through the type of the doping ion of the described nano wire active area 120 of change, controlling the final multiple gate field effect transistor that forms is nmos pass transistor or PMOS transistor.
Described dielectric layer 130 is positioned at described Semiconductor substrate 100 surfaces and covers described grid structure 110 and nano wire active area 120.The material of described dielectric layer 130 is silica, tetraethoxysilane, silicon nitride, wherein one or more of low-K material, and described low-K material comprises agraphitic carbon, porous material etc.Also form groove 135 (please refer to Figure 12) in the dielectric layer 130 of described grid structure 110 both sides, the full dielectric material 132 of the interior filling of described groove 135, described dielectric material 132 can be the same or different with the material of dielectric layer 130.In the present embodiment, described dielectric material 132 is identical with the material of dielectric layer 130.
When being connected with the nano wire active area 120 that is positioned at differing heights for fear of a conductive plunger, described conductive plunger is connected with the nano wire active area 120 that is positioned at differing heights simultaneously, the nano wire active area 120 of described differing heights and the stepped arrangement of link position of conductive plunger.
Therefore, the sidewall of the groove 135 of described grid structure 110 both sides has the angle of inclination, makes when described nano wire active area is positioned at differing heights the stepped arrangement of etching section of the nano wire active area of described differing heights.The length of the described nano wire active area 120 of differing heights is up constantly successively decreased from Semiconductor substrate 100, makes the conductive plunger 165 that is connected with the nano wire active area 120 of described differing heights not overlap each other.Groove or cross section that described groove 135 is inverted trapezoidal for the cross section are the semicircular groove of class.
In embodiments of the present invention, being formed with the cross section in the dielectric layer 130 of described grid structure 110 both sides is the semicircular groove 135 of class (please refer to Figure 12), the full dielectric material 132 of the interior filling of described groove 135.The etching radius of described groove 135 is greater than the distance of minimum nano wire active area to the dielectric layer surface, and in the present embodiment, the minimum nano wire active area of the radius ratio of described semi-cylindrical groove 135 is large to the distance on dielectric layer 130 surfaces
In other embodiments, the bottommost of described groove is larger to the distance on dielectric layer surface than minimum nano wire active area to the distance on dielectric layer surface
In the present embodiment, please refer to Figure 18, described groove surfaces also is formed with etching barrier layer 150.Because described groove with sloped sidewall is that the cross section is that groove or the cross section of inverted trapezoidal is the semicircular groove of class, the etching barrier layer cross sectional shape that is formed at described groove surfaces also is class semicircle or inverted trapezoidal, makes the etching section of described nano wire active area be positioned at the lower surface of described etching barrier layer.The material of described etching barrier layer 150 be silicon nitride, silicon oxynitride wherein one or both.In other embodiments, described etching barrier layer 150 has compression or tension stress, change the interior carrier mobility of the described nano wire active area 120 of crystal lattice constant change of described nano wire active area 120 by effect of stress, can promote the performance of semiconductor device.
In other embodiments, be not formed with etching barrier layer in described dielectric layer, directly fill full dielectric material in described groove.The link position of described different nano wire active area 120 and conductive plunger 165 is positioned at the surface of the semi-cylindrical groove 135 of described class, stepped arrangement.
To sum up, in embodiments of the present invention, utilize etching technics to form the groove that sidewall has the angle of inclination in the dielectric layer of described grid structure both sides, described groove makes described nano wire active area have the etching section, then fill full dielectric material in described groove, and forming conductive plunger in dielectric material, each conductive plunger is connected with corresponding nano wire active area.Because the sidewall of groove has the angle of inclination, the stepped arrangement of etching section of the described nano wire active area of differing heights, there is conductive plunger electricity to be connected between every nano wire active area two ends and metal interconnecting layer, can control voltage, the electric current at every nano wire active area two ends, be conducive to improve device performance.
Further, described groove surfaces is formed with etching barrier layer, when dielectric layer being carried out etching formation through hole, due to the barrier effect of etching barrier layer, all can stop at described etching barrier layer surface corresponding to the first dry etching of different depth, recycling the second dry etching carries out etching to described etching barrier layer surface, form through hole, only need to carry out a photoetching process, twice dry etching, reduced processing step, and etch period be controlled easily.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (30)
1. a conductive plunger, is characterized in that, comprising:
Semiconductor substrate, be positioned at the grid structure of described semiconductor substrate surface, run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be positioned at the dielectric layer of described semiconductor substrate surface and overlies gate structure and nano wire active area, described dielectric layer is filled the clearance space between full nano wire active area;
Be positioned at the groove of described grid structure both sides, the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section;
Fill the dielectric material of full described groove;
Be positioned at the conductive plunger of described dielectric material, each conductive plunger is connected with corresponding nano wire active area.
2. conductive plunger as claimed in claim 1, is characterized in that, is positioned at the stepped arrangement of etching section of nano wire active area of the differing heights of recess sidewall.
3. conductive plunger as claimed in claim 2, is characterized in that, the length of the described nano wire active area of differing heights is up constantly successively decreased from Semiconductor substrate, makes the conductive plunger that is connected with the nano wire active area of described differing heights not overlap each other.
4. conductive plunger as described in the claims 1 to 3 any one, is characterized in that, described nano wire active area is interior doped with foreign ion.
5. conductive plunger as claimed in claim 1, is characterized in that, described groove cross section is class semicircle or inverted trapezoidal.
6. conductive plunger as claimed in claim 1, is characterized in that, the bottommost of described groove is larger to the distance on dielectric layer surface than minimum nano wire active area to the distance on dielectric layer surface
7. conductive plunger as claimed in claim 1, is characterized in that, also comprises, is positioned at the etching barrier layer of described groove surfaces.
8. conductive plunger as claimed in claim 7, is characterized in that, the material of described etching barrier layer is silicon nitride or silicon oxynitride.
9. conductive plunger as claimed in claim 7, is characterized in that, described etching barrier layer has compression or tension stress.
10. conductive plunger as claimed in claim 1, is characterized in that, the difference in height between the described nano wire active area of adjacent height and the scope of described nano wire active area diameter ratio are 1: 1～5: 1.
11. conductive plunger as claimed in claim 1 is characterized in that, described nano wire active area is positioned at 0%～50% position of dielectric layer gross thickness.
12. conductive plunger as claimed in claim 1 is characterized in that, the profile graphics of described nano wire active area is circle, triangle, square, rectangle.
13. the formation method of a conductive plunger is characterized in that, comprising:
Semiconductor substrate is provided, be formed with grid structure on described Semiconductor substrate and run through described grid structure and the some nano wire active areas parallel with Semiconductor substrate, be formed with the dielectric layer that covers described grid structure and nano wire active area at described semiconductor substrate surface, described dielectric layer is filled the clearance space between full nano wire active area;
Dielectric layer and nano wire active area to described grid structure both sides carry out etching, form groove, and the sidewall of described groove has the angle of inclination, and described groove makes described nano wire active area have the etching section;
Fill full dielectric material in described groove;
Form through hole in dielectric material in described groove, described through hole exposes the etching section of corresponding nano wire active area;
Form conductive plunger in described through hole.
14. the formation method of conductive plunger as claimed in claim 13 is characterized in that, the cross section of described groove is class semicircle or inverted trapezoidal.
15. the formation method of conductive plunger as claimed in claim 14, it is characterized in that, the technique that forms described groove comprises: at described dielectric layer surface formation mask layer, form opening in described mask layer, take mask layer with described opening as mask, described dielectric layer and nano wire active area are carried out etching.
16. the formation method of conductive plunger as claimed in claim 15 is characterized in that, the length of described opening is equal to or greater than the described Breadth Maximum that runs through all nano wire active areas of same grid structure.
17. the formation method of conductive plunger as claimed in claim 15 is characterized in that, when the cross section of described groove is class when semicircle, described opening is to the distance of the grid structure radius greater than described groove.
18. the formation method of conductive plunger as claimed in claim 15 is characterized in that, described cross section is that the etching technics of the semicircular groove of class is isotropic etching.
19. the formation method of conductive plunger as claimed in claim 18 is characterized in that, described isotropic etching technics is wet-etching technology.
20. the formation method of conductive plunger as claimed in claim 18 is characterized in that, described isotropic etching technics is plasma etching.
21. the formation method of conductive plunger as claimed in claim 19 is characterized in that, described wet-etching technology specifically comprises: described dielectric layer is carried out the first wet etching, and Formation cross-section is the semicircular groove of class; The described nano wire active area that exposes in described groove is carried out the second wet etching; Dielectric layer in described groove is carried out the 3rd wet etching, until expose the etching section of described nano wire active area.
22. the formation method of conductive plunger as claimed in claim 19, it is characterized in that, described wet-etching technology specifically comprises: utilizing etching selection ratio to described dielectric layer and nano wire active area is that the etching solution of 1: 1 carries out wet etching to described dielectric layer and nano wire active area simultaneously, and Formation cross-section is the semicircular groove of class.
23. the formation method of conductive plunger as claimed in claim 22 is characterized in that, described etching selection ratio to dielectric layer and nano wire active area is that the etching solution of 1: 1 is the wherein mixed solution of at least two kinds of hydrofluoric acid, ammoniacal liquor, ammonium fluoride, nitric acid.
24. the formation method of conductive plunger as claimed in claim 23, it is characterized in that, described etching selection ratio to dielectric layer and nano wire active area is that the etching solution of 1: 1 is the mixed solution of hydrofluoric acid and nitric acid, and the scope of the volume ratio of described hydrofluoric acid and nitric acid is 1: 3～1: 9.
25. the formation method of conductive plunger as claimed in claim 13 is characterized in that, also comprises: form etching barrier layer in described groove surfaces.
26. the formation method of conductive plunger as claimed in claim 25, it is characterized in that, the method that forms described through hole comprises: dry etching is for the first time carried out in the position to the etching section of described nano wire active area corresponding dielectric layer surface, until expose described etching barrier layer; Described etching barrier layer is carried out dry etching for the second time, until expose the etching section of described nano wire active area.
27. the formation method of conductive plunger as claimed in claim 25 is characterized in that the etching barrier layer of described formation has tension stress or compression.
28. the formation method of conductive plunger as claimed in claim 15 is characterized in that, the method that forms described opening comprises that photoetching process, nano-imprint process, self-assembly process are wherein a kind of.
29. the formation method of conductive plunger as claimed in claim 15 is characterized in that, described mask layer is that photoresist layer, hard mask layer, copolymer, polymer are wherein a kind of.
30. the formation method of conductive plunger as claimed in claim 13 is characterized in that, described nano wire active area is interior doped with foreign ion.
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