CN103107786A - Imbalance correcting method for pre-amplifier through controlling amplitude - Google Patents
Imbalance correcting method for pre-amplifier through controlling amplitude Download PDFInfo
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- CN103107786A CN103107786A CN2012105693835A CN201210569383A CN103107786A CN 103107786 A CN103107786 A CN 103107786A CN 2012105693835 A CN2012105693835 A CN 2012105693835A CN 201210569383 A CN201210569383 A CN 201210569383A CN 103107786 A CN103107786 A CN 103107786A
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Abstract
The invention discloses an imbalance correcting method for a pre-amplifier through controlling amplitude. The pre-amplifier comprises a first positive metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a third negative metal oxide semiconductor (NMOS) transistor, a fourth NMOS transistor and a fifth NMOS transistor. An on resistor of a load tube is adjusted through adjusting and controlling the amplitude of control signals on grids of the first PMOS transistor MP1 and the second PMOS transistor MP2 of the load tube, so that when imbalance occurs in a circuit and current at the left side and the right side is unequal, pressure drop from a power source to output nodes at the left side and the right side is equal, and therefore forward output voltage Voutp is equal to reverse output voltage Voutn and the imbalance is corrected. According to the imbalance correcting method for the pre-amplifier through controlling the amplitude, additional arrangement of a controllable capacitor or a metal oxide semiconductor (MOS) tube in a pre-amplifier circuit is not needed and therefore load effect on voltage of an input end can not be exerted.
Description
Technical field
The present invention relates to the analog circuit prime amplifier, particularly relate to a kind of imbalance bearing calibration of prime amplifier.
Background technology
The circuit structure diagram of prime amplifier comprises a PMOS transistor MP1 as shown in Figure 1, the 2nd PMOS transistor MP2, the 3rd nmos pass transistor MN3, the 4th nmos pass transistor MN4 and the 5th nmos pass transistor MN5.Wherein, the grid connection control signal CLKP of the one PMOS transistor MP1, the source electrode of the one PMOS transistor MP1 connects power vd D, and the drain electrode of a PMOS transistor MP1 is connected with the drain electrode of the 3rd nmos pass transistor MN3, the reverse output voltage V outn of the end output amplifier that is connected; The grid connection control signal CLKP of the 2nd PMOS transistor MP2, the source electrode of the 2nd PMOS transistor MP2 connects power vd D, the drain electrode of the 2nd PMOS transistor MP2 is connected with the drain electrode of the 4th nmos pass transistor MN4, the forward output voltage V outp of the end output amplifier that is connected; The source electrode of the 3rd nmos pass transistor MN3 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 3rd nmos pass transistor MN3 connects forward input voltage vin p; The source electrode of the 4th nmos pass transistor MN4 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 4th nmos pass transistor MN4 connects reverse input voltage vin n; The source ground GND of the 5th nmos pass transistor MN5, the grid connection control signal CLKP of the 5th nmos pass transistor MN5.Drive a PMOS transistor MP1, the 2nd PMOS transistor MP2 and the 5th nmos pass transistor MN5 control signal CLKP sequential chart as shown in Figure 2, its clock signal clk according to prime amplifier work produces, frequency is identical with the frequency of clock signal clk, the amplitude initial value is 0, and steady-state value is supply voltage value VDD.Control signal produces t1 moment input clock signal CLK in circuit, postpones a bit of time t2 after the moment, begins to produce control signal CLKP.
During this prime amplifier work, prime amplifier electric current occurs in circuit under the driving of control signal CLKP, complete the amplification to input signal (forward input voltage vin p deducts reverse input voltage vin n).During work, a PMOS transistor MP1 and the 2nd PMOS transistor MP2 are as the load pipe, and the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4 are as input pipe, and the 5th nmos pass transistor MN5 is as the offset that bias current is provided.If the left branch road of circuit (MP1-MN3 branch road) and right branch road (MP2-MN4 branch road) both sides full symmetric, when inputting equal forward input voltage vin p and reverse input voltage vin n, in circuit, the right and left current flowing equates, in circuit, forward output voltage V outp equals reverse output voltage V outn, and do not exist imbalance in circuit this moment.Yet, under practical situation, the impossible full symmetric in circuit left and right, in circuit, for example the size of a PMOS transistor MP1 and the 2nd PMOS transistor MP2 is unequal for the mismatch of components and parts, perhaps the size of the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4 is unequal, and these factors all can cause occurring in amplifier offset voltage, when input voltage vin p=Vinn, the electric current that the right and left flows through is unequal, and in output voltage, Vinp is not equal to Vinn.Occur to reduce prime amplifier to the resolution capability of input signal after imbalance.As prevent large device as the part of dynamic comparer, and then reduced the resolution capability of dynamic comparer to input signal.
In order to proofread and correct the offset voltage that exists in the large device of prevention, can be connected the controllable capacitor array with Voutn at the output node Voutp of prime amplifier, by the size reduction offset voltage of regulating capacitor array capacitor.Also can at the two ends paralleling MOS pipe of input pipe the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4, reduce offset voltage by the gate bias voltage of regulating metal-oxide-semiconductor.Yet in the method that these two kinds are reduced offset voltages, the metal-oxide-semiconductor that is connected to the controllable capacitor of prime amplifier output node or is connected in parallel on input pipe both sides all can produce load effect to output voltage V outp and Voutn, thereby reduces the speed of prime amplifier.As prevent large device as the part of dynamic comparer, and then can reduce the speed of comparator.
Summary of the invention
Technical problem to be solved by this invention is: make up above-mentioned the deficiencies in the prior art, a kind of prime amplifier is proposed by the imbalance bearing calibration of span of control limit of control, can proofread and correct the offset voltage in prime amplifier, can not cause load effect to input terminal voltage simultaneously.
Technical problem of the present invention is solved by following technical scheme:
A kind of prime amplifier is by the imbalance bearing calibration of span of control limit of control, described prime amplifier comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor, a described transistorized source electrode of PMOS connects power supply, and the drain electrode of a described transistorized drain electrode of PMOS and described the 3rd nmos pass transistor is connected, the reverse output voltage of the end output amplifier that is connected; Described the 2nd transistorized source electrode of PMOS connects power supply, and the drain electrode of described the 2nd transistorized drain electrode of PMOS and described the 4th nmos pass transistor is connected, the forward output voltage of the end output amplifier that is connected; The source electrode of described the 3rd nmos pass transistor is connected with the drain electrode of described the 5th nmos pass transistor, and the grid of described the 3rd nmos pass transistor connects the forward input voltage; The source electrode of described the 4th nmos pass transistor is connected with the drain electrode of described the 5th nmos pass transistor, and the grid of described the 4th nmos pass transistor connects reverse input voltage; The source ground of described the 5th nmos pass transistor, the grid of described the 5th nmos pass transistor connects the 3rd control signal; The amplitude initial value of described the 3rd control signal is 0, and steady-state value is supply voltage value VDD; A described transistorized grid of PMOS connects the first control signal, and described the 2nd transistorized grid of PMOS connects the second control signal; Described control method comprises the following steps: before adjusting, the amplitude initial value of controlling described the first control signal and described the second control signal is 0, and steady-state value is supply voltage value VDD; Described forward input voltage and described reverse input power that control inputs equates, when regulating:
The first situation: if imbalance is that described forward output voltage is less than described reverse output voltage, keep the amplitude of described the second control signal constant, regulate in the following manner described the first control signal: 11) set the initial value of adjusting voltage, described initial value is greater than 0, less than VDD; 12) the current number of corrections of new record more, the amplitude initial value of controlling described the first control signal is the value of described adjustment voltage, steady-state value is described supply voltage value VDD; Whether the value that 13) judges current number of corrections equals set point, if not, enters step 14); If so, finish adjustment process; 14) size of judgement described forward output voltage this moment and described reverse output voltage, if described forward output voltage still less than described reverse output voltage, tunes up described adjustment voltage VB, return to step 12); If described forward output voltage greater than described reverse output voltage, is turned described adjustment voltage VB down, return to step 12);
Second case: if imbalance is that described forward output voltage is greater than described reverse output voltage, keep the amplitude of described the first control signal constant, regulate in the following manner described the second control signal: 21) set the initial value of adjusting voltage, described initial value is greater than 0, less than VDD; 22) the current number of corrections of new record more, the amplitude initial value of controlling described the second control signal is the value of described adjustment voltage, steady-state value is described supply voltage value VDD; 23) whether the value of judgement number of corrections this moment equals set point, if not, enters step 24); If so, finish adjustment process; 24) size of judgement described forward output voltage this moment and described reverse output voltage, if described forward output voltage still greater than described reverse output voltage, tunes up described adjustment voltage VB, return to step 22); If described forward output voltage less than described reverse output voltage, is turned described adjustment voltage VB down; Return to step 22).
The beneficial effect that the present invention is compared with the prior art is:
Prime amplifier of the present invention is by the imbalance bearing calibration of span of control limit of control, by the amplitude of the control signal on load pipe the one PMOS transistor MP1 and the 2nd PMOS transistor MP2 grid is regulated control, thereby the conducting resistance of regulating load pipe, and then the electric current that occurs imbalance left and right sides branch road in circuit is not when waiting, can guarantee that also power supply equates to the pressure drop of left and right sides output Nodes, thereby guarantee that output end voltage Voutp and Voutn equate, proofread and correct imbalance.In bearing calibration of the present invention, need to not set up perhaps metal-oxide-semiconductor of controllable electric in preamplifier circuit, therefore can not cause load effect to input terminal voltage.
Description of drawings
Fig. 1 is the circuit structure diagram of prime amplifier in prior art;
Fig. 2 is the sequential chart of the control signal in prime amplifier in prior art;
Fig. 3 is the circuit structure diagram of the prime amplifier in the specific embodiment of the invention;
Fig. 4 regulates the flow chart of the first control signal during for the first imbalance situation in prime amplifier in the specific embodiment of the invention;
Fig. 5 is the sequential chart of the control signal during for the first imbalance situation in prime amplifier in the specific embodiment of the invention;
Fig. 6 regulates the flow chart of the second control signal during for the second imbalance situation in prime amplifier in the specific embodiment of the invention;
Fig. 7 is the sequential chart of the control signal during for the second imbalance situation in prime amplifier in the specific embodiment of the invention.
Embodiment
Below in conjunction with embodiment and contrast accompanying drawing the present invention is described in further details.
In this embodiment, a kind of imbalance bearing calibration of prime amplifier is proposed, be used for existing imbalance in prime amplifier, when having offset voltage to form, when input forward input voltage vin p equals reverse input voltage vin n, output forward output voltage V outp can approach as far as possible and equal reverse output voltage V outn, reduces offset voltage to the impact of circuit.The imbalance bearing calibration for prime amplifier circuit structure diagram as shown in Figure 3, prime amplifier comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor.
Wherein, being connected to each other with identical in prior art of five metal-oxide-semiconductors, the one transistorized source electrode MP1 of PMOS connects power vd D, and the drain electrode of a PMOS transistor MP1 is connected with the drain electrode of the 3rd nmos pass transistor MN3, the reverse output voltage V outn of the end output amplifier that is connected; The source electrode of the 2nd PMOS transistor MP2 connects power vd D, and the drain electrode of the 2nd PMOS transistor MP2 is connected with the drain electrode of the 4th nmos pass transistor MN4, the forward output voltage V outp of the end output amplifier that is connected; The source electrode of the 3rd nmos pass transistor MN3 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 3rd nmos pass transistor MN3 connects forward input voltage vin p; The source electrode of the 4th nmos pass transistor MN4 is connected with the drain electrode of the 5th nmos pass transistor MN5, and the grid of the 4th nmos pass transistor MN4 connects reverse input voltage vin n; The source ground of the 5th nmos pass transistor MN5, the grid of the 5th nmos pass transistor MN5 connects the 3rd control signal CLKP.Identical in the 3rd control signal CLKP and prior art, be to produce circuit by control signal to produce according to the clock signal clk of prime amplifier work equally, frequency is identical with the frequency of clock signal clk, and the amplitude initial value is 0, and steady-state value is supply voltage value VDD.The difference that is connected in circuit structure and prior art is: a transistorized grid of PMOS connects the first control signal CLK1, and the 2nd transistorized grid of PMOS connects the second control signal CLK2.To be minute situation carry out continuous amplitude adjustment to one of them of the first control signal CLK1 and the second control signal CLK2 in the imbalance bearing calibration, two control signals that the generation amplitude does not wait are applied on the grid of two load metal-oxide-semiconductors (MP1 and MP2), the correction of realization to offset voltage can not cause load effect to output simultaneously.
Before correction adjustment, the first control signal CLK1 is identical with the 3rd control signal CLKP with the second control signal CLK2, and its amplitude is 0 ~ VDD.The forward input voltage vin p that control inputs equates and reverse input power Vinn, if this moment, there was imbalance in prime amplifier, two kinds of situations can appear, the one, imbalance makes the 3rd nmos pass transistor MN3 flow through less electric current, the 4th nmos pass transistor MN4 flows through larger electric current, and under the identical load resistance of load pipe (MP1 and MP2), the pressure drop on MP1 is less so, oppositely output voltage V outn can be larger, namely Voutp＜Voutn can occur.The 2nd, imbalance makes the 3rd nmos pass transistor MN3 flow through larger electric current, the 4th nmos pass transistor MN4 flows through less electric current, so under the identical load resistance of load pipe (MP1 and MP2), pressure drop on MP1 is larger, oppositely output voltage V outn can be less, namely Voutp＞Voutn can occur.According to these two kinds of situations, take respectively corresponding measure.
Under the first situation, lack of proper care as forward output voltage V outp less than reverse output voltage V outn, keep the amplitude of the second control signal CLK2 constant, regulate in the following manner the first control signal CLK1, the flow chart during adjusting is as shown in Figure 4.Adjustment process comprises the following steps:
11) set the initial value VB1 that adjusts voltage VB.Wherein, initial value VB1 is greater than 0, less than VDD.
12) the current number of corrections of new record is more controlled the amplitude initial value of the first control signal CLK1 for adjusting the value of voltage VB, and steady-state value is supply voltage value VDD.
As shown in Figure 5, be the sequential chart of each control signal under this kind imbalance situation.After regulating the amplitude of the first control signal CLK1, the change in voltage scope of the first control signal CLK1 changes VB ~ VDD into from 0 ~ VDD before, and the absolute value of the gate source voltage of load pipe MP1 reduces so, and its electric conduction resistive is large.And current imbalance situation is to make the electric current that flows through on load pipe MP1 less, the grid control signal CLK1 of load pipe MP1 makes the electric conduction resistive of MP1 large after regulating, the less offset influence of electric current has neutralized, make the pressure drop on MP1 become large (being tending towards equating with the upper pressure drop of MP2), make reverse output voltage V outn diminish, make two output end voltages be tending towards equal, improve imbalance.Timing for the first time, current number of corrections is 1, the amplitude initial value of the first control signal CLK1 is initial value VB1.During second-order correction, current number of corrections is 2, and the amplitude initial value of the first control signal CLK1 is the value VB2 that returns after follow-up adjustment.The rest may be inferred, until last timing, current number of corrections is set point N, and the amplitude initial value of the first control signal CLK1 is the value VBN that returns after follow-up adjustment, after this finishes to adjust, and the amplitude initial value keeps VBN constant.
Whether the value that 13) judges current number of corrections equals set point, if not, enters step 14); If so, finish adjustment process.
In this step, set the judgement of number of corrections, when in step 12), more the number of corrections of new record arrives predefined set point N time, represent that namely correction adjustment has reached user's instructions for use, thereby finish correction.Value VBN when after this amplitude initial value of the first control signal CLK1 being remained last the adjusting.Number of corrections set point N is set up on their own according to speed and the required precision of proofreading and correct of lacking of proper care by the user of prime amplifier.
14) judgement forward output voltage V outp this moment and the oppositely size of output voltage V outn, if forward output voltage V outp is still less than reverse output voltage V outn, the correction adjustment that represents to lack of proper care this moment is not yet in place, to adjust voltage VB tunes up, return to step 12), thereby continue to reduce the gate source voltage of load pipe MP1, continue to increase the conducting resistance of MP1, manage the less offset influence of side electric current with MP1 further, until reach the number of corrections of setting.If forward output voltage V outp is greater than reverse output voltage V outn, the correction adjustment that represents to lack of proper care this moment has been crossed Best Point, arrived another imbalance situation, will adjust voltage VB turns down, return to step 12), make the value of the VB that the both sides output voltage is tending towards equating with searching, until reach the number of corrections of setting.
In the adjustment process of above-mentioned control signal, only regulate the amplitude of the first control signal CLK1, frequency is to determine according to the clock signal clk of described prime amplifier, and is the same with the frequency of clock signal clk.
Preferably, in step 11), the initial value of adjusting voltage VB be made as offset voltage to be corrected interval peaked half, when tuning up VB in step 14) or turning VB down, all get interval median.For example, for prime amplifier, after circuit connects, be 0～2/3VDD between its imbalance correction zone, the initial value of adjusting voltage VB can be made as half 1/3VDD of 2/3VDD, need to tune up VB after 1/3 VDD, get VB and be the VDD of the median 1/2 of interval (1/3VDD, 2/3VDD); Need to turn down VB after 1/2 VDD, get VB and be the VDD of the median 5/12 of interval (1/3VDD, 1/2VDD), the like.The method of median is got in employing can accelerate adjustment process.
By above-mentioned control, realized that namely input pipe MN3 pipe flows through small electric stream under the first imbalance situation, produce output voltage V outn on the larger conducting resistance of load pipe MP1; Input pipe MN4 pipe flows through larger electric current, produce output voltage V outp on the less resistive of load pipe MP2, make the pressure drop of power vd D after overload pipe MP1 be tending towards equating with pressure drop after overload MP2 after repeatedly regulating, reach output voltage forward output voltage V outp and be tending towards equaling reverse output voltage V outn, thereby reduce even to have eliminated the offset voltage impact of prime amplifier.
Under second case, lack of proper care as forward output voltage V outp greater than reverse output voltage V outn, keep the amplitude of the first control signal CLK1 constant, regulate in the following manner the second control signal CLK2, the flow chart during adjusting is as shown in Figure 6.Adjustment process comprises the following steps:
21) set the initial value VB1 that adjusts voltage VB.Wherein, initial value VB1 is greater than 0, less than VDD.
22) the current number of corrections of new record is more controlled the amplitude initial value of the second control signal CLK2 for adjusting the value of voltage VB, and steady-state value is supply voltage value VDD.As shown in Figure 7, be the sequential chart of each control signal under this kind imbalance situation.After regulating the amplitude of the second control signal CLK2, the change in voltage scope of the second control signal CLK2 changes VB ~ VDD into from 0 ~ VDD before, and the absolute value of the gate source voltage of load pipe MP2 reduces so, and its electric conduction resistive is large.And current imbalance situation is to make the electric current that flows through on load pipe MP2 less, the grid control signal CLK2 of load pipe MP2 makes the electric conduction resistive of MP2 large after regulating, the less offset influence of electric current has neutralized, make the pressure drop on MP2 become large (being tending towards equating with the upper pressure drop of MP1), make forward output voltage V outp diminish, make two output end voltages be tending towards equal, improve imbalance.Similarly, timing for the first time, current number of corrections is 1, the amplitude initial value of the second control signal CLK2 is initial value VB1.During second-order correction, current number of corrections is 2, and the amplitude initial value of the second control signal CLK2 is the value VB2 that returns after follow-up adjustment.The rest may be inferred, until last timing, current number of corrections is set point N, and the amplitude initial value of the second control signal CLK2 is the value VBN that returns after follow-up adjustment, after this finishes to adjust, and the amplitude initial value keeps VBN constant.
Whether the value that 23) judges current number of corrections equals set point, if not, enters step 24); If so, finish adjustment process.Similarly, number of corrections set point N is set up on their own according to speed and the required precision of proofreading and correct of lacking of proper care by the user of prime amplifier.
24) judgement forward output voltage V outp this moment and the oppositely size of output voltage V outn, if forward output voltage V outp is still greater than reverse output voltage V outn, the correction adjustment that represents to lack of proper care this moment is not yet in place, to adjust voltage VB tunes up, return to step 22), thus continue to reduce the gate source voltage of load pipe MP2, continue to increase the conducting resistance of MP2, manage the less offset influence of side electric current with MP2 further, until reach the number of corrections of setting.Correction adjustment has been crossed Best Point if forward output voltage V outp less than reverse output voltage V outn, represents to lack of proper care this moment, has arrived another imbalance situation, will adjust voltage VB and turn down; Return to step 22), make the value of the VB that the both sides output voltage is tending towards equating with searching, until reach the number of corrections of setting.
Similarly, in the adjustment process of above-mentioned control signal, only regulate the amplitude of the second control signal CLK2, frequency is to determine according to the clock signal clk of described prime amplifier, and is the same with the frequency of clock signal clk.
Equally preferably, step 21) in, the initial value of adjusting voltage VB be made as offset voltage to be corrected interval peaked half, step 24) in when tuning up VB or turning VB down, all get interval median, can accelerate adjustment process.
By above-mentioned control, realized that namely input pipe MN3 pipe flows through larger electric current under the second imbalance situation, produce output voltage V outn on the less conducting resistance of load pipe MP1; Input pipe MN4 pipe flows through small electric stream, produce output voltage V outp on the larger resistance of load pipe MP2, make the pressure drop of power vd D after overload pipe MP1 be tending towards equating with pressure drop after overload MP2 after repeatedly regulating, reach output voltage forward output voltage V outp and be tending towards equaling reverse output voltage V outn, thereby reduce even to have eliminated the offset voltage impact of prime amplifier.
The imbalance bearing calibration of this embodiment, according to above-mentioned adjustment process as can be known: the first, the comparative result (magnitude relationship of Voutp and Voutn) during according to the first control signal that applies same magnitude before proofreading and correct and the second control signal determines to need to adjust the first control signal CLK1 or the second control signal CLK2.After determining, the control signal that does not need to adjust will remain unchanged in the trimming process of back, and the control signal that needs to adjust will continue to regulate the change amplitude in the trimming process of back, until whole trimming process finishes.The second, do not need the signal of adjusting range should be identical with the 3rd control signal CLKP in trimming process, its amplitude range is always 0 ~ VDD, therefore can share a signal generating circuit; Need the signal of adjusting range to compare with the CLKP signal variation that should only have on amplitude, for example final amplitude range is VB ~ VDD(VB〉0), signal generating circuit can get final product on the basis of the 3rd control signal generation circuit in increasing degree control.The 3rd, for prime amplifier shown in Figure 3, in order to guarantee its normal operation, MP3 and MP4 need and can turn-off fully, so the maximum of CLK1 and CLK2 signal is VDD.
The imbalance bearing calibration of this embodiment, control the amplitude of the control signal of two load metal-oxide-semiconductors of prime amplifier (MP1 and MP2) grid, make the conducting state of two load metal-oxide-semiconductors different, the equivalent conduction impedance that namely means them is different, namely different to the load effect of input pipe, thus realization is to the correction of prime amplifier input offset voltage.Need to not set up perhaps metal-oxide-semiconductor of controllable electric in preamplifier circuit in the imbalance trimming process, therefore can not cause load effect to input terminal voltage, thereby the imbalance timing also can be guaranteed the speed of amplifier.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, make without departing from the inventive concept of the premise some substituting or obvious modification, and performance or purposes identical, all should be considered as belonging to protection scope of the present invention.
Claims (3)
1. a prime amplifier is by the imbalance bearing calibration of span of control limit of control, described prime amplifier comprises a PMOS transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the 5th nmos pass transistor, a described transistorized source electrode of PMOS connects power supply, and the drain electrode of a described transistorized drain electrode of PMOS and described the 3rd nmos pass transistor is connected, the reverse output voltage (Voutn) of the end output amplifier that is connected; Described the 2nd transistorized source electrode of PMOS connects power supply, and the drain electrode of described the 2nd transistorized drain electrode of PMOS and described the 4th nmos pass transistor is connected, the forward output voltage (Voutp) of the end output amplifier that is connected; The source electrode of described the 3rd nmos pass transistor is connected with the drain electrode of described the 5th nmos pass transistor, and the grid of described the 3rd nmos pass transistor connects forward input voltage (Vinp); The source electrode of described the 4th nmos pass transistor is connected with the drain electrode of described the 5th nmos pass transistor, and the grid of described the 4th nmos pass transistor connects reverse input voltage (Vinn); The source ground of described the 5th nmos pass transistor, the grid of described the 5th nmos pass transistor connects the 3rd control signal (CLKP); The amplitude initial value of described the 3rd control signal (CLKP) is 0, and steady-state value is supply voltage value VDD;
It is characterized in that: a described transistorized grid of PMOS connects the first control signal (CLK1), and described the 2nd transistorized grid of PMOS connects the second control signal (CLK2); Described control method comprises the following steps: before adjusting, the amplitude initial value of controlling described the first control signal (CLK1) and described the second control signal (CLK2) is 0, and steady-state value is supply voltage value VDD; Described forward input voltage (Vinp) and described reverse input power (Vinn) that control inputs equates, when regulating:
The first situation: if imbalance is that described forward output voltage (Voutp) is less than described reverse output voltage (Voutn), keep the amplitude of described the second control signal (CLK2) constant, regulate in the following manner described the first control signal (CLK1): 11) set the initial value of adjusting voltage (VB), described initial value is greater than 0, less than VDD; 12) the current number of corrections of new record more, the amplitude initial value of controlling described the first control signal (CLK1) is the value of described adjustment voltage (VB), steady-state value is described supply voltage value VDD; Whether the value that 13) judges current number of corrections equals set point, if not, enters step 14); If so, finish adjustment process; 14) size of judgement described forward output voltage this moment (Voutp) and described reverse output voltage (Voutn), if described forward output voltage (Voutp) is still less than described reverse output voltage (Voutn), described adjustment voltage VB is tuned up, return to step 12); If described forward output voltage (Voutp) greater than described reverse output voltage (Voutn), is turned described adjustment voltage VB down, return to step 12);
Second case: if imbalance is that described forward output voltage (Voutp) is greater than described reverse output voltage (Voutn), keep the amplitude of described the first control signal (CLK1) constant, regulate in the following manner described the second control signal (CLK2): 21) set the initial value of adjusting voltage (VB), described initial value is greater than 0, less than VDD; 22) the current number of corrections of new record more, the amplitude initial value of controlling described the second control signal (CLK2) is the value of described adjustment voltage (VB), steady-state value is described supply voltage value VDD; 23) whether the value of judgement number of corrections this moment equals set point, if not, enters step 24); If so, finish adjustment process; 24) size of judgement described forward output voltage this moment (Voutp) and described reverse output voltage (Voutn), if described forward output voltage (Voutp) is still greater than described reverse output voltage (Voutn), described adjustment voltage VB is tuned up, return to step 22); If described forward output voltage (Voutp) less than described reverse output voltage (Voutn), is turned described adjustment voltage VB down; Return to step 22).
2. the imbalance bearing calibration of prime amplifier according to claim 1 by span of control limit of control is characterized in that: in described the first situation in step 11) or described second case step 21) in the initial value of adjustment voltage (VB) in being made as between described prime amplifier imbalance correction zone peaked half.
3. the imbalance bearing calibration of prime amplifier according to claim 1 by span of control limit of control is characterized in that: in described the first situation in step 14) or described second case step 24) in all get interval range when tuning up or turning down described adjustment voltage (VB) median.
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| CN201210569383.5A CN103107786B (en) | 2012-12-25 | 2012-12-25 | A kind of prime amplifier is by the offset correction method of span of control limit of control |
| HK13107661.8A HK1180463A1 (en) | 2012-12-25 | 2013-07-01 | An imbalance correction method for preamplifier by controlling amplitude |
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| CN201210569383.5A CN103107786B (en) | 2012-12-25 | 2012-12-25 | A kind of prime amplifier is by the offset correction method of span of control limit of control |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119105A (en) * | 2006-08-04 | 2008-02-06 | 夏普株式会社 | Malajustment emendation, noise detecting apparatus and method, semiconductor device and display device |
| CN201323555Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | Signal preamplifier circuit |
| US20090302895A1 (en) * | 2008-06-04 | 2009-12-10 | Texas Instruments Incorporated | Constant output common mode voltage of a pre-amplifier circuit |
| CN101610070A (en) * | 2008-06-19 | 2009-12-23 | 承景科技股份有限公司 | The method of preamplifier and middle calibrated offset voltage thereof |
| US20100231430A1 (en) * | 2009-03-11 | 2010-09-16 | Nec Electronics Corporation | Amplifier and analog/digital converter |
-
2012
- 2012-12-25 CN CN201210569383.5A patent/CN103107786B/en not_active Expired - Fee Related
-
2013
- 2013-07-01 HK HK13107661.8A patent/HK1180463A1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119105A (en) * | 2006-08-04 | 2008-02-06 | 夏普株式会社 | Malajustment emendation, noise detecting apparatus and method, semiconductor device and display device |
| US20090302895A1 (en) * | 2008-06-04 | 2009-12-10 | Texas Instruments Incorporated | Constant output common mode voltage of a pre-amplifier circuit |
| CN101610070A (en) * | 2008-06-19 | 2009-12-23 | 承景科技股份有限公司 | The method of preamplifier and middle calibrated offset voltage thereof |
| CN201323555Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | Signal preamplifier circuit |
| US20100231430A1 (en) * | 2009-03-11 | 2010-09-16 | Nec Electronics Corporation | Amplifier and analog/digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| HK1180463A1 (en) | 2013-10-18 |
| CN103107786B (en) | 2015-09-02 |
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