CN103095320A - Zero intermediate frequency receiver and direct current leakage suppression method thereof - Google Patents
Zero intermediate frequency receiver and direct current leakage suppression method thereof Download PDFInfo
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- CN103095320A CN103095320A CN2011103337259A CN201110333725A CN103095320A CN 103095320 A CN103095320 A CN 103095320A CN 2011103337259 A CN2011103337259 A CN 2011103337259A CN 201110333725 A CN201110333725 A CN 201110333725A CN 103095320 A CN103095320 A CN 103095320A
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Abstract
The invention discloses a zero intermediate frequency receiver and a direct current leakage suppression method thereof. The zero intermediate frequency receiver direct current leakage suppression method includes: respectively grabbing I route data and Q route data output by a digital-to-analogue conversion (DAC) chip, then respectively computing weighted average values of the grabbed I route data and Q route data to obtain direct current leakage rectifying differences of the I route and the Q route, subtracting respective direct current leakage rectifying differences from the received I route data and Q route data, and namely finishing direct current leakage rectifying of the I/Q data. The rectifying difference values are calculated according to received data in real time and the real-time received data is rectified according to the rectifying difference values, so that the zero intermediate frequency receiver and the direct current leakage suppression method thereof are strong in real time, and the rectifying method is simple and effective.
Description
Technical field
The present invention relates to wireless communication technology field, particularly a kind of zero intermediate frequency reciver and direct current leakage inhibition method thereof.
Background technology
Zero intermediate frequency reciver has that volume is little, cost is low and is easy to that monolithic is integrated etc. an advantage, become a kind of structure that has competitiveness in radio-frequency transmitter, be subject to extensive concern in wireless communication field, but the direct current leakage problem becomes the obstacle that the restriction zero intermediate frequency reciver is used.Direct current leakage directly affects the demodulation of signal, and is especially remarkable on the impact of WCDMA and the demodulation of CDMA2000 signal.In addition, the direct current leakage problem also can affect spuious index in LTE small-signal band.
The zero intermediate frequency modulator of zero intermediate frequency reciver up link self is with the direct current leakage inhibit feature, but it can only be suppressed to direct current leakage-the 40dbm left and right, and this makes an uproar from the up end and requires namely-and also there is a big difference for 120dbm.
Summary of the invention
The embodiment of the present invention has proposed a kind of zero intermediate frequency reciver and direct current leakage inhibition method thereof, to suppress the direct current leakage of zero intermediate frequency reciver.
The direct current leakage inhibition method of embodiment of the present invention zero intermediate frequency reciver comprises step:
Receive and grasp the I/Q data of modulus conversion chip output;
The I circuit-switched data that grasps is summed up be averaging computing, the direct current that obtains the I circuit-switched data is proofreaied and correct difference, simultaneously, the Q circuit-switched data that grasps is summed up be averaging computing, and the direct current that obtains the Q circuit-switched data is proofreaied and correct difference;
The direct current that deducts described I circuit-switched data with the I circuit-switched data that receives from described modulus conversion chip is proofreaied and correct difference, and simultaneously, the direct current of using the Q circuit-switched data that receives from described modulus conversion chip to deduct described Q circuit-switched data is proofreaied and correct difference;
Be sent to fpga chip with deducting I circuit-switched data and the Q circuit-switched data that direct current proofreaies and correct after difference.
Preferably, it is the I circuit-switched data that symbol is arranged that described step sums up to the I circuit-switched data that grasps the I circuit-switched data that is averaging in computing, and it is the Q circuit-switched data that symbol is arranged that described step sums up to the Q circuit-switched data that grasps the Q circuit-switched data that is averaging in computing.
Preferably,
The I/Q data of described step crawl modulus conversion chip output are specially: take 64K as unit, respectively I circuit-switched data and the Q circuit-switched data of modulus conversion chip output are grasped;
Described step sums up the I circuit-switched data of crawl and is averaging computing and is specially: the I circuit-switched data of every 64K of crawl is summed up be averaging successively;
Described step sums up the Q circuit-switched data of crawl and is averaging computing and is specially: the Q circuit-switched data of every 64K of crawl is summed up be averaging successively.
Embodiment of the present invention zero intermediate frequency reciver, its up link comprises filter, amplifier, zero intermediate frequency modulator, modulus conversion chip and the fpga chip that is connected successively, and the radio-frequency (RF) local oscillator that is connected with described zero intermediate frequency modulator, it is characterized in that, also comprise direct current earial drainage correction module between described analog-digital chip and described fpga chip, described direct current leakage correction module comprises:
I circuit-switched data receiver module is used for receiving the I circuit-switched data that described modulus conversion chip is exported;
Q circuit-switched data receiver module is used for receiving the Q circuit-switched data that described modulus conversion chip is exported;
I road signal handling module is used for grasping the I circuit-switched data that described I circuit-switched data receiver module receives;
Q road signal handling module is used for grasping the Q circuit-switched data that described I circuit-switched data receiver module receives;
I road difference calculating module is used for I circuit-switched data to described I road signal handling module crawl and sums up and be averaging, and obtains I road direct current leakage and proofreaies and correct difference;
Q road difference calculating module is used for Q circuit-switched data to described Q road signal handling module crawl and sums up and be averaging, and obtains Q road direct current leakage and proofreaies and correct difference;
I road direct current leakage correction module is used for the I circuit-switched data that described I circuit-switched data receiver module receives is deducted the I road direct current leakage correction difference of described I road difference calculating module calculating, and acquired results is sent to described fpga chip;
Q road direct current leakage correction module is used for the Q circuit-switched data that described Q circuit-switched data receiver module receives is deducted the Q road direct current leakage correction difference of described Q road difference calculating module calculating, and acquired results is sent to described fpga chip.
Preferably,
Described I road difference calculating module sums up for the I circuit-switched data that symbol is arranged to described I road signal handling module crawl and is averaging;
Described Q road difference calculating module sums up for the Q circuit-switched data that symbol is arranged to described Q road signal handling module crawl and is averaging.
Preferably,
Described I road signal handling module and described Q road signal handling module grasp I circuit-switched data and Q circuit-switched data take 64K as unit respectively;
Described I road difference calculating module sums up the I circuit-switched data of every 64K of described I road signal handling module crawl successively and is averaging;
Described Q road difference calculating module sums up the Q circuit-switched data of every 64K of described Q road signal handling module crawl successively and is averaging.
Preferably, described direct current leakage correction module is realized by described fpga chip.
Embodiment of the present invention zero intermediate frequency reciver and direct current leakage inhibition method thereof, grasp respectively I circuit-switched data and the Q circuit-switched data of analog-digital chip output, calculate respectively again the I circuit-switched data of crawl and adding and mean value of Q road, the direct current leakage that obtains I road and Q road is proofreaied and correct difference, the direct current leakage that the I circuit-switched data that receives and Q circuit-switched data deduct is respectively separately proofreaied and correct difference, both completed the direct current leakage of I/Q data and proofreaied and correct.Because being comes the calculation correction difference according to the data that receive, then proofread and correct difference according to this data that receive are proofreaied and correct, so embodiment of the present invention zero intermediate frequency reciver and direct current leakage inhibition method thereof is real-time, and bearing calibration is simply effective.
Description of drawings
Fig. 1 is the schematic flow sheet of zero intermediate frequency reciver direct current leakage inhibition method of the present invention;
Fig. 2 is the structural representation of prior art zero intermediate frequency reciver;
Fig. 3 is the structural representation of zero intermediate frequency reciver of the present invention;
Fig. 4 is the structural representation of direct current leakage correction module in zero intermediate frequency reciver of the present invention.
Embodiment
Suppress the essence of direct current leakage and proofread and correct direct current leakage.The embodiment of the present invention has been carried out the direct current leakage correction to signal at the zero intermediate frequency modulator after, with a kind of simple method, signal has been carried out again a direct current leakage proofreaied and correct.Explain in detail the present invention below in conjunction with accompanying drawing and specific embodiment.
The direct current leakage inhibition method of embodiment of the present invention zero intermediate frequency reciver as shown in Figure 1, comprises step:
Step 1, receive and grasp I/Q (In-phase/Quadrature, the inphase quadrature) data of modulus conversion chip output;
Step 2, the I circuit-switched data of crawl is summed up and is averaging computing, the direct current that obtains the I circuit-switched data is proofreaied and correct difference, simultaneously, the Q circuit-switched data of crawl is summed up be averaging computing, and the direct current that obtains the Q circuit-switched data is proofreaied and correct difference;
Step 3, the direct current of using the I circuit-switched data that receives from described modulus conversion chip to deduct described I circuit-switched data are proofreaied and correct difference, and simultaneously, the direct current of using the Q circuit-switched data that receives from described modulus conversion chip to deduct described Q circuit-switched data is proofreaied and correct difference;
Step 4, will deduct I circuit-switched data and the Q circuit-switched data that direct current proofreaies and correct after difference and be sent to fpga chip.
As seen from the above description, the processing method of I circuit-switched data and Q circuit-switched data is consistent,, take the I circuit-switched data as representative above-mentioned steps is described at this.Modulus conversion chip output I circuit-switched data, this method continues to receive in real time the I circuit-switched data on one side, on one side the I circuit-switched data that receives is grasped, adds and is averaging, proofread and correct difference with the direct current leakage that obtains the I circuit-switched data of real-time reception is proofreaied and correct, each I circuit-switched data that the concrete grammar of correction namely receives in real time deducts I road direct current leakage correction difference.Like this, the I circuit-switched data has just obtained real time correction.
As a preferred embodiment, it is the I circuit-switched data that symbol is arranged that the I circuit-switched data of described step 2 pair crawl sums up the I circuit-switched data that is averaging in computing, and it is the Q circuit-switched data that symbol is arranged that the Q circuit-switched data of described step 2 pair crawl sums up the Q circuit-switched data that is averaging in computing.
When step 1 grasped, once the data of crawl should not too much also should not be very little.As a preferred embodiment, take 64K as unit, respectively I circuit-switched data and the Q circuit-switched data of modulus conversion chip output are grasped.Correspondingly, step 2 be also the 64K data that grasp be one group, it is summed up is averaging computing.Step 3 is proofreaied and correct difference with direct current leakage the data of real-time reception is carried out timing, and what use is all that up-to-date direct current leakage is proofreaied and correct difference at every turn.I/Q data after correction input to abstraction module and the parallel serial conversion module of fpga chip according to normal flow direction.
The zero intermediate frequency reciver of prior art, as shown in Figure 2, its up link comprises filter, amplifier, zero intermediate frequency modulator, modulus conversion chip and the fpga chip that is connected successively, and the radio-frequency (RF) local oscillator that is connected with described zero intermediate frequency modulator.Embodiment of the present invention zero intermediate frequency reciver as shown in Figure 3, has increased the direct current leakage correction module on the architecture basics of prior art zero intermediate frequency reciver, this module is connected between modulus conversion chip and fpga chip, and as shown in Figure 4, it specifically comprises:
I circuit-switched data receiver module is used for receiving the I circuit-switched data that described modulus conversion chip is exported;
Q circuit-switched data receiver module is used for receiving the Q circuit-switched data that described modulus conversion chip is exported;
I road signal handling module is used for grasping the I circuit-switched data that described I circuit-switched data receiver module receives;
Q road signal handling module is used for grasping the Q circuit-switched data that described I circuit-switched data receiver module receives;
I road difference calculating module is used for I circuit-switched data to described I road signal handling module crawl and sums up and be averaging, and obtains I road direct current leakage and proofreaies and correct difference;
Q road difference calculating module is used for Q circuit-switched data to described Q road signal handling module crawl and sums up and be averaging, and obtains Q road direct current leakage and proofreaies and correct difference;
I road direct current leakage correction module is used for the I circuit-switched data that described I circuit-switched data receiver module receives is deducted the I road direct current leakage correction difference of described I road difference calculating module calculating, and acquired results is sent to described fpga chip;
Q road direct current leakage correction module is used for the Q circuit-switched data that described Q circuit-switched data receiver module receives is deducted the Q road direct current leakage correction difference of described Q road difference calculating module calculating, and acquired results is sent to described fpga chip.
By Fig. 3 and above description as can be known, the I circuit-switched data is divided into two-way after being received by I circuit-switched data receiver module, and one the tunnel directly arrives I road direct current leakage correction module, and one the tunnel after I road signal handling module and I road difference calculating module, then enters I road direct current leakage correction module.Embodiment of the present invention zero intermediate frequency reciver to the processing procedure of Q circuit-switched data with consistent to the processing procedure of I circuit-switched data.
As a preferred embodiment, described I road difference calculating module is used for the I circuit-switched data that symbol is arranged to described I road signal handling module crawl and sums up and be averaging; Described Q road difference calculating module sums up for the Q circuit-switched data that symbol is arranged to described Q road signal handling module crawl and is averaging.
As an embodiment preferably, described I road signal handling module and described Q road signal handling module grasp I circuit-switched data and Q circuit-switched data take 64K as unit respectively; Described I road difference calculating module sums up the I circuit-switched data of every 64K of described I road signal handling module crawl successively and is averaging; Described Q road difference calculating module sums up the Q circuit-switched data of every 64K of described Q road signal handling module crawl successively and is averaging.
For the simplified receiver structure, above-mentioned direct current leakage correction module is realized in described fpga chip.
Above-described embodiment of the present invention does not consist of the restriction to protection range of the present invention.Any modification of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in claim protection range of the present invention.
Claims (7)
1. the direct current leakage inhibition method of a zero intermediate frequency reciver, is characterized in that, comprises step:
Receive and grasp the I/Q data of modulus conversion chip output;
The I circuit-switched data that grasps is summed up be averaging computing, the direct current that obtains the I circuit-switched data is proofreaied and correct difference, the Q circuit-switched data that grasps is summed up be averaging computing, and the direct current that obtains the Q circuit-switched data is proofreaied and correct difference;
The direct current that deducts described I circuit-switched data with the I circuit-switched data that receives from described modulus conversion chip is proofreaied and correct difference, and simultaneously, the direct current of using the Q circuit-switched data that receives from described modulus conversion chip to deduct described Q circuit-switched data is proofreaied and correct difference;
With I circuit-switched data and the transmission of Q circuit-switched data that deducts after direct current is proofreaied and correct difference.
2. the direct current leakage inhibition method of zero intermediate frequency reciver according to claim 1, it is characterized in that, it is the I circuit-switched data that symbol is arranged that the I circuit-switched data that grasps is summed up the I circuit-switched data that is averaging in computing, and it is the Q circuit-switched data that symbol is arranged that the Q circuit-switched data that grasps is summed up the Q circuit-switched data that is averaging in computing.
3. the direct current earial drainage inhibition method of zero intermediate frequency reciver according to claim 1 and 2, is characterized in that,
The I/Q data of crawl modulus conversion chip output are specially: take 64K as unit, respectively I circuit-switched data and the Q circuit-switched data of modulus conversion chip output are grasped;
The I circuit-switched data of crawl is summed up be averaging computing and be specially: the I circuit-switched data of every 64K of crawl is summed up be averaging successively;
The Q circuit-switched data of crawl is summed up be averaging computing and be specially: the Q circuit-switched data of every 64K of crawl is summed up be averaging successively.
4. zero intermediate frequency reciver, its up link comprises filter, amplifier, zero intermediate frequency modulator, modulus conversion chip and the fpga chip that is connected successively, and the radio-frequency (RF) local oscillator that is connected with described zero intermediate frequency modulator, it is characterized in that, also comprise direct current earial drainage correction module between described analog-digital chip and described fpga chip, described direct current leakage correction module comprises:
I circuit-switched data receiver module is used for receiving the I circuit-switched data that described modulus conversion chip is exported;
Q circuit-switched data receiver module is used for receiving the Q circuit-switched data that described modulus conversion chip is exported;
I road signal handling module is used for grasping the I circuit-switched data that described I circuit-switched data receiver module receives;
Q road signal handling module is used for grasping the Q circuit-switched data that described I circuit-switched data receiver module receives;
I road difference calculating module is used for I circuit-switched data to described I road signal handling module crawl and sums up and be averaging, and obtains I road direct current leakage and proofreaies and correct difference;
Q road difference calculating module is used for Q circuit-switched data to described Q road signal handling module crawl and sums up and be averaging, and obtains Q road direct current leakage and proofreaies and correct difference;
I road direct current leakage correction module is used for the I circuit-switched data that described I circuit-switched data receiver module receives is deducted the I road direct current leakage correction difference of described I road difference calculating module calculating, and acquired results is sent to described fpga chip;
Q road direct current leakage correction module is used for the Q circuit-switched data that described Q circuit-switched data receiver module receives is deducted the Q road direct current leakage correction difference of described Q road difference calculating module calculating, and acquired results is sent to described fpga chip.
5. zero intermediate frequency reciver according to claim 4, is characterized in that,
Described I road difference calculating module sums up for the I circuit-switched data that symbol is arranged to described I road signal handling module crawl and is averaging;
Described Q road difference calculating module sums up for the Q circuit-switched data that symbol is arranged to described Q road signal handling module crawl and is averaging.
6. according to claim 4 or 5 described zero intermediate frequency recivers, is characterized in that,
Described I road signal handling module and described Q road signal handling module grasp I circuit-switched data and Q circuit-switched data take 64K as unit respectively;
Described I road difference calculating module sums up the I circuit-switched data of every 64K of described I road signal handling module crawl successively and is averaging;
Described Q road difference calculating module sums up the Q circuit-switched data of every 64K of described Q road signal handling module crawl successively and is averaging.
7. according to claim 4 or 5 described zero intermediate frequency recivers, is characterized in that, described direct current leakage correction module is realized by described fpga chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108736913A (en) * | 2018-05-11 | 2018-11-02 | 深圳国人通信股份有限公司 | The calibration method and system of the DC component of zero intermediate frequency transceiving chip |
| CN109525268A (en) * | 2018-12-27 | 2019-03-26 | 中国电子科技集团公司第七研究所 | A kind of pair of zero intermediate frequency receives the bearing calibration of signal |
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| US20050025041A1 (en) * | 2003-07-14 | 2005-02-03 | Stefano Marsili | DC offset estimation and compensation in OFDM radio receivers by weighted averaging over a section of the training sequence |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108736913A (en) * | 2018-05-11 | 2018-11-02 | 深圳国人通信股份有限公司 | The calibration method and system of the DC component of zero intermediate frequency transceiving chip |
| CN109525268A (en) * | 2018-12-27 | 2019-03-26 | 中国电子科技集团公司第七研究所 | A kind of pair of zero intermediate frequency receives the bearing calibration of signal |
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Application publication date: 20130508 |