CN103095297A - Direct digital frequency synthesizer method for generating accurate frequency - Google Patents

Abstract

The invention provides a direct digital frequency synthesizer method for generating accurate frequency. With the direct digital frequency synthesizer method, accurate frequency can still be generated when frequency control word (Fword) calculated according to a formula is a decimal due to the fact that the generated output frequency fo is randomly valued. In the formula, fo is the output frequency, fs is the input system clock frequency, N is the work length of a phase accumulator, and Fword is frequency control word of the output frequency. The direct digital frequency synthesizer method is realized by means of the following technical scheme: the direct digital frequency synthesizer in the method is based on a traditional direct digital frequency synthesizer, adopts a specially designed frequency word sequence register to replace a fixed-frequency register, and substantially comprises a frequency word sequence register, a phase accumulator, a phase register, a waveform lookup table, a digital-to-analog converter and a low pass filter. By means of the direct digital frequency synthesizer method, the problem that accurate output frequency fo cannot be generated in the prior art when the calculated frequency control word is a decimal is resolved.

Description

Direct Digital Frequency Synthesizers produces the method for accurate frequency

Technical field

The present invention relates to a kind of being mainly used in high accuracy navigation and high accuracy domain of telemetry, direct synthesizer produces straight extended code frequency or IF-FRE by system clock, as the frequency control word F that calculates _WordDuring for decimal, Direct Digital Frequency Synthesizers still can produce the method for accurate frequency

Background technology

Direct synthesizer DDS frequency synthesis technique is the signal of a series of digital quantity forms to be converted to the signal of analog quantity form by D/A converter, DDS is a kind of high-resolution digital frequency divider in essence, come the frequency division system clock by the frequency adjustment word, to export required frequency.The structure of DDS has a variety of, and its basic circuit theory mainly is comprised of fixed frequency word register, phase accumulator, phase register, waveform look-up table, analog to digital converter, low pass filter as shown in Figure 2, and wherein, DDS is at clock signal of system f _sControl under, by the phase accumulator output phase code of being controlled by frequency control word, the waveform quantization sampled data value that is stored in wave memorizer is read according to certain rules output waveform after D/A conversion and low-pass filtering.

In prior art shown in Figure 2, the frequency f of DDS output signal _oWith input system clock frequency f _sAnd frequency control word F _WordBetween relational expression:

$F_{\mathrm{word}}=\frac{f_o}{f_s}\×2^N---\left(1\right)$

Wherein, f _oThe DDS output frequency, f _sBe the DDS incoming frequency, N is the figure place of phase accumulator, and frequency control word is F _Wordf _oThe frequency that known needs produce, f _s, 2 ^NBe all also known, can calculate frequency control word F by formula (1) _Word, the F that calculates _WordIt may be the mixed decimal value, but the frequency control word that Direct Digital Frequency Synthesizers is used is integer, must round, therefore, just have data to accept or reject, the output frequency that obtains at last just and needed frequency certain error is arranged, produce error when causing finally using the phase ranging of this clock signal, traditional Direct Digital Frequency Synthesizers cause distance measurement value unavailable after the accumulation of error, so can not produce clock signal accurately.Therefore, when above-mentioned prior art produces the output signal of optional frequency at needs, if asked the frequency control word F that calculates by formula (1) _WordTraditional Direct Digital Frequency Synthesizers is decimal, can not produces accurate output frequency, so can't be completed required requirement.

In high accuracy navigation and high accuracy domain of telemetry, need to use the code phase of straight extended code or the carrier phase of carrier wave to find range, still, frequency control word F _WordDuring for decimal, the frequency that produces by Direct Digital Frequency Synthesizers with a fixing integer frequency control word, with the frequency residual error, not frequency very accurately, when finding range, just have the accumulation of range error, increase along with the time, the error of accumulation can be increasing, and the result that causes finding range is unavailable, and the method that makes existing Direct Digital Frequency Synthesizers produce frequency can not adapt to frequency control word F _WordUnder little said conditions, need to be with the occasion of code phase or carrier phase range finding.

Summary of the invention

The objective of the invention is the weak point for existing Direct Digital Frequency Synthesizers technology existence, a kind of frequency control word F that calculates is provided _WordDuring for decimal numerical value, still can produce accurate output frequency and there is no the method for frequency residual error, can not produce the problem of accurate frequency to solve existing Direct Digital Frequency Synthesizers this moment.

The present invention solves the scheme that the prior art problem adopts: a kind of Direct Digital Frequency Synthesizers produces the method for accurate frequency, it is characterized in that comprising the steps: in the basic circuit of Direct Digital Frequency Synthesizers, adopt a frequency word sequential register to replace the fixed frequency register, and press following Design with Rule frequency word sequence: (1) frequency control word F _WordDuring for decimal, this decimal accurately is converted into, by k integer F _Word1, F _Word2F _WordkThe sequence length that forms is the integer sequence F of K ₁, F ₂F _KAverage, to satisfy sequence F ₁, F ₂F _KSerial mean and decimal F _WordFully equal; (2) with integer F _Word1, F _Word2F _WordkBe chosen for decimal F _WordNear integer; (3) with integer F _WordThe distribution of evenly scattering of position in sequence reaches K length sequences F ₁, F ₂F _KIn the average of arbitrary segment as far as possible near decimal F _Word, then with the F that designs ₁, F ₂F _KSequence is stored in the frequency word sequential register, and each frequency control word that reads in order circularly in this sequence goes to add up with phase accumulator, make output frequency and the frequency that needs identical, wherein k is＞1 integer, K is ≮ integer of k.

The present invention has following beneficial effect than prior art: the present invention is on the basis of traditional Direct Digital Frequency Synthesizers, replace the frequency control word fixed by design frequency word sequence, make the average of this frequency word sequence of design equal to ask according to formula (1) the fractional frequency control word that calculates, then each frequency control word that reads in order circularly in this sequence goes to add up with phase accumulator, the frequency that makes output frequency and need is identical, no longer includes the frequency residual error that traditional Direct Digital Frequency Synthesizers produces.Control circuit of the present invention is simple, flexible configuration, and the resource that takies is few, uses simply, and cost is lower, and reliability is high, there is no the frequency residual error.

The present invention reaches the effect of accurate control output frequency by reasonable design frequency control word sequence, makes output frequency identical with the frequency that will obtain, and the invention solves as the frequency control word F that calculates _WordDuring for decimal, prior art can not produce output frequency f accurately _oProblem.

Description of drawings

Below in conjunction with drawings and Examples, this patent is further illustrated.

Fig. 1 is the Direct Digital Frequency Synthesizers schematic block circuit diagram that the present invention produces accurate frequency.

Fig. 2 is the schematic block circuit diagram of existing Direct Digital Frequency Synthesizers.

Embodiment

Consult Fig. 1, in a most preferred embodiment described below, existing Direct Digital Frequency Synthesizers is shown in Figure 2, mainly comprises: fixed frequency word register, phase accumulator, phase register, waveform look-up table, digital to analog converter and low pass filter.The present embodiment Direct Digital Frequency Synthesizers mainly comprises frequency word sequential register, phase accumulator, phase register, waveform look-up table, digital to analog converter and low pass filter, this Direct Digital Frequency Synthesizers is on the basis of traditional Direct Digital Frequency Synthesizers, adopts a frequency word sequential register to replace the fixed frequency register.When design frequency word sequence, need to satisfy following several rules: 1. frequency control word sequence (F ₁, F ₂, F _K) serial mean and F _WordFully equal; 2. the integer frequency control word need to be chosen for F _WordNear integer is usually only with two different integer frequency control words, i.e. F _Word1And F _Word2, value is decimal F respectively _WordOn round integer and decimal F _WordUnder round integer; 3. the position of integer frequency control word in the sequence distribution of should evenly scattering as much as possible reaches the average of arbitrary segment in K length frequency control word sequence also as far as possible near decimal F _WordEffect, for example, frequency control word sequence (F ₁, F ₂, F _K) in, F _Word1Account for J, F _Word2Account for K-J, wherein J is the integer between 1 to K, allows F during sequences Design ₁,

$F_{1+\mathrm{round}(\frac{K}{J}\×2)},......,F_{1+\mathrm{round}(\frac{K}{J}\×(J-1))}$ This J position assignment is F _Word1, remaining position assignment is F _Word2, wherein round is the round function, so the frequency word sequence of design has guaranteed F _Word1And F _Word2The distribution of evenly scattering in sequence.

The design instantiation of frequency word sequence is as follows:

If system clock frequency f _sBe 90MHz, produce a f by Direct Digital Frequency Synthesizers _oThe clock frequency signal of=10.23MHz, phase accumulator bit wide N gets 32, passes through formula

The frequency control word that calculates is infinite decimal, F _Word=488194615.9786666, the part fraction representation after decimal point is

And then carry out the frequency word sequences Design according to above-mentioned three design rules: at first by second, choose two frequency control word composition sequences, F _Word1And F _Word2Value is decimal F respectively _WordOn round integer and decimal F _WordUnder round integer, i.e. F _Word1=488194616, F _Word2=488194615; By article one, the implementation sequence length K is taken as 375, F again _Word1Number J=367 in sequence, F _Word2Number in sequence is (K-J)=8, the substitution formula

Calculate, obtaining this serial mean is 488194615.9786666, satisfies the second rule; Determine the position by the 3rd rule at last, advanced row-coordinate calculates,

$1+\mathrm{round}(\frac{K}{K-J}\×2)=95,$ $1+\mathrm{round}(\frac{K}{K-J}\×3)=142,$ $1+\mathrm{round}(\frac{K}{K-J}\×4)=189,$

$1+\mathrm{round}(\frac{K}{K-J}\×5)=235,$ $1+\mathrm{round}(\frac{K}{K-J}\×6)=282,$ $1+\mathrm{round}(\frac{K}{K-J}\×7)=329,$ Again to sequence permutation, allow F ₁, F ₄₈, F ₉₅, F ₁₄₂, F ₁₈₉, F ₂₃₅, F ₂₈₂, F ₃₂₉These 8 position assignment are F _Word2=488194615,367 remaining whole assignment in position are F _Word1=488194616, the sequence of design has just reached 488194616 and 488194615 distributions of evenly scattering in whole sequence like this.

After designing the frequency word sequence, the sequence that designs is stored in the frequency word sequential register, in the system clock cycle of a 90MHz, a frequency control word in reading frequency word sequence carries out one-accumulate to phase accumulator, in second 90MHz system clock cycle, read in order next frequency control word and add up to phase accumulator in the frequency word sequence, so circularly in order in the frequency word sequence reading frequency control word add up to phase accumulator.Form a kind of Direct Digital Frequency Synthesizers that produces accurate 10.23MHz frequency signal through follow-up phase register, waveform look-up table, digital to analog converter, low pass filter again.

Claims (4)

1. a Direct Digital Frequency Synthesizers produces the method for accurate frequency, it is characterized in that comprising the steps: in the basic circuit of Direct Digital Frequency Synthesizers, adopt a frequency word sequential register to replace the fixed frequency register, and press following Design with Rule frequency word sequence: (1) frequency control word F _WordDuring for decimal, this decimal accurately is converted into, by k integer F _Word1, F _Word2F _WordkThe sequence length that forms is the integer sequence F of K ₁, F ₂F _KAverage, i.e. sequence f ₁, f ₂F _kSerial mean and decimal F _WordFully equal; (2) with integer F _Word1, F _Word2F _WordkBe chosen for decimal F _WordNear integer; (3) with integer F _Word1, F _Word2F _WordkThe distribution of evenly scattering of position in sequence reaches K length F ₁, f ₂F _KIn sequence, the average of arbitrary segment is as far as possible near decimal F _WordThen with the F that designs ₁, F ₂F _KSequence is stored in the frequency word sequential register, each frequency control word that reads in order circularly in this sequence goes to add up with phase accumulator, the frequency that makes the frequency of generation and need is identical, and wherein k is＞1 integer, and K is ≮ integer of k.

2. produce the method for accurate frequency by Direct Digital Frequency Synthesizers claimed in claim 1, it is characterized in that frequency control word sequence (F ₁, F ₂, F _K) serial mean and decimal F _WordFully equal.

3. produce the method for accurate frequency by Direct Digital Frequency Synthesizers claimed in claim 1, it is characterized in that the integer frequency control word is taken as two usually, i.e. F _Word1And F _Word2, value is decimal F respectively _WordOn round integer and decimal F _WordUnder round integer.

4. produce the method for accurate frequency by the described Direct Digital Frequency Synthesizers of claim 1 or 3, it is characterized in that frequency control word sequence (f ₁, F ₂, F _K) in, F _Word1Account for J, F _Word2Account for K-J, wherein J is the integer between 1 to K, allows F during sequences Design ₁, $F_{1+\mathrm{round}(\frac{K}{J}\×2)},......,F_{1+\mathrm{round}\left(\frac{K}{J}(J-1)\right)}$ This J position assignment is F _Word1, remaining position assignment is F _Word2, wherein round is the round function, is used for guaranteeing F _Word1And F _Word2The distribution of evenly scattering in the frequency control word sequence.

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